7

SEQUENTIAL
LOGIC DESIGN
PRINCIPLES

E X E R C I S E S O L U T I O N S
7.2
S

/Q

7.3 The latch oscillates if S and R are negated simultaneously. Many simulator programs will exhibit this same
behavior when confronted with such input waveforms.

/Q

A–124
 EXERCISE SOLUTIONS A–125

7.4

EN Q Q
D
T Q /Q
CLK

7.5

J
EN Q Q
K
T Q /Q
CLK

7.8 Just tie the J and /K inputs together and use as the D input.
7.9 Excitation and output equations:
D1 = Q1′ + Q2
D2 = Q2′ ⋅ X
Z = Q1 + Q2′

Excitation/transition table; state/output table:

EN EN
Q1 Q2 0 1 S 0 1 Z

00 10 11 A C D 1
01 10 10 B C C 0
10 00 01 C A B 1
11 10 10 D C C 1
Q1∗ Q2∗ S∗

7.10 Excitation and output equations:

D1 = Q1′ ⋅ Q2
D2 = Q2′ + X
Z = Q1 ⋅ Q2′

Excitation/transition table; state/output table:

EN EN
Q1 Q2 0 1 S 0 1 Z

00 01 01 A B B 0
01 10 11 B C D 0
10 01 01 C B B 1
11 00 01 D A B 0
Q1∗ Q2∗ S∗

The concept of duality does not apply to state tables.

A–126 SEQUENTIAL LOGIC DESIGN PRINCIPLES CH. 7

7.15 Excitation equations:

D2 = (Q1⊕Q0)⊕(Q1′ ⋅ Q2′)
D1 = Q2
D0 = Q1

Excitation/transition table; state table:

Q2 Q1 Q0 Q2∗ Q1∗ Q0∗ S S∗

000 100 A E
001 000 B A
010 101 C F
011 001 D B
100 010 E C
101 110 F G
110 111 G H
111 011 H D

7.16 Excitation equations:

D1 = X
D2 = Q1 ⋅ Y + Q3′
D3 = (Q2′ + Y) ⋅ Q1′

Excitation/transition table; state table:

XY XY
Q1 Q2 Q3 00 01 10 11 S 00 01 10 11
000 011 011 111 111 A D D H H
001 001 001 101 101 B B B F F
010 010 011 111 110 C C D H G
011 000 001 101 100 D A B F E
100 010 010 110 110 E C C G G
101 000 010 110 100 F A C G E
110 010 010 110 110 G C C G G
111 000 010 110 100 H A C G E

Q1∗ Q2∗ Q3∗ S∗

7.17 Excitation equations:

J1 = X
K1 = Q2′
J2 = X
K2 = Q1

Note that the characteristic equation for a J-K flip-flop is Q∗ = J ⋅ Q′ + K′ ⋅ Q. Thus, we obtain the following
transition equations:
Q1∗ = X ⋅ Q1′ + Q2 ⋅ Q1
Q2∗ = X ⋅ Q2′ + Q1′ ⋅ Q2
 EXERCISE SOLUTIONS A–127

Transition table; state table:

X X
Q1 Q2 0 1 S 0 1
00 00 11 A A D
01 01 11 B B D
10 00 01 C A B
11 10 10 D C C

Q1∗ Q2∗ S∗

State diagram:
X=0 X=0
A B

X=1

X=1 X=1
X=0

D C

Timing diagram:

CLK

Q1

Q2

7.18 Excitation and output equations:

J0 = K0 = EN
J1 = K1 = Q0 ⋅ EN
MAX = EN ⋅ Q1 ⋅ Q0

Note that the characteristic equation for a J-K flip-flop is Q∗ = J ⋅ Q′ + K′ ⋅ Q. Thus, we obtain the following
transition equations:
Q0∗ = EN′ ⋅ Q0 + EN ⋅ Q0′
Q1∗ = EN′ ⋅ Q1 + EN ⋅ Q0 ⋅ Q1′ + EN ⋅ Q0′ ⋅ Q1
A–128 SEQUENTIAL LOGIC DESIGN PRINCIPLES CH. 7

Transition/output table; state/output table:

EN EN
Q1 Q0 0 1 S 0 1
00 00,0 01,0 A A,0 B,0
01 01,0 10,0 B B,0 C,0
10 10,0 11,0 C C,0 D,0
11 11,0 00,1 D D,0 A,1

Q1∗ Q0∗, MAX S∗, MAX

State diagram:
EN′ EN′
A B
EN

EN EN
EN

D C
EN′ EN′
Timing diagram:

CLK

EN

Q0

Q1

MAX

7.19 Excitation and output equations:

EN1 = Y
EN2 = X′ ⋅ Y ⋅ Q1
Z = X′ ⋅ Q2′

Note that the characteristic equation for a T flip-flop is Q∗ = EN ⋅ Q′ + EN′ ⋅ Q. Thus, we obtain the following
transition equations:
Q1∗ = Y ⋅ Q1′ + Y1′ ⋅ Q1
Q2∗ = X′ ⋅ Y′ ⋅ Q1 ⋅ Q2′ + (X′ ⋅ Y′ ⋅ Q1)′ ⋅ Q2
 EXERCISE SOLUTIONS A–129

Transition/output table; state/output table:

XY XY
Q1 Q2 00 01 10 11 S 00 01 10 11
00 00, 1 10, 1 00, 0 10, 0 A A, 1 C, 1 A, 0 C, 0
01 01, 0 11, 0 01, 0 11, 0 B B, 0 D, 0 B, 0 D, 0
10 11, 1 00, 1 10, 0 00, 0 C D, 1 A, 1 C, 0 A, 0
11 10, 0 01, 0 11, 0 01, 0 D C, 0 B, 0 D, 0 B, 0
Q1∗ Q2∗, Z S∗, Z

7.20 Refer to the figure to the right. The de- D /S

tails of metastability triggering depend on
Q
the details of the internal circuit timing.
C

/R /Q

For example, suppose that the inverter has nonzero delay, and that /go C and D are 1. Then when D
changes from 1 to 0, both /S and /R will be asserted for a short time. If C changes from 1 to 0 during this
time, then /S and /R will be negated simultaneously; this is analogous to the situation in the previous exercise.
On the other hand, let us assume for the sake of argument that the inverter has zero delay, and that /go
C and D are 1. The feedback loop is in one of the stable states depicted in Figure 7–3. If D is changed from
1 to 0, and assuming that the delays through the NAND gates to /S and /R are equal, the “operating point” of
the feedback loop starts moving toward the other stable state. However, if C is changed to 0 while this is
happening, the circuit may stop halfway at the metastable operating point.
7.21 The minimum setup time is the clock period times the duty cycle. That is, the minimum setup time is the
time that the clock is 1.
7.22 If both /PR and /CLR are asserted simultaneously, both Q and /Q will be 1.
7.23 As shown in Section 7.5.1, the excitation equation for the latch of Figure 7–12 is
Y∗ = C ⋅ D + C′ ⋅ Y + D ⋅ Y
Below, we analyze Figure X7.23 in the same way:

D (C⋅D)′
C⋅D+(((C⋅D)′ ⋅ C)+Y′)′
C Q
Y∗
Y

((C⋅D)′ ⋅ C)′ /Q
((C⋅D)′ ⋅ C)+Y′
 EXERCISE SOLUTIONS A–131

7.30 INIT

INIT

INIT′ ⋅ X
INIT
B INIT′ ⋅ X′ D F INIT′ ⋅ X
Z=0 Z=0 Z=0 INIT′
INIT′ ⋅ X′
INIT INIT′ ⋅ X′

A H
Z=0 Z=1
INIT′ ⋅ X′
INIT′ ⋅ X
C INIT′ ⋅ X E G
Z=0 Z=0 Z=0 INIT′ ⋅ X′
INIT′ ⋅ X
INIT
INIT
INIT′ ⋅ X

INIT

INIT

7.45 A transition table corresponding to the state table is shown below:

AB
Q2 Q1 Q0 00 01 11 10 Z

000 001 001 010 010 0

001 011 011 010 010 0
010 001 001 100 100 0
011 011 011 110 010 1
100 001 101 100 100 1
101 011 011 110 010 1
110 001 101 100 100 1
Q2∗ Q1∗ Q0∗

This table leads to the Karnaugh maps for the excitation logic on the next page, assuming a “minimal cost”
treatment of unused states.
A–132 SEQUENTIAL LOGIC DESIGN PRINCIPLES CH. 7

D0 A A
AB AB
Q1 Q2 00 01 11 10 Q1 Q2 00 01 11 10

00 1 1 0 0 00 1 1 0 0
A′
01 1 1 0 0 01 1 1 0 0
Q2 Q2
11 1 1 0 0 11 d d d d
Q1 Q1
10 1 1 0 0 10 1 1 0 0

Q0=0 B Q0=1 B

Q1′ ⋅ Q2′ ⋅ A
D1 A A
AB AB
Q1 Q2 00 01 11 10 Q1 Q2 00 01 11 10
00 0 0 1 1 00 1 1 1 1

01 0 0 0 0 01 1 1 1 1
Q2 Q2
11 0 0 0 0 11 d d d d
Q1 Q1
10 0 0 0 0 10 1 1 1 1 Q0

Q0=0 B Q0=1 B

Q0′ ⋅ Q2 ⋅ A
D2 A A
AB AB
Q1 Q2 00 01 11 10 Q1 Q2 00 01 11 10
00 0 0 0 0 Q2 ⋅ A ⋅ B 00 0 0 0 0

01 0 0 1 1 01 0 0 1 0
Q2 Q2
11 0 1 1 1 11 d d d d
Q1 Q1
10 0 1 1 1 10 0 0 1 0
Q0′ ⋅ Q1 ⋅ A
Q0=0 B Q0=1 B
Q1 ⋅ A ⋅ B
Q0′ ⋅ Q1 ⋅ B

The resulting excitation equations are

D0 = A′
D1 = Q1′ ⋅ Q2′ ⋅ A + Q0
D2 = Q2 ⋅ A ⋅ B + Q0′ ⋅ Q2 ⋅ A + Q0′ ⋅ Q1 ⋅ A + Q1 ⋅ A ⋅ B + Q0′ ⋅ Q1 ⋅ B

Ignoring inverters, a circuit realization with the new equations requires one 2-input gate, six 3-input gates,
and one 5-input gate. This is more expensive than Figure 7–50, by four gates.
 EXERCISE SOLUTIONS A–133

7.46 Unlike a J-K flip-flop, a T flip-flop has no

“don’t-cares” in its application table:
Q Q∗ EN

0 0 0
0 1 1
1 0 1
1 1 0

7.47 In this application, we would have the

RESET signal force the machine to state AB
A0, and use the state table shown to the
right: S 00 01 11 10 Z

A0 OK0 OK0 A1 A1 0
A1 A0 A0 OK1 OK1 0
OK0 OK0 OK0 OK1 A1 1
OK1 A0 OK0 OK1 OK1 1
S∗

Following the guidelines for state assignment (p. 489 in the text),
we’ll assign 00 to the initial state, and try to minimize the number S Q1 Q0
state variables that change on each transition. In this case, we
can find an assignment in which only one bit changes on every A0 0 0
transition: A1 0 1
OK0 1 0
OK1 1 1
This yields the following transition table:
AB
Q1 Q0 00 01 11 10 Z

00 10 10 01 01 0
01 00 00 11 11 0
10 10 10 11 01 1
11 00 10 11 11 1
Q2∗ Q1∗ Q0∗

By inspection, Z = Q1. Karnaugh maps for the excitation logic are shown next:

A Q1 ⋅ A

D0 A D1 A
AB AB
Q0 Q1 00 01 11 10 Q0 Q1 00 01 11 10

00 0 0 1 1 00 1 1 0 0

01 0 0 1 1 01 0 0 1 1
Q1 Q1
11 0 0 1 1 11 0 1 1 1
Q0 Q0
10 0 0 1 1 10 1 1 1 0

B B
Q1′ ⋅ A′ Q0 ⋅ B
A–134 SEQUENTIAL LOGIC DESIGN PRINCIPLES CH. 7

The corresponding excitation equations are

D0 = A
D1 = Q1 ⋅ A + Q1′ ⋅ A′ + Q0 ⋅ B

Finally, the logic diagram is:

Q1′
A′ D1 Q1
D Q Z
Q1
CLK Q
A
A CLR

Q0
B
B D0 Q0
D Q

CLK Q
CLR

/RESET

CLK

Comparing with Figure 7–50, the cost of the excitation logic is almost the same (the difference is a 2-input
gate vs. a 3-input gate). The big difference is in having one less flip-flop in the new design.
7.49 The new state assignment yields the following
transition/excitation table and Karnaugh maps: XY
Q1 Q2 00 01 11 10 Z

00 00 01 11 01 1
01 01 11 10 11 0
11 11 10 00 10 0
10 10 00 01 00 0
Q1∗ Q2∗ or D1 D2

Q1′ ⋅ Q2 ⋅ X

Q1′ ⋅ Q2 ⋅ Y Q1′ ⋅ X ⋅ Y Q2′ ⋅ X′ ⋅ Y Q2′ ⋅ X ⋅ Y′

D1 X D2 X
XY XY
Q1 Q2 00 01 11 10 Q1 Q2 00 01 11 10
00 0 0 1 0 00 0 1 0 1

Q1 ⋅ X′ ⋅ Y′ 01 0 1 1 1 01 1 0 1 0
Q2 Q2
11 1 0 0 0 11 1 0 1 0
Q1 Q1
10 1 1 0 1 10 0 1 0 1

Y Y
Q1 ⋅ Q2′ ⋅ X′ Q1 ⋅ Q2′ ⋅ Y′ Q2 ⋅ X′ ⋅ Y′ Q2 ⋅ X ⋅ Y
 EXERCISE SOLUTIONS A–135

This yields the following excitation equations:

D1 = Q1′ ⋅ Q2 ⋅ X + Q1′ ⋅ Q2 ⋅ Y + Q1′ ⋅ X ⋅ Y + Q1 ⋅ Q2′ ⋅ X′ + Q1 ⋅ Q2′ ⋅ Y′ + Q1 ⋅ X′ ⋅ Y′
D2 = Q2 ⋅ X ⋅ Y + Q2′ ⋅ X ⋅ Y′ + Q2′ ⋅ X′ ⋅ Y + Q2 ⋅ X′ ⋅ Y′

Compared with the results of original state assigment, these equations require two more 3-input AND gates,
plus a 6-input OR gate inplace of a 4-input one. However, if we are not restricted to a sum-of-products
realization, using the fact that D2 = Q2⊕X⊕Y might make this realization less expensive.
7.50 As far as I know, I was the first person to propose
BUT-flops, and Glenn Trewitt was the first person Y1∗ Y1
Q1
to analyze them, in 1982. To analyze, we break X1
the feedback loops as shown in the figure to the X2 Y2∗ Y2
Q2
right.

The excitation and output equations are

Y1 = [(X1 ⋅ Y1) ⋅(X2 ⋅ Y2)′]′
= X1′ + Y1′ + X2 ⋅ Y2
Y2 = [(X2 ⋅ Y2) ⋅(X1 ⋅ Y1)′]′
= X2′ + Y2′ + X1 ⋅ Y1
Q1 = Y1
Q2 = Y2

The corresponding transition/state table is

X1 X2
Y1 Y2 00 01 11 10

00 11 11 11 11
01 11 10 10 11
11 11 10 11 01
10 11 11 01 01
Y1∗ Y2∗

The two stable total states are circled. Notice that state 00 is unreachable.
When X1 X2 = 00 or 11, the circuit generally goes to stable state 11, with Q1 Q2 = 11. The apparent
oscillation between states 01 and 10 when X1 X2 = 11 may not occur in practice, because it contains a critical
race that tends to force the circuit into stable state 11.
When X1 X2 = 01 or 10, the Q output corresponding to the HIGH input will oscillate, while the other
output remains HIGH.
Whether this circuit is useful is a matter of opinion.