SERVICE MANUAL

Model:

PDP4210EA

Safety Precaution
Technical Specifications
Block Diagram
Circuit Diagram
Basic Operations & Circuit Description
Main IC Specifications
Product Specification of PDP Module
Trouble Shooting Manual of PDP Module
Spare Part List
Exploded View
If you forget your V-Chip Password
Software Upgrade

This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.
Safety Precaution
The lightning flash with arrowhead symbol,
within an equilateral triangle, is intended to
CAUTION alert the user to the presence of uninsulated
“dangerous voltage” within the product’s enclo
RISK OF ELECTRIC SHOCK sure that may be of sufficient magnitude to
DO NOT OPEN constitute a risk of electric shock to persons.

CAUTION: TO REDUCE THE RISK OF The exclamation point within an equilateral

ELECTRIC SHOCK, DO NOT REMOVE COVER triangle is intended to alert the user to the
(OR BACK). NO USER-SERVICEABLE PARTS presence of important operating and
INSIDE. REFER SERVICING TO QUALIFIED maintenance (servicing) instructions in the
SERVICE PERSONNEL ONLY. literature accompanying the appliance.

PRECAUTIONS DURING MAKE YOUR CONTRIBUTION

SERVICING TO PROTECT THE
1. In addition to safety, other parts and ENVIRONMENT
assemblies are specified for conformance with Used batteries with the ISO symbol
such regulations as those applying to spurious
radiation. These must also be replaced only for recycling as well as small accumulators
with specified replacements. (rechargeable batteries), mini-batteries (cells) and
Examples: RF converters, tuner units, antenna starter batteries should not be thrown into the
selection switches, RF cables, noise-blocking garbage can.
capacitors, noise-blocking filters, etc. Please leave them at an appropriate depot.
2. Use specified internal Wiring. Note especially:
WARNING:
1) Wires covered with PVC tubing
2) Double insulated wires
Before servicing this TV receiver, read the
3) High voltage leads
SAFETY INSTRUCTION and PRODUCT
3. Use specified insulating materials for hazardous
SAFETY NOTICE.
live parts. Note especially:
1) Insulating Tape
2) PVC tubing
SAFETY INSTRUCTION
The service should not be attempted by anyone
3) Spacers (insulating barriers)
unfamiliar with the necessary instructions on this
4) Insulating sheets for transistors
apparatus. The following are the necessary
5) Plastic screws for fixing micro switches
instructions to be observed before servicing.
4. When replacing AC primary side components
1. An isolation transformer should be connected in
(transformers, power cords, noise blocking
the power line between the receiver and the
capacitors, etc.), wrap ends of wires securely
AC line when a service is performed on the
about the terminals before soldering.
primary of the converter transformer of the set.
2. Comply with all caution and safety related
provided on the back of the cabinet, inside the
cabinet, on the chassis or picture tube.
3. To avoid a shock hazard, always discharge the
5. Make sure that wires do not contact heat
picture tube's anode to the chassis ground
generating parts (heat sinks, oxide metal film
before removing the anode cap.
resistors, fusible resistors, etc.)
4. Completely discharge the high potential voltage
6. Check if replaced wires do not contact sharply
of the picture tube before handling. The picture
edged or pointed parts.
tube is a vacuum and if broken, the glass will
7. Make sure that foreign objects (screws, solder
explode.
droplets, etc.) do not remain inside the set.
5. When replacing a MAIN PCB in the cabinet, PRODUCT SAFETY NOTICE
always be certain that all protective are
installed properly such as control knobs, Many electrical and mechanical parts in this
adjustment covers or shields, barriers, isolation apparatus have special safety-related
resistor networks etc. characteristics.
6. When servicing is required, observe the original These characteristics are offer passed
lead dressing. Extra precaution should be given unnoticed by visual spection and the protection
to assure correct lead dressing in the high afforded by them cannot necessarily be obtained
voltage area. by using replacement components rates for a
7. Keep wires away from high voltage or high higher voltage, wattage, etc.
tempera ture components. The replacement parts which have these
8. Before returning the set to the customer, special safety characteristics are identified by
always perform an AC leakage current check marks on the schematic diagram and on the parts
on the exposed metallic parts of the cabinet, list.
such as antennas, terminals, screwheads,metal Before replacing any of these components,
overlay, control shafts, etc., to be sure the set read the parts list in this manual carefully. The
is safe to operate without danger of electrical use of substitute replacement parts which do not
shock. Plug the AC line cord directly to the have the same safety characteristics as specified
AC outlet (do not use a line isolation in the parts list may create shock, fire, or other
transformer during this check). Use an AC hazards.
voltmeter having 5K ohms volt sensitivity or 9. Must be sure that the ground wire of the AC
more in the following manner. inlet is connected with the ground of the
Connect a 1.5K ohm 10 watt resistor paralleled apparatus properly.
by a 0.15µF AC type capacitor, between a
good earth ground (water pipe, conductor etc.,)
and the exposed metallic parts, one at a time.
Measure the AC voltage across the combination
of the 1.5K ohm resistor and 0.15 uF
capacitor. Reverse the AC plug at the AC
outlet and repeat the AC voltage measurements
for each exposed metallic part.
The measured voltage must not exceed 0.3V
RMS.
This corresponds to 0.5mA AC. Any value
exceeding this limit constitutes a potential
shock hazard and must be corrected
immediately.
The resistance measurement should be done
between accessible exposed metal parts and
power cord plug prongs with the power switch
"ON". The resistance should be more than
6M ohms.
AC VOLTMETER

Good earth ground Place this probe

such as the water on each exposed
pipe, conductor, metallic part
etc.
AC Leakage Current Check
 MODEL : PDP4210EA
Technical Specifications
42” Plasma Display

DATE FIRST ISSUED ISSUE RAISED BY CHECKED BY NUMBER OF PAGES

1 10
REVISIONS
ISSUED DATE DESCRIPTION RAISED BY :

SPECIFICATION AGREED : SIGNATURE DATE

R & D DEPARTMENT
...................................................................................... ...........................
...... ...

COMMERCIAL DEPARTMENT

...................................................................................... ...........................
...... ...
PRODUCTION DEPARTMENT

...................................................................................... ...........................
Q/A DEPARTMENT ....... ...

...................................................................................... ...........................
CUSTOMER ....... ...

...................................................................................... ...........................
....... ...

SPECIFICATION APPROVED : SIGNATURE : DATE :

NOTE : Only documents stamped “Controlled Document” to be used for manufacture of production parts.
 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 2 OF 10 PAGES

1. Standard Test Conditions

All tests shall be performed under the following conditions, unless otherwise specified.

1.1 Ambient light : 150ux (When measuring IB, the ambient luminance
≦0.1Cd/m2)

1.2 Viewing distance : 50cm in front of PDP

1.3 Warm up time : 30 minutes

1.4 PDP Panel facing : no restricted

1.5 Measuring Equipment : PC, Chroma 2225 signal generator (with Chroma digital
additional card) or equivalent, Minolta CA100 photometer

1.6 Magnetic field : no restricted

1.7 Control settings : Brightness, Contrast, Tint, Color set at Center(50)

1.8 Power input : 110~120Vac,60Hz

1.9 Ambient temperature : 20°C ± 5°C (68°F ± 9°F)

1.10 Display mode : 31.5KHz/60Hz (Resolution 852 x 480)

1.11 Other conditions :

1.11.1 With image sticking protection of PDP module, the luminance will descend
by time on a same still screen and rapidly go down in 5 minutes. When
measuring the color tracking and luminance of a same still screen, be sure
to accomplish the measurement in one minute to ensure its accuracy.

1.11.2 Due to the structure of PDP, the extra-high-bright same screen should not
hold over 5 minutes for fear of branding on the panel.
 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 3 OF 10 PAGES

ELECTRICAL CHARACTERISTICS

2. Power Input

2.1 Voltage : 110 ~120VAC

2.2 Input Current : 3.5A

2.3 Maximum Inrush Current : <30 A (FOR AC110V ONLY)

Test condition : Measured when switched off for at least 20 mins

2.4 Frequency : 60Hz(±3Hz)

2.5 Power Consumption : ≤ 330W

Test condition : full white display with maximum brightness and
contrast

2.6 Power Factor : Meets IEC1000-3-2

2.7 Withstanding voltage : 1.5kVac or 2.2kVdc for 1 sec

3. Display

3.1 Screen Size : 42” Plasma display

3.2 Aspect Ratio : 16:9
3.3 Pixel Resolution : 852x480
3.4 Peak Brightness : 1000 cd/m² (Panel module without filter)
3.5 Contrast Ratio (Dark room) : 3000:1 (Panel module without filter)
3.6 Viewing Angle : Over 160°
3.7 OSD language : English,Spaish,French

4. Signal

4.1 AV & Graphic input

4.1.1 TV standard : NTSC/ATSC

4.1.2 TV Tuning system : 181CH (for NTSC), 2~69CH (for ATSC)
4.1.3 CATV : 125CH (for NTSC)
4.1.4 Composite signal : AV
4.1.5 Y,C Signal : S-Video
4.1.6 Component signal : Y, Pb/Cb, Pr/Cr, HDTV compatible
4.1.7 Graphic I/P : Analog: D-sub 15pin detachable cable
Digital: DVI
4.1.8 PnP compatibility : DDC 1.0
4.1.9 I/P frequency : fH: 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz (640x480
recommended)
 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 4 OF 10 PAGES

4.2 Audio input

Audio I/P(L/Rx5) : 1 for DVI
1 for D-Sub
2 for YPbPr
1 for S-Video /AV

4.3 Audio output

Audio O/P(L/Rx1) : Monitor out(L/R)

SPDIF : Optical x 1

5. Environment
5.1 Operating environment
5.1.1 Temperature : 5º to 33°C
5.1.2 Relative humidity: 20% to 85%(non-condensing)

5.2 Storage and Transport

5.2.1 Temperature : -20°C to 60°C(-4º to 140°F)
5.2.2 Relative humidity: 5% to 95%

6. Panel Characteristics

6.1 Type : LG V6
6.2 Size : 42”, 1005mm(width)x597mm(height)x61mm(depth)±1
mm)
6.3 Aspect ratio : 16:9
6.4 Viewing angle : Over 160°
6.5 Resolution : 852x480
6.6 Weight : 14.8kg ±0.5 kg (Net)
6.7 Color : 16.77 million colors by combination of 8 bits R,G,B digital
6.8 Contrast : Average 60:1 (In a bright room with 150Lux at center)
Typical 3000:1 (In a dark room 1/25 White Window
pattern at center).
6.9 Peak brightness : Typical 1000cd/㎡ (1/25 White Window)

6.10 Color Coordinate Uniformity : Contrast; Brightness and Color control

at normal setting
Test Pattern : Full white pattern

Average of point A,B,C,D and E +/- 0.01

 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 5 OF 10 PAGES

6.11 Color temperature : Contrast at center (50); Brightness center (50);

Color temperature set at Natural
x=0.285±0.02
y=0.293±0.02

6.12 Cell Defect Specifications

Subject to Panel supplier specification as appends.

7. Front Panel Control Button

7.1 CH Up / Down Button : Push the key to changing the channel up or down.
When selecting the item on OSD menu.
Volume Up/ Down Button : Push the key to increase the volume up or down.
When selecting the adjusting item on OSD menu
increase or decrease the data-bar.
Menu Button : Enter to the OSD menu.

Input Select Button : Push the key to select the input signals source.

7.2 Stand by Button : Switch on main power, or switch off to enter power
Saving modes.

7.3 Main Power Switch : Turn on or off the unit.

8. OSD Function

Full on screen display

 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 6 OF 10 PAGES

9. Agency Approvals

Safety UL60950

Emissions FCC class B

10. Reliability

11.1 MTBF : 20,000 hours(Use moving picture signal at 25°C ambient)

11. Accessories : User manual x1, Remote control x1, Stand x1, Power cord x1,
Battery x 2.
 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 7 OF 10 PAGES

13. Support the Signal Mode

A. VGA and DVI mode

Horizontal Vertical Dot Clock

NO. Resolution Frequency Frequency Frequency
(KHz) (Hz) (MHz)
1 640 x 400 31.47 70.08 25.17
2 640 x 480 31.50 60.00 25.18
3 640 x 480 37.50 75.00 31.50
4 640 x 480 37.86 72.81 31.50
5 720 x 400 31.47 70.08 28.32
6 800 x 600 35.16 56.25 36.00
7 800 x 600 37.90 60.32 40.00
8 800 x 600 46.90 75.00 49.50
9 800 x 600 48.08 72.19 50.00
10 832 x 624 49.00 75.00 57.27
11 1024 x 768 48.40 60.00 65.00
12 1024 x 768 56.50 70.00 75.00
13 1024 x 768 60.00 75.00 78.75
14 1152 x 864 63.86 70.02 94.51
15 1152 x 864 67.52 75.02 108.03
16 1280 x 720 45.00 60.00 74.25
17 1280 x 960 60.02 60.02 108.04
18 1280 x 1024 64.00 60.01 108.00

B. HDTV Mode (YPbPr)

Horizontal Vertical Dot Clock

NO. Resolution Frequency Frequency Frequency
(KHz) (Hz) (MHz)
1 480i 15.734 59.94 13.50
2 480p(720x480) 31.468 59.94 27.00
3 576p(720x576) 31.25 50.00 27.00
4 720p(1280x720) 37.50 50.00 74.25
5 720p(1280x720) 45.00 60.00 74.25
6 1080i(1920x1080) 33.75 60.00 74.25

- When the signal received by the Display exceeds the allowed range, a warning message
“Main Not Support!” shall appear on the screen.
- You can confirm the input signal format from the on-screen.
- DVI could not support some PC Graphic cards.
 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 8 OF 10 PAGES

Remote Control

Standby ( ): Press to turn on and off.

Mute ( ): Press to mute the sound.
Press again to restore the sound.
0~9 Number Buttons: Press 0~9 to
select a channel, and used to input the
password; the channel changes after
2 seconds.
EPG: Press to display EPG mode.
Press it again to exit EPG mode.
Input: Press to select the signal
source, such as TV, AV, S-Video,
Component 1, Component 2, VGA,
DVI or DTV.
DTV: Press to choose DTV directly.
Dot: Press number buttons with it to
select the channels directly in DTV.
VOL +/-: Press to adjust the volume.
CH +/- : Press to select the channel
forward or backward.
MTS: Press repeatedly to cycle through
the Multi-channel TV sound (MTS)
options: Mono, Stereo and SAP
(Second Audio Program).
◄,►,▲,▼, Enter: Press ◄,►,▲,
▼ to move the on-screen cursor. To
select an item, press Enter to confirm.
And it can also press ▲ or ▼ to
select channels, press ◄ or ► to
adjust the volume.
Exit: Press this button to exit.
Menu: Press to enter into the on-screen
setup menu, press again to exit.
V-Chip: Press to select the child
protect mode.
CCD: Press to select the Closed Caption mode.
Freeze: Press to freeze the picture, press again to restore the picture.
Display: Press to display the channel information and it disappear after 3 seconds.
Favorite: Press repeatedly to cycle through the favorite channel list.
Add/Erase: Press to add or delete favorite or dislike channels.
S.Mode: Press repeatedly to cycle through the sound mode: Normal, News, Cinema,
Flat and User.
PIC Size: Press repeatedly to cycle through the picture size that best corresponds your
viewing requirements: Normal, Full, Wide1, Wide2, Wide3, 4:3, No Scale and Panoramic.
(Continued on next page)
 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 9 OF 10 PAGES

P.Mode: Press repeatedly to cycle

through the picture mode: Normal,
Vivid, Hi-Bright, User and Dark.
System: Press repeatedly to cycle
through the system options: AUTO,
and NTSC3.58.
Recall: Press to return to previous
channel.
Sleep: Press repeatedly until it
displays the time in minutes (5 Min,
10 Min, 15 Min, 30 Min, 60 Min, 90
Min, 120 Min and, OFF) that you
want the TV to remain on before
shutting off. To cancel sleep time,
press SLEEP repeatedly until sleep
OFF appears.
Red: Press this button to access the
red item or page.
Blue: Press this button to access the
blue item or page.
Green: Press this button to access
the green item or page.
Yellow: Press this button to access
the yellow item or page.

Note: Press CH +/- on the remote control can turn on TV set from standby mode.

Insertion of Batteries:
- Turn the remote control upside down, press and slide off the battery cover.
- Insert two 1.5V (AAA) batteries into the compartment, take care to observe the  and 
markings indicated inside.
- Replace the cover and slide in reverse until the lock snaps.
 CONTINUATION PAGE
Technical Specifications PDP4210EA
NUMBER 10 OF 10 PAGES

PHYSICAL CHARACTERISTICS

14. Power Cord

Length : 1.8m nominal

Type : optional

15. Cabinet

15.1 Color : “Black” colour as defined by colour plaque reference number

15.2 Weight

Net weight : 36.2 kg(with stand) /34.0kg(without stand)

Gross weight : 41.0 kg

15.3 Dimensions(with stand)

Width : 1040 mm
Height : 690 mm
Depth : 290 mm
Block Diagram Product Specification of PDP Module

Vs(180V~190V)
LVDS Input Memory
Controller
Input Va(55V~65V)
Interface
Controller Vcc(+5V)
Control Signal
(Serial Interface) Driver
Timing
APL Data Controller

Display data, Driver timing

Common sustain driver

Scan Driver

Color Plasma Display Panel

852 X 480 pixels

Address Driver

☞ Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.
Block Diagram

X6965D
SAW Filter
(U9)

TD1336 UPC3218 2nd_IF+ & 2nd_IF-

MT5111
Coaxial AGC Amplifier Differential Data Stream DTV Front-end
Tuner(U8) (U10) 74HC74
(U11) (U12)

TS[0...7] I2C
EEPROM
24C16(U13)

I2C
256Mb DDR
(U15)

MT5351
DTV Back-end
(U14) 32Mb
Flash(U17)

256Mb DDR
Video Data[0...23]

(U18)
Audio Data

Signals
Control

SPD

Connect with
MT8205
Block Diagram

Power Connector To PDP

(Supplied by PDP)

1.25V

To PDP
3.3V
2.5V

1.8V
5V

PDP Control Signals

PDP Connector

RGB Output
From MT 5351

Control Signals
Audio LVDS Data

3.3V
2.5V
1.8V
Vedio[0...23]
74LVC244A
U30-U33

3.3V SiI161B
DVI (SiI169) Video[0...23]
DVI Reciver
(U18) I2C (MT8205 I2C) Flash 3.3V
5V EEPROM 16M-BIT(U9)
DVII2C 24C02(U19)

DDR
MT8205
CVBS×2 (CVBS0 is from tuner.) 2.5V

TV 128Mb(U10) 1.25V
BA7612F
(U23)

V_BYPASS AV (U7)
Data[0...31] LP2996
IDTQS3
VH257

Address[0...11]
(U16)

YPbPr (U12)
YpbPr×2

S-Video
DDR 1.25V
VGA 128Mb(U11) 2.5V
Bypass Out

RS232 5V EEPOROM
Signals VGAI2C 24C02(U14)
IDTQS3VH257

MX232A TTL Signals

EEPROM
Dout

(U1) (Used by MT8205) I2C

Din

3.3V 24C16(U2)
From MT3551

(U25)

CS4334
MT8205 I2C

UART0 (Communication with MT5351)

(U22)
UART2 (MT5351 DownLoad) 5V

5V
Audio Bypass

DVI Audio in

YPbPr Audio in MT8776 I2C

(U20)
AV1 Audio
CD4052

AV Audio in
(U17)

AV2 Audio
5V
& Audio R
Audio L
Circuit Diagram

- Power supply board of PDP Module, DGP-420WXGA

- Power supply board of PDP Module, USP490M-42LP
- Main (Video) board
- Audio/Tuner board
- ATSC board
- Keypad board
- Remote control receiver board
- External L/R Speakers board
- Remote control board
 5 4 3 2 1

F101 CN01 VI
250VAC 8A 3-176976-2 T204,205 D600
VS EER4042 FSF10A60
1 1 L104 R108 R103
L101 L103
CH108200S CH108200S 5W 15 5W 20 T208 D102 PFC + 190VS

1
23mH PFC+
2 2 PFC COIL 200uH FEP30JP
CN02 CN03 R609
3-176976-1 3-176976-1 R226 300KF
R221 2W 240K R600 C600
R102 2.2M C222
RELAY1

275VAC 1uF
1W 390KJ Q102,Q103,Q109 D205 630V 0.1uF
SDT-SH-118DM SPW20N60C3*3 C105,106 BYV26EGP 1W4R7 1KV 220pF

C101
C104 450V 330uF R610
TNR101 RYC 630V 1uF R222 300KF
14D 621K D103 D204 2.2M Q203,204
LL4148 C206 SPW11N80C3*2
630V 0.047uF D601
LL4148 R104 VA VCC FSF10A60 C602
10W 0.02 R223 250V 820uF R611
TNR102 2.2M 300KF
L102 14D 621K
23mH BD101 R603 C601
D25XB60 R112 3KF
C102,103 R224 C221 VS DET
250V 0.001uF 2.2M R227 R228 1W4R7 1KV 220pF 630V 0.1uF
PFC VCC 1W 4.7 1W 4.7 R612
D 12KF D

R115
1.5KF
C110 R109 R106 R107 R225
470pF C108 1W 4.7 1W 4.7 1W 4.7 R144 1M
680pF R113 10F D213

3K
24KF LL4148 Q206 GND
C111 KTA1281 R230
R116 4.7KF
0.1uF 10KF D109 C123
PFC+ 1N5236B 35V 47uF

R114
R117 R118 R119 R120 R121 C112 Q104 190VS
180KF 180KF 180KF 160KF 160KF 330pF C109 KTC3209 Q106
R123 C113 R124 68PF KSP2907 R232 R231 R604 R613
R122 330KF 2.2uF 220KF R176 1K 5W 0.05 120KF 120KF
18KF 10KF

11

3
R620 R602
7 Q105 R110 2W 100K 2W 100K R606 R627
VO

MO
VS

RE

PK

IS

CA
R129 R111 KTA1281 10KF PC102 C220 35V 47uF 270KF 120KF
150KF 6 16 100F PC-17K1C
VI IA U101 UC3854N GT

GND

6
R125 R126 R127 R128 8 10 R628

RS

VC
SS

CT
VR EN R137 120KF
75KF 75KF 75KF 75KF

VCC
R130 RYC R233 C209 1uF
10KF 8 CS

13

14

12

15
240KF R131 100KF 5

1
OUT

50V 10uF

0.0022uF
C114 33KF C210 0.001uF 7
R133 0.68uF D111 CT R243 R607

10KF
33KF 1N4148 R235 4.7KF 1 1W 47R 130KF
R136 RT PC204
IS + 3
10KF C211 0.001uF 2 FB

GND
C117
R134 35V 470uF R608

C116
C115

R135
24KF Q207 R236 10KF 120KF
KRC103M IC201 Q702

4
KA7552A KTC3207
VR601
R260
R132 C212 5K
2.4KF
33KF T100 PC204 0.0047uF
STBY EE1927 L301 PC-17K1C
PFC+ 27uH +5VSTBY C225 D211
D300 C263 0.1uF 1N5234B R615

630V 0.01uF
R143 R145 SB560 R301 R302 10uF 18KF

C121
220F
3W 470K 2W 240K 1.02KF
C301,301A
AC-1 10V 2200uF*2 PC101 T206 D700
D104 VA EER4042 FSF10A60
D107 US1M R146 C302
US1M Q107 2W 100 0.68uF PFC + 60VA
R140 KTC3198Y R704
R199 R196 R193 R189 7.5KF 22KF
R303
2

56KF 56KF 56KF 200KF IC300 R253

D105 KA431AZ 1KF 2W 240K R700 C700
DRAIN

VCC

R198 R195 R192 R190 PC100 US1M D208

56KF 56KF 56KF 200KF GND BYV26EGP
C R705 C
U100 D226 1W 10 1KV 100pF 20KF
R142 5M0280R-YDTU LL4148
GND

6.8KF C213
FB

R141 VA VS AC DET PFC ON/OFF VA VCC 630V 0.01uF C701,702,704

4.7KF C118 R155 R152 R154 R153 Q209 100V 330uF
0.01uF C120 100KF 100KF 100KF 100KF D302 SPW11N80C3
1

R706
D108 1N5236B

C126 R175 35V 47uF D301 US1M 20KF

0.1uF

250V 0.47uF 0 US1M

R151 R150 R149 R148
PC-17K1C

100KF 100KF 100KF 100KF R306 R229

R305 5W6.8 D209 1W 4.7F VA DET
5W15 LL4148
C119

PC101

R307 PC100 PC102

5W6.8 PC-17K1C R707
2.7KF
Q208 R245
R156 Q300 KTA1281 10KF GND
1KF FQP17N40
PFC VCC
D106 Q108
C128 US1M 방전 CTL KTC3198Y D303 C304 60VA
35V 470uF 1N5245B 50V 4.7uF R247 R246
1.2K 5W 0.2
R715 R716 R720 R710 R701 R708 R702
PFC GND 45.3KF 45.3KF 45.3KF 18KF 18KF 18KF 33KF

T207 C215 35V 47uF

MULTI EER4042 R500 C500
1W 10 1KV0.001uF MULTI ON/OFF R718 R717 R721 R712 R714 R719 R703
PFC +

6
L500 45.3KF 45.3KF 45.3KF 18KF 18KF 18KF 36KF
C550~C554 6*20 2.5uH C504,C555~C557

VCC
10V 2200uF*5 10V 2200uF*4 R248 C216 1uF 8
R209 +5VCTRL 100KF CS
OUT 5 VA ON/OFF
2W 240K D500 C217 0.001uF 7 R709
SF30SC6 R520 VR500 CT R252 PC206 36KF
470F 2K R502 R250 4.7KF 1 1W 100R
D202 0 5VSC RT
IS + 3
D200 BYV26EGP Q210 C218 0.047uF 2 FB

GND
D5001 PC202 R503 KRC103M Q701
MULTI VCC SF30SC6 PC201 KTC3207 VR700
LL4148 C200 1KF R251 10KF 5K
630V 0.01uF IC202

4
+5V DET
R501 KA7552A
Q201
C530 3.3KF R261
SPW11N80C3
1uF 1KF PC205
R249 PC206 C219
R504 10KF
D206 IC500A R522 C214 PC-17K1C 0.01uF R711
1.8KF
LL4148 R210 KA431AZ 4.7KF PC205 0.01uF D212 11KF
D203 1W 10F PC-17K1C C226 1N5234B
LL4148 C261 0.001uF
GND 4.7uF
B IC500 B
R505 C505 KA317
R212 1W 4R7 1KV 0.001uF
Q200 10KF 1 2
KTA1281 Adj Output +30V/1.0A (+24V/1.25A)
Input

D501 R525
56KF R511
15KF R400 LED401
+30V DET
R214 R237 SUF30J 1KF RED
3

360RF 5W 0.1
R509 R512 REVISION HISTORY
3.3KF 15KF 5VCTRL R401 1KF
C506
50V 220uF
R507
5W 2.7K
C507
35V 47uF
R510
5W 1K R402 4.7KF
NO 일자/사유 변경 변경
C202 35V 47uF SEL 전 후
R508 CABLE IC400
0R R513 KIA7045AP 2004/07/28 PH967C6 FEP30JP
1
6

2.7KF
1 3
VCC

VCC OUT

GND
C203 1uF GND
8 CS
5 IC501
R216 C204 0.001uF OUT KIA278R12PI LED400 CRST400
7 CT

50V0.01uF

50V0.01uF
100KF R220 C519 R531 GREEN 4MHZ

2
R218 4.7KF 1 1 2 C400 C401
ON/OFF

RT 1/4W 100R Vin Vo +12V /1.0A

3 50V 0.1uF 50V 0.1uF 1 3
IS + Xin Xout
GND

GND
C205 0.22uF 2 D502

10KF

10KF
FB
GND

R514
2KF
Q202 R219 31GF6
3

2
KRC103M 10K IC200 +12V DET
4

KA7552A R532 R515

C510 1W 2.7K C511 1.8KF R516

C411
24

23

22

21

20

19

18

17

16

15

14

13

C410
R421

R422
35V 470uF 35V 47uF 1KF

Vss

Xout
RA3/AN3

RA2/AN2

RA1/AN1

RA0/EC0

RC1

RC0

|RESET

Xin

RD3

RD2
GND

R416 1KF
PC-17K1C

R262 IC502

DGP-420WXGA
1KF KIA378R09PI
R217 C208 C520 R526 IC401

100F
PWM0/COMP0/RB4
10KF 470pF 1 2 HMS87C1304A
ON/OFF

Vin Vo 9VSC

AN0/AVref/RB0
GND

PC202 D503 R518

C201 PC-17K1C 3.9KF

R415
INT0/RB2

INT1/RB3
BUZ/RB1
AN4/RA4

AN5/RA5

AN6/RA6

AN6/RA6
0.01uF
PC201

C262 C227 D10L20U

3

+9V DET

VDD

RD0

RD1
4.7uF 0.001uF C516 C514
35V 1000uF 35V 47uF J2
0 R519
1.5KF

10

11

12
1

9
GND C403 50V 0.68uF SW400
JSS 2209

R420 4.7KF
CN803 C404 50V 0.1uF

330F

R412 1KF

R414 2KF

R417 1KF

R418 1KF
R408 1KF
A 5VSC 1 A
C405 50V 0.1uF
2

1KF
CN806 C406 50V 0.1uF

R411
CN804
3 60VA 10

1KF
C407 50V 0.1uF
CN807 CN808

R407
4 9VSC 1 9 C408 50V 0.1uF

R409 2KF
1KF

CN801
R406
5 2 8 190VS 1 5VCTRL 1
1KF

C409 50V 0.1uF

330F
R403 1KF

R423 1KF
ACD 1 6 3 7 2 2
R405

RLY_ON
R404

2 12VSC 7 4 6 3 3

R410
CN802 CN805
SB5V 3 8 5VSC 5 5 4 4

4 24V/30V 1 9 6 5VCTRL 4 4 5 5 9 4
7 11 6 21 20 16 18 17 19 3 13 12 2 15 5 8 1
VA,VS ON/OFF

MULTI ON/OFF
CN809
VS_ON 5 2 10 7 3 3 60VA 6 6
PFC ON/OFF

5VD OUT
GND

RY ON/OFF
VS ON
방전CTL

RLY ON
AC DET
+30V DET
+5V DET

+9V DET

ACD OUT
VA DET

+12V DET
+5VSTBY

VS DET
GND

5VD 6 3 11 8 2 190VS 2 7 7 9VSC 1

< D
7 4 12 9 1 1 5VCTRL 8 8 2
HIC_MICOM m <D
171825-7 171825-4 1-171825-2 171825-9 1-1123723-4 1-1123723-0 1-1123723-8 171825-8 171825-2
1
5 4 3 2 1
USP490M-42LP
 A B C D E

MT8205E (PBGA388) LCDTV BOARD 4 LAYERS

DV18A

4
1. INDEX RSRXD
RSTXD
RSRXD
RSTXD
6
6 4

2. LDO Power down Reset circuit PCRXD

PCRXD 13
PCTXD
PCTXD 13
R73 10/NC TXD
TXD 3,13

3. MT8205E PBGA388
CE88 2N3904 RXD
RXD 3,13
DV33A R341 10 3 2 R342 URST# S CL

+
SCL 7,10
0 SDA
SDA 7,10

4. MT8205 ANALOG DECOUPLING

47uF/16v Q14 URST#
URST# 3
CB136

1
D28 0.1uF +12V
+12V 7,10,13,14

5. DDR MEMORY & FLASH

1N4148 TUNER_12V
TUNER_12V 7
8205UP3_1
8205UP3_1 3
PWR_ GND
PWR_GND 11

6. VGA IN & PC AUDIO IN

INVERTER_PWR
INVERTER_PWR 11
GPIO_DVD1
GPIO_DVD1 3
DV18A
DV18A 2,3

7. VIDEO IN & TUNER IO ADD BY MTK

8. AUDIO/VIDEO IN CIRCUIT
9. DVI INPUT
10.LVDS/CRT/TTL OUT
11.BACK LIGHT / KEYPAD
RSRXD

PCRXD

12.WM8776 & A/V BYPASS 5VSB

RSTXD PCTXD

13.ATSC INTERFACE
U1 INVERTER_PWR
13 12 5VSB DV33A J3
R1IN R1OUT
8 R2IN R2OUT 9

14.PDP INTERFACE
11 14 INVERTER_PWR 1
CE1 T1IN T1OUT R335 R336
3 + 10 T2IN T2OUT 7 2 3
220uF/16v 0/NC 0 3
C220UF16V/D6H11 C1 0.1uF 1 4
5VSB C+ ADD BY MTK
3 C1- 5
C2 0.1uF 4 16 6
C2+ VCC
5 C2- 7
C3 0.1uF 2 C4 PWR_ GND 8
V+ 0.1uF
6 V- GND 15
C5 0.1uF 8x1 W/HOUSING
MAX232A DIP8/W/H/P2.54

HOLE/GND
H1
9 9 2 2
8 8 3 3
7 7 4 4
6 5 5VSB
6 5 5VSB 5VSB
1

DV33A
1

SYSTEM EEPROM R1 8205UP3_1 HIGH :POWER OFF

10k R112
R337 R3 R4
J1
R 8205UP3_1 LOW :POWER ON
10k 10K 10K R0603/SMD R5 R6
CB1 U2 SYS _PWR 10k 10k J4
5
1 NC VCC 8 4 5VSB Q1
HOLE/GND 0.1uF 2 7 GPIO_DVD1 3 1
H2 NC WP R2

2
3 6 S CL 2 R xD 2
NC SCL SDA 8205UP3_1 TxD
9 9 2 2 4 GND SDA 5 1 1 3
8 8 3 3 Add by MTK 4
7 4 SOT23/SMD 4.7k
7 4 EEPROM 24C16 5x1 W/HOUSING

3
RS-232
6 5 2N3904
6 5 SOP8/SMD PH5/2.0 4x1 W/HOUSING
C132 C133 DIP4/W/H/P2.0
1

2 2
20pF 20pF
1

Add by MTK

VCC
J2
1 +12V For Tuner
HOLE/GND 2
H3 L1
L44 L50 3
9 2 4 TUNER_12V
9 2
8 8 3 3 5
7 4 6 +12V FB
7 4 FB FB CE2 BEAD/SMD/0805
6 6 5 5 7 +
BEAD/SMD/1206 BEAD/SMD/1206 8 220uF/16v + CE3
C220UF16V/D6H11 47uF/16v CB2
1

9
10 0.1uF
1

11
PWR_ GND

DIP11/P2.54
AUIO IN/OUT GND ANALOG INPUT GND DIGITAL GND

HOLE/GND
H4
9 9 2 2
8 8 3 3
7 7 4 4 From Power board.
6 6 5 5 J21
VCC
1

1
2
1

3
4
1 5 1
6
+12V 7
8
9
1 M1 1 M2 1 M3 10

CON10
1 V1 1 V2 1 V3 1 V4

Title

Size Doc Number Rev

C INDEX V1.2
Date: Wednesday, October 12, 2005 Sheet 1 of 15
A B C D E
 A B C D E

4 4

R96
0/NC
Power ON alive source
R0805/SMD

VCC U3 CM1117-3.3V DV33 5VSB U4 CM1117-3.3V

TP1
TEST POINT DIP1.0
L2 L3
Vout
ADJ/GND

ADJ/GND
3 2 DV33 3 2
IN OUT IN OUT
FB CE4 FB
BEAD/SMD/0805 + BEAD/SMD/0805
+ CE5 + CE6 CB3 + CE7
1

1
220uF/16v CB4 220uF/16v CB5 220uF/16v 0.1uF 220uF/16v CB6
3 0.1uF SOT223/SMD 0.1uF SOT223/SMD 0.1uF 3

R99
0/NC

R0805/SMD
AV33 DV33A
U5 CM1117-3.3V
L4
ADJ/GND

3 2 AV33 DV33A
IN OUT
FB
BEAD/SMD/0805 + CE8
220uF/16v C6 CB7
U6 CM1117-1.8V
L5
TP2
DV18A
1

10uF/10v 0.1uF

ADJ/GND
SOT223/SMD 3 2 DV18A
IN OUT
FB
BEAD/SMD/0805
+ CE9 + CE10

1
100uF/16v CB8 220uF/16v CB9 DV18A
0.1uF 0.1uF DV18A 1,3
SOT223/SMD

2 2

1 1

Title

Size Doc Number Rev

C LDO V1.2
Date: Wednesday, October 12, 2005 Sheet 2 of 15
A B C D E
 A B C D E

R106
DV33A 0

5VSB 0 U27
R104 LM809
SOT23/SMD DV IODCK
DVIODCK 9,13
RSTVCC 3 2 URST# DV IDE
IN OUT DVIDE 9,13
DV IHSYNC

ANALOGVDD

ANALOGVDD
DVIHSYNC 9,13

GND
GND

GND
ADCPLLVDD1
DVIVSY NC

H SYNC_VGA

ANALOGVDD
VGAVSYNC#

ADCPLLVDD

APLL_CAP
AD CVDD0

AD CVDD0

AD CVDD0

AD CVDD0

AD CVDD0
DVIVSYNC 9,13

DV IODCK
GND

APLLVDD

DV18A
VGASOG

DV18A
CB135 CE81

GREEN+
GREEN-
+

CVBS2+

CVBS1+

CVBS0+
CVBS2-

CVBS1-

CVBS0-
A_DQS[0..3]

BLUE+
R270 A_DQS[0..3] 5

XTALO
VOCM

BLUE-
AVCM

RED+

XTALI
R ED-
VICM
GND

GND

GND

GND

GND

GND

GND

1
SOY

GND
A_RA[0..11]

CR+

VI10
VI11

VI12
VI13
VI14
VI15

VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
0.1uF 22uF/25v 100K A_RA[0..11] 5

SY+
SC+

CB+
C R-
S Y-
SC-

CB-

VI0
VI1
VI2
VI3
VI4
VI5
VI6

VI7
VI8
VI9
Y+

GND

GND
GND

GND
Y-
A_BA[0..1] A_BA[0..1] 5
A_DQM[0..1] A_DQM[0..1] 5
A_DQ[0..31] A_DQ[0..31] 5

M13

M14

M15

M16
N13

D10

D11
C11

D13

C10
D12
C12
C13
C14
N14
D14

D15
C15

D16

C16

D18
D17
C17
C18

C19
D19

C20
D20

C21
D21

C22
D22

C23
D23
B10
A10

B11
A11
B12
A12

B13
A13

B14
A14

B15
A15

A16

B16
A17
B17
A18
B18

E23
A19
B19

A20

B20

A21

B21

A22
B22

A23
B23
L12

L13

L14

L15

L16
A_CLK A_CLK 5

D5
C4

C5

D6
C6
D7

C7

C8

D9
C9

D8
B1
A1
B2
A2
B3
A3

B4
A4

B5
A5
B6
A6

B7

A7

B8
A8
B9
A9
XTALI A_CLK# A_CLK# 5
XTALI 4
XTALO U7 A_CKE A_CKE 5
XTALO 4

CVBS2P

CVBS1P

CVBS0P

SCP

SYP

CRP

CBP

YP
SOY

RP

GP

BP

DVSS

ADCPLLVSS
SYSPLLVSS

TESTP

XTALI
XTALVSS
APLL_CAP
APLLVSS

DMPLLVSS

VCLK_DVI
AVCM

VOCM

VICM
VFEVSS1

ADCVDD0

ADCVSS0
REFP0
REFN0
ADCVDD1

ADCVSS1
REFP1
REFN1
VFEVDD0

VFEVSS0

ADCVSS2
REFP2
REFN2
MON0
MON1
ADCVDD3

SOG

ADCVSS3
REFP3
REFN3

ADCPLLVSS1

XTALO

VI0
VI1
VI2
VI3
VI4
VI5
VI6
DVDD18
VI7
VI8
VI9
VI10
VI11
DVSS3
VI12
VI13
VI14
VI15
DVSS18
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
CVBS2N

CVBS1N

CVBS0N

SCN

ADCVDD2
SYN

CRN

CBN

YN

RN

GN

BN

VSYNC
HSYNC

DVDD

ADCPLLVDD1
ADCPLLVDD

SYSPLLVDD

TESTN
XTALVDD

APLLVDD
DMPLLVDD
4 4
ANALOGVDD
ADCV DD
ANALOGVDD 4 External Reset Circuit A_CS#
A_RAS#
A_CS#
A_RAS#
5
5
ADCVDD 4
APLLVDD A_CAS# A_CAS# 5
APLLVDD 4
VPLLVDD ADC VDD4 C3 C24 DV IDE A_WE# A_WE# 5
VPLLVDD 4 VFEVDD1 DE_DVI
ADCPLLVDD1 ADC VDD4 D3 D24 DVIVSY NC SDV25 SDV25 5
ADCPLLVDD1 4 ADCVDD4 VSYNC_DVI
ADCPLLVDD MPX1 C1 A24 DV IHSYNC V REF VREF 5
ADCPLLVDD 4 SIF HSYNC_DVI
AUXTOP MPX2 C2 Y24 DV18A ORO7
AUXTOP 4 AF DVDD18 ORO7 12
AUXBOTTOM GND L11 A25 ORO4
AUXBOTTOM 4 ADCVSS4 AOSDATA0 ORO4 12
REXTA VREFP4 D1 A26 AOSDATA1 ORO2
REXTA 4 REFP4 AOSDATA1 VI[0..23] ORO2 7
APLL_CAP V REFN4 D2 B26 DV33A VI[0..23] 9,13
APLL_CAP 4 REFN4 AOSDATA2 F_A[0..20]
PWM2VREF GND F2 F23 DV33A F_A[0..20] 5
PWM2VREF 4 ADCVSS DVDD3I F_ D[0..7]
ADC VDD0 AD IN4 D4 B25 AOSDATA3 F_D[0..7] 5
ADCVDD0 4 ADIN4 AOSDATA3
ADC VDD4 AD IN3 E1 B24 DOUT DV33A F_OE# F_OE# 5
ADCVDD4 4 ADIN3 LIN
AVCM AD IN2 E2 C26 DACBCLK
AVCM 4 ADIN2 AOBCK
VOCM AD IN1 E3 C25 DACLRC
VOCM 4 ADIN1 AOLRCK
VICM AD IN0 E4 E24 DACMCLK R7 D1 TXD
VICM 4 ADIN0 AOMCLK TXD 1,13
VREFP4 ADCV DD F1 N15 GND 10K/NC RXD
VREFP4 4 ADCVDD DVSS3 RXD 1,13
V REFN4 PWM2VREF F4 G26 A_DQ24 WE#
VREFN4 4 PWM2VREF DQ24 WE# 13
DA CFS AUXTOP F3 G25 A_DQ25 1N4148/SMD PCE#
DACFS 4 AUXVTOP DQ25 PCE# 5
DA CVREF AUXBOTTOM G3 F26 A_DQ26 8205UP3_0
DACVREF 4 AUXVBOTTOM DQ26 8205UP3_0 11
DACV DD GND J3 F24 SDV25 URST# MPX1
DACVDD 4 VPLLVSS DVDD2 MPX1 8
LVDDA VPLLVDD G4 F25 A_DQ27 MPX2
LVDDA 4 VPLLVDD DQ27 MPX2 8
IR VPLLVDD H3 E26 A_DQ28
IR 7,11 DLLVDD DQ28
GND K3 N16 GND VS YNC VSYNC 10
GND DLLVSS DVSS2 A_DQ29 CE11 H SYNC HSYNC 10
K4 BGVSS DQ29 E25 +
REXTA J4 G24 SDV25
VPLLVDD REXTA DVDD2 A_DQ30 10uF/25v/NC
H4 BGVDD DQ30 D26
LVDDA L3 D25 A_DQ31 OGO[0..6] OGO[0..6] 7,9,13
AP7 LVDDA DQ31 A_DQS3
G2 A7P DQS3 H25
G1 H26 A_DQM1 OBO[0..7] OBO[0..7] 11
A7N DQM1 GND AP[0..7] AP[0..7] 10
H2 CLK2P DVSS18 P14
H1 J25 A_DQS2 A N[0..6] AN[0..6] 10
CLK2N DQS2
GND
AP6
M12 LVSSA DQ23 J26 A_DQ23
A_DQ22
Internal Reset Circuit R
G
R 10
J2 A6P DQ22 K25 G 10
A N6 J1 P16 GND B
A6N DVSS2 B 10
AP5 K2 K26 A_DQ21
A N5 A5P DQ21 A_DQ20 RED+ RED+ 8
K1 A5N DQ20 L25
3 LVDDA L4 AA24 DV18A R ED- RED- 8 3
AP4 LVDDB DVDD18 A_DQ19 GREEN+
L2 A4P DQ19 L26 DV33A GREEN+ 8
A N4 L1 H24 SDV25 GREEN- GREEN- 8
AP3 A4N DVDD2 A_DQ18 BLUE+ BLUE+ 8
M2 A3P DQ18 M25
A N3 M1 M26 A_DQ17 BLUE- BLUE- 8
GND A3N DQ17 A_DQ16 R8 CVBS1+ CVBS1+ 8
M11 LVSSB DQ16 N25
CLK1+ N2 J23 A_RA4 47k CVBS1- CVBS1- 8
CLK1- CLK1P RA4 GND CVBS2+ CVBS2+ 8
N1 CLK1N DVSS2 R16
AP2 P2 J24 A_RA5 CVBS2- CVBS2- 8
A N2 A2P RA5 A_RA6 CVBS0+ CVBS0+ 8
P1 A2N RA6 K23
LVDDA M3 K24 A_RA7 DACBCLK CVBS0- CVBS0- 8
AP1 LVDDC RA7 A_RA8 SOY SOY 7

MT8205
R2 A1P RA8 L23
A N1 R1 R14 GND GND SY+ SY+ 8
AP0 A1N DVSS18 A_RA9 S Y- SY- 8
T2 A0P RA9 L24
A N0 T1 M23 A_RA11 SC+ SC+ 8
GND A0N RA11 A_CKE SC- SC- 8
N12 LVSSC CKE N26
DACV DD N3 H23 SDV25 Y+ Y+ 8
DA CVREF DACVDDC DVDD2 A_CLK Y- Y- 8
M4 VREF RCLK P26
DA CFS N4 P25 A_CLK# CB+ CB+ 8
GND FS RCLKB GND CB- CB- 8
N11 DACVSSC DVSS2 P15
T4 M24 A_RA3 CR+ CR+ 8
DACV DD SVM RA3 A_RA2 C R- CR- 8
P3 DACVDDB RA2 N23
GND R3 N24 A_RA1 CLK1+ CLK1+ 10
DACV DD DACVSSB RA1 A_RA0 CLK1- CLK1- 10
P4 DACVDDA RA0 R26
G U4 P24 A_RA10
GND G RA10 A_BA1
R4 DACVSSA BA1 P23
B U3 U23 SDV25 SCL_8205 SCL_8205 10
R B DVDD2I DV18A SDA_8205 SDA_8205 10
V4 R DVDD18 AA23
T3 R24 A_BA0
VS YNC DE BA0 A_CS#
U1 VSYNCO RCS# R23
H SYNC U2 T24 A_RAS#
HSYNCO RAS# GND DACBCLK DACBCLK 12
V1 VCLK DVSS2 R15
V2 T23 A_CAS# DACMCLK DACMCLK 12
EBO7 CAS# A_WE# DACLRC DACLRC 12
V3 EBO6 RWE# U24
W1 W26 A_DQ8 DOUT DOUT 12
EBO5 DQ8 A_DQ9 AOSDATA1 AOSDATA1 12
W2 EBO4 DQ9 V25
DV33A AC9 V26 A_DQ10 AOSDATA3 AOSDATA3 12
DVDD3I DQ10 SDV25 MUTE MUTE 12
2
W3 EBO3 DVDD2 V23 2
W4 U25 A_DQ11
EBO2 DQ11 GND
Y1 EBO1 DVSS18 T13
Y2 U26 A_DQ12 VGASOG VGASOG 8
EBO0 DQ12 A_DQ13 HS YNC_VGA
Y3 EGO7 DQ13 T25 HSYNC_VGA 6
GND P11 T15 GND VGAVSYNC# VGAVSYNC# 6
DVSS18 DVSS2 A_DQ14
Y4 EGO6 DQ14 T26
AA1 R25 A_DQ15 PWM0
EGO5 DQ15 PWM0 11
AA2 W25 A_DQS1 8205UP3_1
EGO4 DQS1 8205UP3_1 1
AA3 W23 GND 8205UP1_2
EGO3 AVSS18 8205UP1_2 9,11
AA4 Y23 DV18A 8205UP1_3
EGO2 AVDD18 8205UP1_3 13
AB1 G23 V REF SW
EGO1 RVREF SW 13
AB2 T16 GND OGO7
EGO0 DVSS18 OGO7 12
AB3 Y26 A_DQM0 PWM1
ERO7 DQM0 PWM1 12
AB4 Y25 A_DQS0 OGO4 OGO4 9,13
ERO6 DQS0 A_DQ7 DVISCL
AC1 ERO5 DQ7 AA26 DVISCL 9
DV18A AC18 V24 SDV25 DVISDA
DVDD18 DVDD2 DVISDA 9
AC2 AA25 A_DQ6
ERO4 DQ6 A_DQ5
AC3 ERO3 DQ5 AB26
AC4 T14 GND
GND ERO2 DVSS2 A_DQ4 GPIO_DVD0
R11 DVSS3 DQ4 AB25 GPIO_DVD0 7
AD1 AC26 A_DQ3 GPIO_DVD1 GPIO_DVD1 1
ERO1 DQ3 SDV25 GPIO_DVD2
AD2 ERO0 DVDD2 W24 GPIO_DVD2 7
OBO7 AD3 AC25 A_DQ2 DVD GPIO PORTS
OBO6 OBO7 DQ2 A_DQ1
AD4 OBO6 DQ1 AD26
OBO5 AE1 AD25 A_DQ0
OBO5 DQ0 PDP power cotrol GPIO.
DVDD18

DVDD18

DVDD18

FCICMD ORO1
DVSS18

DVSS18

DVSS18

DVSS18
HIGHA7

HIGHA6
HIGHA5
HIGHA4
HIGHA3
HIGHA2
HIGHA1
HIGHA0

DVDD3I

FCIDAT
FCICLK
DVDD3

DVDD3

ORO1 10,14
IOWR#
DVSS3

DVSS3
PRST#
IOOE#

GPIO0
IOCS#

PWM0
PWM1
IOALE
OGO7
OGO6
OGO5

OGO4
OGO3
OGO2
OGO1

OGO0

ORO3
ORO7
ORO6
ORO5
ORO4

ORO3
ORO2
ORO1
ORO0

BGA388/SOCKET
IOA18
IOA19
IOA20

IOA21
OBO4
OBO3
OBO2
OBO1
OBO0

INT0#

SDA0

SDA1
UP12
UP13
UP14

UP15
UP16
UP17
UP30
UP31

UP34
UP35

SCL0

SCL1
ORO3 10,14
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7

WR#

RXD

SDA
RD#

TXD
AD0
AD1

AD2
AD3
AD4

AD5
AD6
AD7

SCL
A16

A17

MT8205 ORO5

ICE
ORO5 10

IR
8205UP1_4
8205UP1_4 10
AE2
AF1
AF2
AE3
AF3
AE4
AF4
AC5
T11
AD5
AE5
AF5
AC6
AD9
AD6
AE6
AF6
AC7
AD7
AD18
AE7
AF7
AC8
AD8
AF8
P12
AE9
AF9
AE10
AF10
AC11
AD11
AF12
AE15
AD15
AC19
AC15
AF16
AE16
R12
AD16
AC16
AF17
AD17
AD14
AE14
AF14
AF13
AE13
AD13
AC13
AE8
AC10
AC17
AE12
AD12
AE11
T12
AF11
AE17
AF15
AC12
AC14
AF18
AE18
AD10
AF19
8205UP1_2 AE19
8205UP1_3 AF20
8205UP1_4 AE20
AD19
AD20
AC20
AF21
8205UP3_0 AE21
8205UP3_1AD21
P13
AC21
AD22
AC22
GPIO_DVD2 AF22
GPIO_DVD0 AE22
AF23
AE23
AD23
AC23
AF24
AE24
AD24
R13
AC24
AF25
HWSDA AE25
AF26
AE26
REQUEST#AB23
REA DY# AB24
PDP signal cotrol GPIO.
GPIO
GPIO 7,10
GPIO_DVD1

ORO6
ORO6 10
UP3_4 FOR S/W SCL

DVISDA
HWS CL

DVISCL
URST#

UP3_5 FOR S/W SDA

F_OE#

UP3_4
UP3_5
F_A15

F_A14
F_A13
F_A12
F_A11
F_A10

F_A16

F_A17
F_A18
F_A19
F_A20

F_A21

PWM0
PWM1
ORO7
ORO6
ORO5
ORO4

ORO3
ORO2
ORO1
OGO7
OGO6
OGO5

OGO4
OGO3
OGO2
OGO1

OGO0
OBO4
OBO3
OBO2
OBO1
OBO0

MUTE

PCE#
F_D0
F_D1

F_D2
F_D3
F_D4

F_D5
F_D6
F_D7

GPIO
F_A9
F_A8

F_A0
F_A1
F_A2
F_A3
F_A4
F_A5
F_A6
F_A7

W E#

R xD
DV33A

DV18A

DV18A

DV33A

DV33A

DV18A

REQUEST#
TxD

I CE
SW

REQUEST# 13
GND

GND

GND

GND

GND

GND
IR

1 HWSDA R15 R/NC SDA_8205 READ Y# 1

READY# 13
HWSCL R16 R/NC SCL_8205

UP3_5 R17 0 F_A21

F_A21 9
UP3_4 R18 0 AD IN4
ADIN4 14
R9 URST#
URST# 1
Change by MTK 1k DV18A
DV18A 1,2
AD IN3 R365 10K
AD IN2 R366 10K
AD IN1 R367 10K
DV33A DV18A AD IN0 R368 10K

Title
DV33A DV18A

Size Doc Number Rev

C MT5205BGA388 V1.2
Date: Wednesday, October 12, 2005 Sheet 3 of 15
A B C D E
 A B C D E

DV18A

DA CVREF
DV18A 1,2,3 AV33 MT8205 ANALOG DECOUPLING&DIGITAL DECOUPLING DV33A
DACVREF 3
DA CFS
DACFS 3 L7
ADCPLLVDD1
ADCPLLVDD1 3
ADCPLLVDD
ADCPLLVDD 3 L6 DV18A ANALOGVDD

FOR DACVDD
APLLVDD
APLLVDD 3 L12
ANALOGVDD AV33 DACV DD FB C8
ANALOGVDD 3
VPLLVDD DV18A ADCPLLVDD1 BEAD/SMD/0603 4.7uF
VPLLVDD 3
LVDDA CE12 FB C7 CB10 C10 C0603/SMD
LVDDA 3
+ CB11 BEAD/SMD/0603 CE13 4.7uF 0.1uF FB 0.1uF GND
+ C0603/SMD C0603/SMD BEAD/SMD/0603 C24 CB32 R20
ADCV DD 10uF/25v 0.1uF GND 4.7uF 0.1uF ADCPLLVDD
ADCVDD 3
DACV DD 10uF/25v C0603/SMD C0603/SMD
4 DACVDD 3 4
AVCM DACV DD 0 C13 CB13
AVCM 3
VOCM + CE14 4.7uF 0.1uF
VOCM 3
VICM
VICM 3
C9 CB12 GND 22uF/25v C0603/SMD C0603/SMD
4.7uF 0.1uF
VREFP4
VREFP4 3
C0603/SMD C0603/SMD GND
V REFN4 GND
VREFN4 3
ADC VDD0
ADCVDD0 3
ADC VDD4 DACV DD ANALOGVDD
ADCVDD4 3
PWM2VREF
PWM2VREF 3
AUXTOP C14 CB14 C15 CB15
AUXTOP 3
AUXBOTTOM 4.7uF 0.1uF + CE15 4.7uF 0.1uF
AUXBOTTOM 3 47uF/16v
REXTA C0603/SMD C0603/SMD C0603/SMD C0603/SMD
REXTA 3
APLL_CAP GND
APLL_CAP 3 L14
XTALI
XTALI 3
GND
XTALO R101 0/NC ADC VDD0 ADCV DD
XTALO 3 VCC
FB
AVCM FOR ADCVDD R0805/SMD C27 CB36 R22
CB35 4.7uF 0.1uF APLLVDD
U8 CM1117-3.3V 0.1uF C0603/SMD C0603/SMD
CB45 ADC_VDD 0 C17 CB20
4.7uF L8 GND GND CE20 4.7uF 0.1uF
Vout +

ADJ/GND
GND 3 2 ADC _VDD 22uF/25v C0603/SMD C0603/SMD
IN OUT PWM2VREF
VOCM FB GND
BEAD/SMD/0805 + CE18 CB17 CB42
CB46 + 1 + CE17 10uF/25v CB16 + CE22 0.1uF
0.1uF CB18 220uF/16v 0.1uF 47uF/16v C0603/SMD ANALOGVDD
CE16 0.1uF SOT223/SMD 0.1uF
GND 100uF/16v GND C18 CB22
GND 4.7uF 0.1uF
C0603/SMD C0603/SMD
VICM GND
CB47
0.1uF

3 GND 3

AV33

VREFP4 ADC_VDD
R23
C0603/SMD 0
CB44 4.7uF L10
ADC VDD0 L11
CB48 G ND VPLLVDD
4.7uF FB CB24
C0603/SMD BEAD/SMD/0805 0.1uF FB C19 CB27
CB49 4.7uF C0603/SMD BEAD/SMD/0603 4.7uF 0.1uF
C0603/SMD GND C0603/SMD C0603/SMD
V REFN4 C20 GND
ADC VDD0 0.1uF

CB28 CB30 VPLLVDD

0.1uF 0.1uF
DV33A DIGITAL DECOUPLING + CE21 C21 CB29
GND 47uF/16v 4.7uF 0.1uF
C0603/SMD C0603/SMD
GND
ADC VDD0

CB33 CB43 CB25 CB26 CB31 C22 C23 VPLLVDD

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 3300pF
C25 CB34
GND 4.7uF 0.1uF
C0603/SMD C0603/SMD
AV33 GND

L13
2 2
ADC VDD4 R21
0
FB C26 CB41 DV18A
BEAD/SMD/0603 4.7uF 0.1uF L9
C0603/SMD LVDDA
GND
FB
BEAD/SMD/0603 CB19 0.1uF
CB37 CB38 CB39 CB40 CE19 C0603/SMD
0.1uF 0.1uF 0.1uF 0.1uF + GND
C0603/SMD C0603/SMD C0603/SMD C0603/SMD C16
0.1uF 47uF/16v
LVDDA
0603 PUT ON NEARLY BGA CB21 0.1uF
R19 C0603/SMD
DA CVREF C33 0.1uF/NC GND
GND
100k
C28 C29 C30 C31
APLL_CAP C32 1500pF GND 3300pF 3300pF 3300pF 3300pF LVDDA
XTALI XTALO C0603/SMD C0603/SMD C0603/SMD C0603/SMD

Y1 27MHz CB23 0.1uF

REXTA R24 3.3k GND C0603/SMD
GND
C11
33pF
C12
33pF 0603 PUT ON NEARLY BGA
GND DA CFS R27 560 GND
TP5

LVDDA L15 FB R25 50/47R AUXTOP

TP6

R26 50/47R AUXBOTTOM

1 1

Title

Size Doc Number Rev

C MT8205 DECOUPOMG--ANALOG V1.2
Date: Wednesday, October 12, 2005 Sheet 4 of 15
A B C D E
 A B C D E

SDV25 SDV25 U9
F_A1 25 29 F_ D0
RN1 U10 D1V25 F_A2 A0 D0 F_ D1
24 A1 D1 31
A_DQS[0..3] A_DQS[0..3] 3 A_RA3 7 8 D_RA3 1 66 F_A3 23 33 F_ D2
A_RA[0..11] A_RA[0..11] 3 A_RA2 D_RA2 D _DQ0 VDD VSS D_DQ15 RN2 F_A4 A2 D2 F_ D3
5 6 2 DQ0 DQ15 65 22 A3 D3 35
A_BA[0..1] A_BA[0..1] 3 A_RA1 3 4 D_RA1 3 64 D_RA0 7 8 F_A5 21 38 F_ D4
A_DQM[0..1] A_DQM[0..1] 3 A_RA0 D_RA0 D _DQ1 VDDQ VSSQ D_DQ14 D_RA1 F_A6 A4 D4 F_ D5
1 2 4 DQ1 DQ14 63 5 6 20 A5 D5 40
A_DQ[0..31] A_DQ[0..31] 3 D _DQ2 5 62 D_DQ13 D_RA2 3 4 F_A7 19 42 F_ D6
RN3 22x4 DQ2 DQ13 D_RA3 F_A8 A6 D6 F_ D7
6 VSSQ VDDQ 61 1 2 18 A7 D7 44
A_CLK A_CLK 3 A_RA4 7 8 D_RA4 D _DQ3 7 60 D_DQ12 F_A9 8 30
A_CLK# A_CLK# 3 A_RA5 D_RA5 D _DQ4 DQ3 DQ12 D_DQ11 75x4 F_A10 A8 D8
5 6 8 DQ4 DQ11 59 7 A9 D9 32
A_CKE A_CKE 3 A_RA6 3 4 D_RA6 9 58 RN4 F_A11 6 34 DV33A
A_CS# A_CS# 3 A_RA7 D_RA7 D _DQ5 VDDQ VSSQ D_DQ10 D_RA4 F_A12 A10 D10
1 2 10 DQ5 DQ10 57 8 7 5 A11 D11 36
A_RAS# A_RAS# 3 D _DQ6 11 56 D _DQ9 D_RA5 6 5 F_A13 4 39
A_CAS# A_CAS# 3 RN5 22x4 DQ6 DQ9 D_RA6 F_A14 A12 D12 DV33A
12 VSSQ VDDQ 55 4 3 3 A13 D13 41
A_WE# A_WE# 3 A_RA8 7 8 D_RA8 D _DQ7 13 54 D _DQ8 D_RA7 2 1 DV33A F_A15 2 43 R28
SDV25 SDV25 3 A_RA9 D_RA9 DQ7 DQ8 F_A16 A14 D14 F_A0
4
5 6 14 NC NC 53 1 A15 D15 45 4
V REF VREF 3 A_RA11 3 4 D_RA11 15 52 75x4 F_A17 48 16 F_A19
RWR# PWR# 13 D_DQS0 VDDQ VSSQ D_DQS1 RN6 F_A18 A16 A18 10k R29
1 2 16 LDQS UDQS 51 17 A17 NC 13
PCE# PCE# 3 17 50 2 1 15 14 0
F_OE# F_OE# 3 22x4 NC NC V REF D_RA11 4 R30 F_A20 RY/BY WP/ACC
18 VDD VREF 49 3 9 A19 BYTE 47
F_ D[0..7] F_D[0..7] 3 A_RA10 R31 22 D_RA10 19 48 D_RA9 6 5 Del By Ada 10
F_A[0..20] F_A[0..20] 3 D_DQM0 DNU VSS D_DQM0 CB50 D_RA8 PCE# A20 FLASHVCC
20 LDM UDM 47 8 7 26 CE VCC 37
D _WE# 21 46 D_CLK# 10k F_OE# 28
RN7 D_CAS# WE CK D_CLK 75x4 PWR# OE
22 CAS CK 45 11 WE GND1 27
A_DQ0 7 8 D _DQ0 D_RAS# 23 44 D_CKE 0.1uF 46 CB51
A_DQ1 D _DQ1 D_CS# RAS CKE D_RA10 R32 75 GND2 0.1uF
5 6 24 CS NC 43 DV33A 12 RESET
A_DQ2 3 4 D _DQ2 25 42
A_DQ3 D _DQ3 D_BA0 NC A12 D_RA11
1 2 26 BA0 A11 41
D_BA1 27 40 D_RA9 RN8 MX29LV160BT
RN9 47x4 D_RA10 BA1 A9 D_RA8 D _DQ0
28 A10/AP A8 39 7 8 TSOP 48 pin
A_DQ4 7 8 D _DQ4 D_RA0 29 38 D_RA7 D _DQ1 5 6
A_DQ5 D _DQ5 D_RA1 A0 A7 D_RA6 D _DQ2 D1V25
5 6 30 A1 A6 37 3 4
A_DQ6 3 4 D _DQ6 D_RA2 31 A2 8M x 16 A5 36 D_RA5 D _DQ3 1 2
A_DQ7 1 2 D _DQ7 D_RA3 32 35 D_RA4 D1V25
A3 DDR A4 75x4
33 VDD VSS 34
RN10 47x4 RN11
A_DQ8 7 8 D _DQ8 M13L128168 8Mx16-6 D _DQ4 7 8
A_DQ9 5 6 D _DQ9 D _DQ5 5 6 CB52 CB53 CB54 CB55 CB56 CB57 CB58 CB59 CB77
A_DQ10 3 4 D_DQ10 D _DQ6 3 4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A_DQ11 1 2 D_DQ11 D _DQ7 1 2

RN12 47x4 75x4

A_DQ12 7 8 D_DQ12 RN13
A_DQ13 5 6 D_DQ13 D _DQ8 7 8
A_DQ14 3 4 D_DQ14 D _DQ9 5 6 D1V25
A_DQ15 1 2 D_DQ15 D_DQ10 3 4
D_DQ11 1 2
47x4
SDV25 SDV25 75x4 CB60 CB61 CB62 CB63 CB64 CB65 CB66 CB67 CB78
RN14 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RN15 U11 D_DQ12 7 8
A_DQ16 7 8 D_DQ16 1 66 D_DQ13 5 6
A_DQ17 D_DQ17 D_DQ16 VDD VSS D_DQ31 D_DQ14 3
5 6 2 DQ0 DQ15 65 4
3 A_DQ18 3 4 D_DQ18 3 64 D_DQ15 1 2 3
A_DQ19 D_DQ19 D_DQ17 VDDQ VSSQ D_DQ30
1 2 4 DQ1 DQ14 63
D_DQ18 5 62 D_DQ29 75x4 D1V25
RN16 47x4 DQ2 DQ13 RN17
6 VSSQ VDDQ 61
A_DQ20 7 8 D_DQ20 D_DQ19 7 60 D_DQ28 D_DQ16 2 1
A_DQ21 5 D_DQ21 D_DQ20 DQ3 DQ12 D_DQ27 D_DQ17 4
6 8 DQ4 DQ11 59 3
A_DQ22 3 4 D_DQ22 9 58 D_DQ18 6 5 CB68 CB69 CB70 CB71 CB72 CB73 CB74 CB75 CB76
A_DQ23 1 D_DQ23 D_DQ21 VDDQ VSSQ D_DQ26 D_DQ19 8 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2 10 DQ5 DQ10 57 7
D_DQ22 11 56 D_DQ25
RN18 47x4 DQ6 DQ9 75x4
12 VSSQ VDDQ 55
A_DQ24 7 8 D_DQ24 D_DQ23 13 54 D_DQ24 RN19
A_DQ25 D_DQ25 DQ7 DQ8 D_DQ20 2
5 6 14 NC NC 53 1
A_DQ26 3 4 D_DQ26 15 52 D_DQ21 4 3 D1V25
A_DQ27 D_DQ27 D_DQS2 VDDQ VSSQ D_DQS3 D_DQ22 6
1 2 16 LDQS UDQS 51 5
17 50 D_DQ23 8 7
RN20 47x4 NC NC V REF + CE24 C34
18 VDD VREF 49
A_DQ28 7 8 D_DQ28 19 48 75x4 3300pF C35 C36 C37 C38 C39 C40 C41
A_DQ29 5 D_DQ29 D_DQM1 DNU VSS D_DQM1 CB79 RN21 220uF/16v 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF
6 20 LDM UDM 47
A_DQ30 3 4 D_DQ30 D _WE# 21 46 D_CLK# D_DQ27 1 2
A_DQ31 1 D_DQ31 D_CAS# WE CK D_CLK D_DQ26 3
2 22 CAS CK 45 4
D_RAS# 23 44 D_CKE 0.1uF D_DQ25 5 6
47x4 D_CS# RAS CKE D_DQ24 7
24 CS NC 43 8
25 NC A12 42
D_BA0 26 41 D_RA11 75x4
A_DQS0 R33 47 D_DQS0 D_BA1 BA0 A11 D_RA9 RN22
27 BA1 A9 40
D_RA10 28 39 D_RA8 D_DQ31 1 2
A_DQS1 R34 47 D_DQS1 D_RA0 A10/AP A8 D_RA7 D_DQ30 3
29 A0 A7 38 4
D_RA1 30 37 D_RA6 D_DQ29 5 6
A1 A6
A_DQS2 R35 47 D_DQS2 D_RA2 31 A2 8M x 16 A5 36 D_RA5 D_DQ28 7 8
D_RA3 32 35 D_RA4
A_DQS3 R36 47 D_DQS3 A3 DDR A4 75x4
33 VDD VSS 34

RN23 SDV25
M13L128168 8Mx16-6/NC FOR ENTRY
D_RAS# 7 8
D_CS# 5 6 SDV25 SDV25
RN24 D_BA0 3 4
A_CS# 7 8 D_CS# D_BA1 1 2
A_RAS# 5 6 D_RAS#
2 2
A_CAS# 3 4 D_CAS# 75x4 CB80 CB81 CB82 CB83 CB84 CB85 CB86 CB87
A_WE# 1 2 D _WE# 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R41 4.7k
22x4 D_DQS2 R37 75
A_BA1 R38 22 D_BA1 D1V25 U12 SDV25
1 8 D_DQS3 R39 75
A_BA0 R40 22 D_BA0 GND VTT
2 SD PVIN 7
D1V25 3 6 D_CAS# R42 75 SDV25
A_DQM0 R43 22 D_DQM0 V REF VSENSE AVIN
4 VREF VDDQ 5
TP7 D _WE# R44 75
A_DQM1 R45 22 D_DQM1 IC LP2996 DDR Termination SOP8 + CE25 CB91 CB92 CB93 CB94
47uF/16v D_DQM1 R46 75 CB88 CB89 CB90
A_CKE R47 22 D_CKE 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
CB95 CB96 + CE26 D_DQS1 R48 75
A_CLK R49 22 D_CLK 220uF/16v
0.1uF 0.1uF D_DQS0 R50 75
A_CLK# R51 22 D_CLK#
D_DQM0 R52 75 SDV25

SDV25 C42 C43 C44 C45 C46 C47 C48 C49

3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF

SDV25

SDV25
CB105 CB106 CB107 CB108 CB109 VCC
VREF U13 CM1117-2.5V
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
L16 CB97 CB98 CB99 CB100 CB101 CB102 CB103 CB104
ADJ/GND

V REF 3 2 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

IN OUT
FB
VREF BEAD/SMD/0805 + CE27 + CE28 + CE29 + CE30
VREF DECOUPLING 220uF/16v 220uF/16v 220uF/16v 220uF/16v
1

+ CE31
1 V REF SOT223/SMD 1
220uF/16v

CB110 CB111 CB112 CB113 CB114

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

Title

Size Doc Number Rev

C DDR MEMORY&FLASH V1.2
Date: Wednesday, October 12, 2005 Sheet 5 of 15
A B C D E
 A B C D E

VGA_IN_L
VGA_IN_L 12
VGA_IN_R
VGA_IN_R 12
P2 HSYNC_VGA
HSYNC_VGA 3
VGAVSYNC#
VGAVSYNC# 3
RED_GND
RED_GND 8
R 1 VGA_R R56 15K VGA_IN_R GRN_GND
GRN_GND 8
2 BLU_GND
BLU_GND 8
3 R ED
4 RED 8 4
L 4 VGA_L R58 15K VGA_IN_L GREEN
GREEN 8
PHONEJACK STEREO G BLUE
BLUE 8
RSRXD
RSRXD 1
PHONEJACK/DIP RSTXD
RSTXD 1

K1
K2
K3
K4
K5
R59 R60

75K
75K
Change by MICO

L17 R ED
VSYNC# VGAVSYNC#
Change by MICO

2
FB
BEAD/SMD/0603 R61 D13
2.2k C50 HSYN C#
0.1uF

2
SOT23/SMD VCC
Modified by Bin_wang.22/7/05 D16

3
RED_GND
SOT23/SMD
VCC GREEN
L18

3
GND
3 3

2
HSYN C# HSYNC_VGA
D14
FB VSYNC# VCC

2
BEAD/SMD/0603 R62 SOT23/SMD
2.2k C51 D17

3
5pF GRN_GND
SOT23/SMD VCC
BLUE

3
GND

2
D15
SOT23/SMD
VGA_PLUGPWR VCC

3
P3 BLU_GND
VGA_PLUGPWR

16
VGA_PLUGPWR D-SUB15 FEMALE
DSUB15/DIP/F
RSRXD 11 1 R ED
6 RED_GND VCC
VGASDA R55 100 VGA_SDA 12 2 GREEN
CB115 R53 R54 7 GRN_GND DIODE SMD
U14 10k 10k HSYN C# BLUE 1N4148/SMD D2
2 13 3 2
1 8 8 BLU_GND
NC VCC D3 DIODE SMD
0.1uF 2 7 VSYNC# 14 4 RSTXD
NC WP VGASCL VGA_PWR VGA_PLUGPWR 1N4148/SMD
3 NC SCL 6 9
4 5 VGASDA VGASCL R57 100 VGA_SCL 15 5
GND SDA
10
EEPROM 24C02 GND

17
1 1

Title

Size Doc Number Rev

B VGA IN&PC AUDIO IN V1.2
Date: Wednesday, October 12, 2005 Sheet 6 of 15
A B C D E
 A B C D E

Y
Y 8
Y_G ND
Y_GND 8
CB
CB 8
CB _GND
CB_GND 8
CR TU_VCC C122 4.7nF Y1 SOY
CR_GND
CR
CR_GND
8
8
J5 COMPONENTS SWITCH.
SOY
S Y_IN
SOY 3 TUNER IN TU_12V
1
SY_IN 8 2
SY_ GND1
SY_GND1 8 3
SC _IN Y1_I NB R63 0 Y1B CE32 22uF/10V Y1SWB VCC
SC_IN 8 4 VCC
SC_GND1 VCC

+
SC_GND1 8 5
AV2_IN SDA VCC
AV2_IN 8,12 6
AV2_GND S CL

2
AV2_GND 8 7
TV SIF1_OUT R64 R68
TV 8,12 8
TV_GND AF1_OUT 75 10K L20 R67 L19
4 TV_GND 8 9 D4 4
AV1_IN FB 10K FB
AV1_IN 8,12 10 BAV99
AV1_GND TV_GND U16 U15
AV1_GND 8 11
TV Y1_ GNDB Y1_ GNDB ORO2 1 16 GPIO_DVD0 1 16

3
SIF1_OUT 12 CB1SWB S VCC GN DS C BQ S VCC GN DS
SIF1_OUT 8 2 I0A E# 15 2 I0A E# 15
AF1_OUT CON12 CB2SWB 3 14 Y1 SOY CB3SWB 3 14 SO YQ
AF1_OUT 8 I1A I0D I1A I0D
S CL PH12/2.0 C BQ 4 13 Y2 SOY CB 4 13 Y3 SOY
SCL 1,10 YA I1D YA I1D
SDA Y1SWB 5 12 SO YQ YQ 5 12 SOY
SDA 1,10 P4 VCC I0B YD I0B YD
Y2SWB 6 11 CR 1SWB Y3SWB 6 11 CRQ
TUNER_12V Y2_I NB Y1_I NB CB1_INB R65 0 CB1B CE33 22uF/10V CB1SWB YQ I1B I0C CR 2SWB Y I1B I0C CR 3SWB
TUNER_12V 1 2 3 7 YB I1C 10 7 YB I1C 10

2
1 Y1_ GNDB GN DS 8 9 CRQ GN DS 8 9 CR

+
OGO[0..6] OGO[0..6] 3,9,13 C129 GND YC GND YC
ORO2 100pF CB2_INB 5 6 CB1_INB C117 D5 IDTQS3VH257/TIV330 IDTQS3VH257/TIV330
ORO2 3 100pF
AV_L 4 CB1_GNDB BAV99 R66 TSSOP16/SMD TSSOP16/SMD
AV_L 12
AV_R C130 75
AV_R 12

3
100pF CR 2_INB 8 9 CR 1_INB C127
YPBPR1_L 7 C R1_GNDB 100pF CB1_GNDB CB1_GNDB
YPBPR1_L 12
Y PBPR1_R C131
YPBPR1_R 12
YPBPR2_L 100pF RCA1X3 EMC Ready
YPBPR2_L 12
Y PBPR2_R RCA5/9P/Y C128 VCC
YPBPR2_R 12 100pF
DVI_L P5 CR 1_INB R69 0 CR 1B CE35 22uF/10V CR 1SWB SO YQ R311 0 SOY
DVI_L 12
DV I_R YPB PR1/R 3 1 YPBPR1/L

+
DVI_R 12

2
YQ R312 0 Y
R70
+12V YPB PR2/R 4 2 YPBPR2/L VCC
+12V 1,10,13,14 75
J8 D6 C BQ R313 0 CB 9/05
OGO6 RCA2 BAV99
OGO6 3

5
GPIO_DVD0 GPIO_DVD0 3 1 DVI/R RCA2X2/6P/DIP R272 CRQ R314 0 CR

3
GPIO GPIO 3,10 2 GND C R1_GNDB C R1_GNDB 47k
CE82
GPIO_DVD2 GPIO_DVD2 3 3 DV I/L
IR IR 3,11 4 GND AV1_L
VCC

+
4x1 W/HOUSING P7 P6 C123 4.7nF Y2 SOY R274VCC VCC
22uF/25v
DIP4/W/H/P2.0 1DV I/L 1 AV1_IN 47k
2
VCC 2 DVI/R C52
L22 AV1_R 100pF R275 VCC
3
TU_VCC 4 AV1_L Y2_I NB R71 0 Y2B CE37 22uF/10V Y2SWB 47k
CE83
5
3
4

2
Change by MICO L21

+
RCA2
3 FB CE41 RCA2/4P/DIP 5 AV1_GND AV1_R FB 3
+ 6 D7

+
R72
C53 BAV99 VCC R276
1000uF/16v 0.1uF RCA1X3 22uF/25v 47k
75

3
RCA2X2/6P/DIP Y1_ GNDB Y2_ GNDB
J6 R277

TUNER_12V AV2_IN
AV1 & S-VIDEO AUDIO IN CE84
47k R299 R300
10K
CB116
0.1uF
1
2 AV2_GND VCC AV2_L 10K
L23 AV2_L
3

+
TU_12V 4 AV2_R CB2_INB R74 0 CB2B CE39 22uF/10V CB2SWB R278 U17
22uF/25v

2
47k VCC 12 16

+
FB + CE42 4x1 W/HOUSING 0X VCC
1 0Y
1000uF/16v C54 DIP4/W/H/P2.0 D8 R75 14 3 A V/R
0.1uF JP1 BAV99 75 1X Y AV/L
5 1Y X 13
CON\SVHS R279 15 2X

3
SC _IN 2 3 S Y_IN CB1_GNDB CB2_GNDB 47k 2
CE85 2Y
SC_GND1 1 4SY_ GND1 11 6
AV2_R 3X INH
4 3Y
7 5 VCC VCC OGO6 10 7

+
R280 GPIO_DVD0 A VEE
22uF/25v 9 B VSS 8
VCC 47k
6

CR 2_INB R76 0 CR 2B CE40 22uF/10V CR 2SWB CD 4052BC

R281 SOP16/SMD

+
2
47k
CE86
R11 J7
VCC 10k/NC D9 R77 DV D/L ADD BY MICO
D VD/R 1 BAV99 75 VCC

+
8/18 modify by steven DV D/L 2 R282
22uF/25v

3
R12 3 C R1_GNDB C R2_GNDB 47k AV1_L R350 0/NC AV/L
10k DVD_ IR 4
DVD /CB_GND 5 R283 AV1_R R351 0/NC A V/R
DVD /CB_IN 6 VCC 47k
R107 SOT-23 CE87
3

4.7K DVD/Y_GND 7 C124 4.7nF Y3 SOY

GPIO_DVD2 2N3904 DV D/Y_IN D VD/R
1 8
Q3 DVD/CR _GND 9

+
DVD/CR_ IN 10 10x1 W/HOUSING R285
22uF/25v
2

47k
2 2
PH10/2.0 DV D/Y_IN R78 0 Y3BCE34 22uF/10V Y3SWB
IR

+
2

R79
75
D10
BAV99
Y_G ND FB5 0
1

DVI/R 15K R86 DV I_R DVD/Y_GND Y3_ GNDB

CB _GND FB4 0
DV I/L 15K R84 DVI_L
CR_GND FB3 0 VCC
YPB PR2/R 15K R97 Y PBPR2_R +12V
DVD /CB_IN R85 0 CB3B CE36 22uF/10V CB3SWB
2

YPBPR2/L 15K R94 YPBPR2_L

+

NEARLY YPBPR2-CON. A V/R 15K R103 AV_R D11

Y2_ GNDB FB6 0 BAV99 R89
AV/L 15K R102 AV_L 75 VCC VCC
1

CB2_GNDB FB7 0 R267 R268

YPB PR1/R 15K R92 Y PBPR1_R DVD /CB_GND CB3_GNDB 22K 22K
J9
C R2_GNDB FB10 0
L48
YPBPR1/L 15K R87 YPBPR1_L U26 DVD+5V 5
VCC 4 5 DVD+5V DVD+5V 4
DVD/CR_ IN R98 0 CR 3B CE38 22uF/10V CR 3SWB G2 D2
3 S2 D2 6 FB 3
Y1_ GNDB FB11 0 R269 2 7 GND 2
+

G1 D1 BEAD/SMD/1206
2

R118 R119 R120 R121 R122 R123 R124 R125 1 8 GND 1

CB1_GNDB FB12 0 75K 75K 75K 75K 75K 75K 75K 75K R100 10K S1 D1
D12 75 IR7314
C R1_GNDB FB13 0 BAV99 5x1 W/HOUSING R.A.
SOT-23 PH5/2.5
1

3
NEARLY YPBPR1-CON. DVD/CR _GND C R3_GNDB
GPIO
R95
1
2N3904
Q2
VCC 4.7k

2
1 1
Change by MTK

Title

Size Doc Number Rev

C VIDEO IN & TUNER IO V1.2
Date: Wednesday, October 12, 2005 Sheet 7 of 15
A B C D E
 A B C D E

R128 C55
Y Y+

100
VGASOG 47nF
VGASOG 3
RED+ C56
RED+ 3 R130 15pF
C57
R ED- TV R90 18 CVBS0 CVBS0+ R131 C58
RED- 3
Y_G ND Y-
22
GREEN+ 47nF 100
GREEN+ 3
R93 C59 47nF
GREEN- 56 330pF
GREEN- 3
R132 C60 R133 C61
BLUE+ TV_GND CVBS0_GND CVBS0- CB CB+
BLUE+ 3
4 4
BLUE- 0 100
BLUE- 3
FB2 47nF 47nF
C62
0 15pF
CB+
CB+ 3
R136 C64
CB- R135 C63 CB _GND CB-
CB- 3
AV1_IN R80 18 CVBS1 CVBS1+
CR+ 100
CR+ 3
22 47nF
C R- R82 47nF R137 C66
CR- 3
56 CR CR+
Y+ C65
Y+ 3 330pF 100
Y- R138 C67 47nF
Y- 3
AV1_GND CVBS1_GND CVBS1- C68
15pF
SY+ FB1 0
SY+ 3
47nF R141 C70
S Y- 0 CR_GND C R-
SY- 3
R105
R140 C69 100
SC+ AV2_IN CVBS2 CVBS2+ 47nF
SC+ 3
SC- 18 22
SC- 3
47nF
R111
R108 R143
CVBS0+ 56 C71 C73
CVBS0+ 3 330pF S Y_IN SY SY+
CVBS0- R142 C72
CVBS0- 3
AV2_GND CVBS2_GND CVBS2- 22
0 R110 47nF
CVBS1+ FB8 0 75 C74
CVBS1+ 3 330pF
47nF
CVBS1- 0 Close to 8205. R144 C75
CVBS1- 3
SY_ GND1 SY_GND S Y-
CVBS2+
CVBS2+ 3
3 FB9 0 3
CVBS2- 47nF
CVBS2- 3 0

R114 R145 C76

MPX1 SC _IN SC SC+
MPX1 3
MPX2 0 22
MPX2 3
R116 C77 47nF
75 330pF
CE43 R148

FROM Tuner
C79
SC_GND1 SC _GND SC-

+
OUTPUT 0
47uF/16v /NC FB14 47nF

C78 0 Close to 8205.

SIF1_OUT R146 0 R147 8.2K MPX1
Y
Y 7
Y_G ND 47nF
Y_GND 7
C80 C81
CB 15pF/NC 15pF/NC
CB 7
CB _GND L24 C83
CB_GND 7
C82 RED RED_ IN R151 68 RED+
CR
CR 7
FB R152
CR_GND BEAD/SMD/0603 47nF
CR_GND 7
47nF/NC 75
SOY
SOY 3,7 CE44 C86
S Y_IN AF1_OUT R149 39k R150 39k MPX2 5pF C87
+

SY_IN 7
RED _GND R153 100 R ED-
SY_ GND1
SY_GND1 7
47uF/16v
C84 C85 L25 47nF
SC _IN 15pF 15pF
2 SC_IN 7 FB 2
C88
SC_GND1 R154 0 VGASOG
SC_GND1 7
4.7nF

AV2_IN L26 C89

AV2_IN 7,12
GREEN GREEN_IN R155 68 GREEN+
AV2_GND
AV2_GND 7
FB
TV BEAD/SMD/0603 47nF
TV 7,12
R156
TV_GND C90
TV_GND 7 5pF
75
C91
AV1_IN GRN_ GND R157 100 GREEN-
AV1_IN 7,12
AV1_GND
AV1_GND 7
L27 47nF

SIF1_OUT FB
SIF1_OUT 7
AF1_OUT
AF1_OUT 7
L28 C92
RED BLUE BLUE_IN R158 68 BLUE+
RED 6
GREEN FB
GREEN 6
BEAD/SMD/0603 47nF
BLUE R159
BLUE 6
C93
75 5pF
RED _GND C94
RED_GND 6
BLU_GND R160 100 BLUE-
GRN_ GND
GRN_GND 6
BLU_GND L29 47nF
BLU_GND 6
FB
1 1

Close VGA input interface Close to MT8205

INPUT

Title

Size Doc Number Rev

C AUDIO/VIDEO IN CIRCUIT V1.2
Date: Wednesday, October 12, 2005 Sheet 8 of 15
A B C D E
 A B C D E

VI[0..23] VI[0..23] VCC

DV IODCK
DVIODCK
DV IDE P8 DVI-I DIP 34P DIODE SMD
DVIDE
DV IHSYNC 1N4148/SMD D22

27
25
DVIHSYNC
DVIVSY NC DVIPWR DVIPWR DVIPWR DVIPWR DVIPWR DVIPWR DVIPWR
DVIVSYNC
8205UP1_2 DATA2- 1 13 D18
8205UP1_2
OGO4 OGO4 DATA2+ 2 14 DVI_PLUGPWR 1N4148/SMD
DVISCL 3 15
DVISCL
DVISDA 4 16
DVISDA
F_A21 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C100 C101 C102 C103 5 17 DATA0-
F_A21 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v 220pF 10uF/10v DDCD VISCL R161 100 DDC _SCL 6 18 DATA0+
DDCD VISDA R162 100 DDC _SDA 7 19 R163
DVISCDT R167 R DVIPDO# 8 20 10k
4 4
DVICAB R177 0 8205UP1_2 DATA1- 9 21
DATA1+ 10 22
Add By MTK 11
12
23
24
CLOCK+
CLOCK- DVICAB

CLOCK+ CLOCK- DDC _SCL DDC _SDA 29 31

33 34

2
30 32
D29 D30 D31 D32 R164
SOT23/SMD SOT23/SMD SOT23/SMD SOT23/SMD 100k
DV33

28
26
VCC VCC VCC VCC
L31

3
DVIPWR GND GND GND GND
DVIP WR

FB
+ CE45

Add By MTK
CB117 DVIP WR DVIP WR
100uF/16v
0.1uF
DATA0- DATA1- DATA2-

2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
D33 D34 D35
SOT23/SMD SOT23/SMD SOT23/SMD

QO22
QO21
QO20
QO19
QO18
QO17
QO16

QO15
QO14
QO13
QO12
QO11
QO10
QO9
QO8

QO7
QO6
QO5
QO4
QO3
QO2
GND
VCC

OGND
OVCC
VCC VCC VCC
L32

3
76 50 GND GND GND
D VIAVCC OGND QO1
DVIP WR 77 49
DVIP WR QO23 QO0 DVIHSYN C0
78 48 DATA0+ DATA1+ DATA2+
OVCC HSYNC DVIV SYNC0
FB BEAD/SMD/0603 79 47
DATA2+ AGND VSYNC DVIDE0

2
CB118 80 46
C95 C96 DATA2- RX2+ DE
81 45 D36 D37 D38
10uF/10v 0.1uF 220pF D VIAVCC RX2- OGND DVIODCK0
82 AVCC ODCK 44 TP8 SOT23/SMD SOT23/SMD SOT23/SMD
83
84
AGND
AVCC
U18 OVCC
CTL3
43
42 CTL3
TP9 VCC VCC VCC

3
DATA1+ 85 41 OCK_INV GND GND GND
RX1+ CTL2 TP10
3 DATA1- 86 40 HS_DJTR 3
RX1- CTL1 TP11
87 AGND GND 39

DVIAVCC
88
89
AVCC
AGND
SiI 161B VCC
QE23
38
37 DVI23
CHANGE
DATA0+ 90 36 DVI22
DATA0- RX0+ QE22 DVI21
91 RX0- QE21 35
92 34 DVI20
R165 CLOCK+ AGND QE20 DVI19
93 RXC+ QE19 33
390 CLOCK- 94
95
RXC- SiI 169 QE18 32
31
DVI18
DVI17
DVIHSYN C0
DVIV SYNC0
2 RN25
4
1
3
DV IHSYNC
DVIVSY NC DVIPWR
EXT_RST AVCC TQFP100/SMD QE17 DVI16
96 30 DVIDE0 6 5 DV IDE DVIPWR
D VIPVCC EXT_RST QE16
97 29 DVIODCK0 8 7 DV IODCK
PVCC OVCC
98 28 33x4
R83 PGND OGND DVI15
0/NC 99 27 R170
DVISCL RESERVED QE15 DVI14
100 26 10k R171
OCK_INV QE14

STAG_OUT
L33 DVI20 VI20
2 RN26 1 10k

HS_DJTR
DVIP WR D VIPVCC DVI21 4 3 VI21

OGND
OVCC
C134 DVI22 VI22

SCDT

QE10
QE11
QE12
QE13
6 5

PIXS
GND

PDO
VCC

QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7

OE8
QE9
PD#
FB BEAD/SMD/0603 1uF/25V/NC R81 DVI23 8 7 VI23 RED DVIPD# DVIPDO#

ST
10k/NC 33x4
C97 C98 DVI16 2 RN27 1 VI16 R344

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10uF/10v 220pF DVI17 4 3 VI17 R176
ADD BY MTK DVI18 6 5 VI18 R/NC R/NC
DVIP WR DVIP WR DVI19 8 7 VI19
DVI_PLUGPWR 33x4

DVI10
DVI11
DVI12
DVI13
M_S#
DVI0
DVI1
DVI2
DVI3
DVI4
DVI5
DVI6
DVI7

DVI8
DVI9
DVISCDT
DVIPDO#
DVISTAG
DVIRST#

DVIPIXS
DVI12 2 RN28 1 VI12

DVISDA
DVIPD#
DVI_PLUGPWR DVI13 4 3 VI13
DVI_PLUGPWR CHANGE DVI14
DVI15
6 5 VI14
VI15
8 7
33x4 GREEN
R310 D VI8 2 RN29 1 VI8
R168 R169 10k D VI9 4 3 VI9
C99 U19 10k 10k DVI10 VI10
6 5

0.1uF
1 NC VCC 8 DVI11 8 7
33x4
VI11 WHEN USE Sil169//Sil161 ADD R175 , NC R345
2 NC WP 7
2
3 NC SCL 6 DDCD VISCL
DDCD VISDA OGO4 R166 0 D VI4 VI4
WHEN USE Sil1169 ADD R345,NC R175 2
4 GND SDA 5 2 RN30 1
D VI5 4 3 VI5 DVIPWR
D VI6 6 5 VI6
TP12
EEPROM 24C02 D VI7 8 7 VI7
33x4 BLUE R345
D VI0 2 RN31 1 VI0 10k/NC
D VI1 4 3 VI1
D VI2 6 5 VI2 DVIPIXS
DVI_PLUGPWR D VI3 8 7 VI3 Add by MTK
DVIPWR 33x4

R175
0

R88
0/NC
R322 R323 R324 R325 DVIPWR
4K7 4K7 4K7 4K7 DVIPWR DVIPWR DVIP WR
DVIPWR
R0603/SMD DVISDA DVISCL
R326
QF3 10K R346 R327 R328 R329
DDCD VISCL 2 3 DVISCL 10k/NC 4.7K/NC 4.7K/NC 4k7/NC
R173 R174
MOSFET N 2N7002 M_S# 10k/NC 10k/NC
DV33A SOT23/SMD F_A21 R330 0 DVIRST#
1

R347 HS_DJTR OCK_INV DVISTAG

10k/NC
R172
QF4 0.1uF R331 R332 R333
DDCD VISDA 2 3 DVISDA 0 0 0
DVISCL REPLACE OCK_INV NET
DV33A
MOSFET N 2N7002 When Sil169/Sil161 R346 NC
SOT23/SMD
Add R347 DVISDA REPLACE ST
1

1 1
WHEN SIL161 ADD R173 R174
R91
WHEN USE Sil169/sil1169 ADD WHEN Sil169/ Sil1169 R173 R174 NC
When use Sil169//Sil1169 R172 NC,Add R326 WHEN USE Sil1169 add R331 R332 When use Sil169/Sil1161 ADD R333
WHEN USE Sil169 add R327 R332
0/NC WHhen use Sil161 R326 NC,Add R172 WHEN USE Sil161 NC R331 R332
R0603/SMD

Title

Size Doc Number Rev

C DVI INPUT V1.2
Date: Wednesday, October 12, 2005 Sheet 9 of 15

A B C D E
 A B C D E

LVDS OUT(Include PDP and 32' LCD LVDS interface)

+12V
+12V 1,7,13,14
CLK1+
CLK1+ 3
CLK1-
CLK1- 3 5VSB
DV33A

AP[0..7]
AP[0..7] 3
A N[0..6] AN[0..6] 3
R
R 3
G
G 3
B
4 B 3 4
VS YNC
VSYNC 3 J10
H SYNC
HSYNC 3
R361 R362 R363 ORO5 Repalce ADIN2
10K 10K 10K R301 R302 R303 8205UP1_4 Repalce ADIN3 A N0 1
S CL 10K 10K 10K AP0 2
SCL 1,7
SDA A N1 3
SDA 1,7
ORO6 A N6 R290 0/NC AP1 4
ORO6 3
GPIO ORO5 R291 0/NC CPUGO A N2 5
GPIO 3,7
+12V AP6 R292 0/NC AP2 6
ORO1 8205UP1_4R293 0/NC PDPGO 7
ORO1 3,14
ORO3 CLK1- 8
ORO3 3,14
CLK1+ 9
ORO5 + CE46 AP7 R178 0/NC A N3 10
ORO5 3 220uF/16v
8205UP1_4 AP3 11
8205UP1_4 3
A N4 12
SCL1 GPIO R179 0/NC SEL_AP7_IRQ AP4 13
SCL1 12
SDA1 14
SDA1 12
A N5 15
SCL_8205 AP5 16
SCL_8205 3
SDA_8205 +12V 17
SDA_8205 3 VCC 5VSB DV33A
Change by MICO 18
19
5VSB 20
DV33A R180 R286 21
Change by MICO 4.7k/NC 4.7k 22
23
24
R364 R184 DI SPEN_PDWN_READY R185 0 25
F1 10K 10k SCL_P R186 100/NC 26
L34

2
FB L51 BEAD/SMD/1206 4.7k SDA_P R187 100/NC 27
FB L52 BEAD/SMD/1206 LVDSVDD ORO6 1 28
LVDSVDD L49 FB 29
FB R189 SOT23/SMD BEAD/SMD/1206 30

3
4A/?v 2N3904
BEAD/SMD/1206 FUSE/DIP/P10.0 + CE47 Change By MTK
Ada Q4
330uF/25v FI-SE30P-HF
C330UF25V/D8H14 LVDS/30P/P1.25/S
3 3
+ +
CE48 CE49 CB119 CB120
220uF/16v 220uF/16v 0.1uF 0.1uF

WHEN USE LG V6 PDP ,ADD R185 R286 ,Must del R193 R194
WHEN USE LG V7 PDP ,ADD R185 R286 R179
WHEN USE SangsungSD1 PDP ,ADD R186 R187 R185 R286
WHEN USE Fujitsu 42 PDP ,ADD R179 R186 R187 R185 R286 R291 R293.REMOVE R178 R290 R292

WHEN NOT USE PDP ADD L49 R178 R290 R292

REMOVE R179 R185 R186 R187 R291 R293
ORO1
ORO1 3,14
4.7K REPALAC 47K
ORO3
ORO3 3,14

2 2
5VSB DV33A R
R188 0 SCL1
R195
R181 R182
4.7k 4.7k R297 75 1%
R183 0
QF1
4.7k
2 3 SCL_8205 R192 0 SCL_P GND CRT OUT J11
S CL
MOSFET N 2N7002 G 1
5VSB DV33A SOT23/SMD R295 0 SDA1 R 2
1

R196 G 3
R191 B 4
4.7k 75 1% 5
QF2 R298 H SYNC 6
SDA 2 3 SDA_8205 0 VS YNC 7
GND 8
5VSB DV33A MOSFET N 2N7002 R296 0 SDA_P
SOT23/SMD B
1

DV33A GND
R197
R348 R349 R352 R353
75 1% 8x1 W/HOUSING
10K 10K 10K 10K DIP8/W/H/P2.54

ORO1 R193 0/NC GND

ORO3 R194 0/NC

CHANGE

1 1

Title

Size Doc Number Rev

C LVDS/CRT OUT V1.2
Date: Wednesday, October 12, 2005 Sheet 10 of 15
A B C D E
 A B C D E

OBO[0..7] OBO[0..7] 3

PANEL INVERTER POWER

IR
IR 3,7
PWR_ GND
PWR_GND 1
INVERTER_PWR In verter_PWR In verter_PWR
INVERTER_PWR 1
OBO0
OBO0 3
OBO1 + CE50 + CE51 CB121 CB122
OBO1 3 470uF/50v 470uF/50v 0.1uF 0.1uF
OBO2
OBO2 3
PWR_ GND
4 4
OBO3
OBO3 3
OBO4
OBO4 3
OBO5 VCC FOR AU 32" INVERTER CONNECTOR
OBO5 3
J12
OBO6
OBO6 3 In verter_PWR 1
OBO7 2
OBO7 3
3
8205UP3_0 4
8205UP3_0 3
R199 5
PWM0 10k

R. ANGLE
PWM0 3,14 6
7
8205UP1_2 8
8205UP1_2 3,9
9
PWR_ GND R200 10 VCC
PWR_GND 1
Dimming 11
12

2
100k 13
PWM0 R201 4.7k 1 Q5 CB123 PWR_ GND 14 R202
2N3904 0.1uF VCC R
SOT23/SMD 14x1 W/HOUSING

3
DIP14/WH/P2.0/R
R203 SELECT
10k

Back Light circuit R204

0
External PWM input
for dimming control
BL_ON/OFF

2
R205
8205UP3_0 1 Q6
2N3904
4.7k SOT23/SMD

3
3 3

J13

In verter_PWR 1
2
3
4

R. ANGLE
5
6
7
8
9
10

PWR_ GND
10x1 W/HOUSING R.A.
DIP10/WH/P2.0/R

L35 L36
FB FB
BEAD/SMD/1206
BEAD/SMD/1206

5VSB

R109 R320 R319R318R317 R316 R315 J19

J14

KEYPAD - MAX 8-KEYS

10K 10K 10K 10K 10K 10K 10K 1
9/05 DIP13/W/H/P2.0 TV/AV 2
13x1 W/HOUSING MENU 3
1 VOL- 4
2 2
OBO0 L37 FB TV/AV 2 VOL+ 5
OBO1 L38 FB MENU 3 C H- 6
5VSB OBO2 L39 FB VOL- 4 CH+ 7
OBO3 L40 FB VOL+ 5 8205UP1_2 8
OBO4 L41 FB C H- 6 9
OBO5 L42 FB CH+ 7
IR 8
R206 510 LED_RED 9 CON9
R207 R208 R209 510 LED_GRN 10
10K 10K 8205UP1_2 11
R0603/SMD R0603/SMD R210 0 POW 12
5VSB J20
13
2

OBO6 R211 4.7K 1 Q7 1

2N3906 IR 2
2

LED_RED 3
3

OBO7 1 Q8 LED_GRN 4
R212 4.7K 2N3906 POW 5
3

DV33A CONN RCPT 5

IR & POWER ON LED

1 1

Title

Size Doc Number Rev

C BACK_LIGHT/KEYPAD V1.2
Date: Wednesday, October 12, 2005 Sheet 11 of 15

A B C D E
 A B C D E

VCC
L43
DV I_R CE53 10uF/25v R213 100k HPV DD

+
VGA_IN_L
VGA_IN_L 6
VGA_IN_R DVI_L CE54 10uF/25v R214 100k FB

+
VGA_IN_R 6
YPBPR1_L C114
YPBPR1_L 7
Y PBPR1_R + CB124
YPBPR1_R 7 0.1uF
YPBPR2_L Y PBPR2_R CE55 10uF/25v R215 100k

+
YPBPR2_L 7
Y PBPR2_R 10uF/25v SCL1 R216 100 SCL14
YPBPR2_R 7
DVI_L YPBPR2_L CE56 10uF/25v R217 100k

+
DVI_L 7
DV I_R SDA1 R218 100 SDA14
DVI_R 7

50k

50k
DACBCLK DACBCLK 3 Y PBPR1_R CE57 10uF/25v R219 100k

+
DACMCLK DACMCLK 3 CODHPOUTR C125
4 HPVDD 4
DACLRC DACLRC 3 YPBPR1_L CE59 10uF/25v R222 100k C115 C116

+
DOUT DOUT 3 100pF 100pF
AOSDATA1 AOSDATA1 3 10uF/10v
AOSDATA3 AOSDATA3 3

R220

R221
AV_R CE60 10uF/25v R224 100k CODHPOUTL C126

+
AV_L CE61 10uF/25v R225 100k

+
+ CE62 10uF/10v
MUTE R14 10uF/25v CB125

48
47
46
45
44
43
42
41
40
39
38
37
MUTE 3 0.1uF
PWM0 U20 33
PWM0 3,11
+12V
+12V 1,7,10,13,14 Change

AIN3L

AIN4L

AIN5L

AINOPL
AINVGL
AIN2R

AIN3R

AIN4R

AIN5R

AINOPR
AINVGR
AGND
TV
TV 7,8
AV_L VGA_IN_R CE64 10uF/25v R226 100k

+
AV_L 7
AV_R J15
AV_R 7
AV1_IN VGA_IN_L CE65 10uF/25v R227 100k HPV DD

+
AV1_IN 7,8 1 AIN2L AVDD 36
AV2_IN 2 35 AD CREFP AD CREFP GND 1
AV2_IN 7,8 AIN1R ADCREFP
3 34 GND 2
ORO4 DACBCLK AIN1L ADCREFGND VMIDADC VMIDADC AUSPR
ORO4 3 4 DACBCLK VMIDADC 33 3
ORO7 DACMCLK 5 32 + CE67 GND 4
ORO7 3 DACMCLK AUXL 10uF/25v
OGO7 AOSDATA1 6 31 CB126 GND 5
OGO7 3 DIN AUXR 0.1uF
PWM1 DACLRC 7 30 H PVDD_ + CE69 AUSPL 6
PWM1 3 DACLRC DACREFP 10uF/25v
SCL1 8 29 CB127 GND 7
SCL1 10 ZFLAGR DACREFN 0.1uF
SDA1 9 28 VMIDDAC MUTE 8
SDA1 10 ZFLAGL VMIDDAC
DACBCLK 10 27 COD_VOUTR
DACMCLK ADCBCLK VOUTR COD_VOUTL R230
11 ADCMCLK VOUTL 26
DOUT 12 25 + CE70 10k CON8
DOUT NC 10uF/25v CB128

HPOUTR
ADCLRC

HPOUTL
DACLRC 0.1uF

HPGND
HPVDD
MODE
DGND
DVDD
5VSB

NC
CE

CL
DI
R229
1k WM8776

13
14
15
16
17
18
19
20
21
22
23
24
CE71
COD_VOUTR AUSPR

HPV DD

+
SDA14
DACL RC

SCL14
DV DD
3 10uF/25V R231 3

DV33 CODHPOUTR GND 10k

L45 DVDD CODHPOUTL

TO AUDIO BD
DV33 DV DD

FB MUST USE SHIELD CABLE

+ CE72 CE73
47uF/16v CB130 COD_VOUTL AUSPL

+
0.1uF
TWO WIRE SERIAL CONTROL DEVICE ADDRESS 0x34h
10uF/25v R232
10k

A/V Bypass
VCC
R233
0
R0805/SMD
FB15 FB DACVA
BEAD/SMD/0805

2
+ CE74 CB132
CB131
0.1uF VCC 2
100uF/16V 1uF + CE75
100uF/16V

OGO7 Repalce ADIN0 -----MTK

PWM1 Repalce ADIN1 -----MTK
R334 R10
10k
10K
AUDIO BYPASS. J16
R13
U22 0 V_BYPASS 1
AOSDATA3 R234 33 1 8 L_BYPASS OGO7 LINE_MUTE 2
DACBCLK R235 33 SDATA AOUTL DACVA PWM1
2 DEM#/SCLK VA 7 3
DACLRC R236 33 3 6 SPK SWICTH(PDP) BY MICO 4
DACMCLK R237 33 LRCK AGND R_BYPASS L_BYPASS
4 MCLK AOUTR 5 5
R_BYPASS 6
CS4334 2-CH AUDIO DAC
SOP8/SMD
VCC 5x1 W/HOUSING
PH6/2.0

R306 R307
10K 10K
U23
TV C118 1uF 1 8 CE76 220uF/16v R238 43,1% V_BYPASS
+

ORO4 IN1 OUT

2 A VCC 7 VCC
ORO7 3 6 AV2_IN
AV1_IN C119 1uF B IN3
4 IN2 GND 5
R239
BA7612F 75

R240 R241
75/NC 75/NC

1 1

Title

Size Doc Number Rev

C WM8776/WM8766/AUDIO CODEC V1.2
Date: Wednesday, October 12, 2005 Sheet 12 of 15

A B C D E
 A B C D E

+12V +12V 1,7,10,14

TXD TXD 1,3
RXD RXD 1,3

DVIVSYNC DVIVSYNC 3,9 VCC Trace width of 12V>30mil

DVI HSYNC DVIHSYNC 3,9 U24
DVIDE DVIDE 3,9 5V
Trace width of 5V >40mil J17
8 D1 S1 1
DVIODCK DVIODCK 3,9
7 D1 G1 2 1
8205UP1_3 8205UP1_3 3 12V 6 3 +12V 12V 2
D2 S2
4
5 D2 G2 4 3 4
G ND 4
DACMCLK DACMCLK 3,12 CE77 CE78 5
DACBCLK CB133 IRF7314
DACBCLK 3,12 + + 6
DACLRC DACLRC 3,12 0.1uF CB134 SOIC8/SMD 5V 7
220uF/16v 220uF/16v 0.1uF 8
READY# READY# 3
"GND Need Very Strong"
+12V
REQUEST# REQUEST# 3 DIP8/W/H/P2.54
LO = > DTV BOARD POWER ON
TXD_0:MT5351 Transmit
HI = > DTV BOARD POWER OFF RXD_0:MT5351 Receiver
OGO4 OGO4 3,9 TXD_2:MT5351& MT8205 Communication
DV33A RXD_2:MT5351& MT8205 Communication
OGO5
OGO5 3
OGO6
OGO6 3,7 5VSB
DV33A
DV33A R242 R243
22k 22k
VI[0..23] VI[0..23] 3,9
R338 R339 C135
OGO3 0/NC 0/NC 56pF
OGO3 3
OGO1 R244 74LVC244A
OGO1 3 U30
OGO2 10k
OGO2 3
OGO0 U28 20 19 OGO4
OGO0 3 VCC 2G
SW 10 1
SW 3 GND 1G
PCRXD TXD
PCRXD 1 1 14
PCTXD TXD_2 OGO3 3 17
PCTXD 1 2 13 2Y4 2A4
OGO1 5 15
3 12 R245 2Y3 2A3

2
WE# RXD_2 C120 C121 OGO2 7 13 J18
WE# 3 4 11 1uF 2Y2 2A2
PWR# RXD OGO5 1 Q9 1uF OGO0 9 11
PWR# 5 5 10 2N3904 2Y1 2A1 TXD_0 1
G ND 6 9 0 SOT23/SMD VI0 RXD_0
3
7 8 12 1Y4 1A4 8 2 3

3
VI1 14 6 RXD_2 3
VI2 1Y3 1A3 TXD_2
16 1Y2 1A2 4 4
74HCT04A/NC VI3 18 2 5
1Y1 1A1
Add by MTK 6
U31 74LVC244A 7
20 VCC 2G 19 8
10 GND 1G 1 9
10
VI4 3 17 11
VI5 2Y4 2A4
5 2Y3 2A3 15 12
VI6 7 13 13
VI7 2Y2 2A2
9 2Y1 2A1 11 14
15
VI8 12 8 16
1Y4 1A4
DV33A
VI9 14 6 17
VI10 1Y3 1A3
16 1Y2 1A2 4 18
VI11 18 2 19
1Y1 1A1
20
DV33A U32
74LVC244A
21
22
20 VCC 2G 19 23
10 GND 1G 1 24
DV33A 5VSB R246 25
10k R247 VI12 3 17 26
VI13 2Y4 2A4
10k 5 2Y3 2A3 15 27
VI14 7 13 28
R248 R249 READY# VI15 2Y2 2A2
9 2Y1 2A1 11 29

2
5VSB DV33A 10k 10k/NC
5VSB DV33A VI16 12 1Y4 1A4 8
30
31 2
VI17 14 6 32
R250 1Y3 1A3

2
SW VI18 16 4 33
Q10 READY0# VI19 1Y2 1A2
1 18 1Y1 1A1 2 34
2N3904 35
R251 L46 L47 SOT23/SMD 0/NC 36
U33

3
MTK Modify
0 FB/NC FB 74LVC244A 37
R252 R253 20 VCC 2G 19 38
10k/NC 10k JP3 10 GND 1G 1 39
U25 40
2 1 16 VI20 3 17 41
TXD_2 S VCC VI21 2Y4 2A4
1 3 2 I0A E# 15 5 2Y3 2A3 15 42
DV33A
PCTXD 3 14 PCTXD VI22 7 13 43
3x1 RXD I1A I0D VI23 2Y2 2A2
4 YA I1D 13 9 2Y1 2A1 11 44
DV33A
JP3/DIP/P2.54 RXD_2 5 12 RXD_0 45
PCRXD I0B YD PCRXD DVI HSYNC 8205UP1_3 46
6 I1B I0C 11 12 1Y4 1A4 8
TXD 7 10 DVIVSYNC 14 6 READY0# 47
YB I1C TXD_0 DVIDE 1Y3 1A3 REQUEST0#48
8 GND YC 9 16 1Y2 1A2 4
R254 DVIODCK 18 2 49
IDTQS3VH257 10k R255 1Y1 1A1
50
U29 DV33A TSSOP16/SMD 10k

WE# REQUEST# CON50

1 14
2 13 WHEN OGO4 HIGH , DVI OUPUT
3 12
4 11 SW Function R256 WHEN OGO4 LOW ,ATSC OUPUT
2

SW
5 10
PWR#
6 9 PC <---> MT5351 U0 Q11 1 REQUEST0#
2N3904
7 8 0 MT5351 U2 <---> MT8205 SOT23/SMD 0/NC
ADD 22/9
3

1
1 PC <---> MT8205 1
74LVC00A/NC
PC -----> MT5351 U0RX

Title

Size Doc Number R ev

Custom ATSC INTERFACE V1.2
Date: Wednesday, October 12, 2005 Sheet 13 of 15

A B C D E
 A B C D E

4 4
DV33A
5VSB
CN2 DV33A

+12V 1
+12V 1,7,10,13
ORO1 2 RELAY_ON R287 R257
ORO1 3,10
ORO3 3 5VSB 4.7k/NC 1k R354
ORO3 3,10
PWM0 4 G ND RELAY_ON 10K
PWM0 3,11
ADIN4 5 VS_ON
ADIN4 3

2
6 5VD R259 Q15
7 2N3904 1 2N3904

2
ADIN4 Q12 1k
TP3
1 R355 1k ORO1

3
DIP7/P2.0

3
DEL ACD Net--------MTK R288
10k/NC
3 3

R356 0/NC

Change--------MTK USE WHEN LG V6

DV33A
5VSB
R340
5VD PWM0 DV33A
4.7k
R294
4.7k/NC R260
R343 1k R357
10k VS_ON 10K
1k

2
R262 Q16
Q13 1 2N3904

2
2N3904
2 2
1 R358 1k ORO3

3
R289
10k/NC

R360 0/NC

VCC +12V
USE WHEN LG V6

+ CE80 + CE79
220uF/16v 220uF/16v
C220UF16V/D6H11 C220UF16V/D6H11
1 1

Title

Size Doc Number Rev

A PDP interface V1.2
Date: Wednesday, October 12, 2005 Sheet 14 of 15
A B C D E
 A B C D E

4 From V0.1 To V1.2 change item: 4

1,Add R109-10K;R107-4.7K;C135-56pF;0603-R88,R91,R104,R106-0欧姆.0805-R96,R99,R101-0欧姆
2,Reset IC 增加5V Supply;DVI AUDIO ADD CONNECTOR J8.
3,ADIN4 CHANGE TO PWM0

3 3

2 2

1 1

Title

Size Doc Number Rev

A History V1.2
Date: Wednesday, October 12, 2005 Sheet 15 of 15
A B C D E
 1 2 3 4 5 6 7 8

C1

2 1

TUNER1 IN
22pF NPO

2 5% 1

TUNER1 ADDRESS R1
82K +24V
TUNER IF R2
+24V

1
1 2

1
5%
R11 + 100K

1
C10

5%
C2 86 R10 10K C12 R5 C5

2
+
10K 100NF 100UF/25V 100K 4.7uF C7 C4
FQ1236 / : NTSC TV

5%

5%
C14 NPO X5R C6 1UF 100UF/25V

2
22UF/16V 4.7nF 100NF X7R

2
D U2A C8 U1 FILM D
X7R

1
TU1 3 1 2 1 8
+ PIN PGND C38
C3 R3 L5 10uH
AV , TUNER I/O
FQ1236-MK3 1 1 2 2 1 2 7 1 2 1 2 LOUT
5%
OUT NIN SW
TU_VCC

+
R12
1J1 J11 AUDPL 2 R47 21 R66 21 R67 11 22 1UF 10K 3 6
- AGND VPP 1000UF/25V
RC4558 X5R C9

1
TU_12V ROUT 1K8 4K7 4K7 4K7
2nd SIF OUT

1 1 C20
VS_TUNER

10UF 5% 5% 5% 5% 4 5 1 2
2 2 EN BS
AF /MPX

C54 C55 R6

1
LOUT R4 1n 1n R7
3 3 5% 1UF 10
GND1
GND2

GND3
GND4
VS_IF

1
CVBS

AGND
AF-R

ATA-120
AF-L
SDA

4 4 100K
SCL

X5R R8 R9 D1 C11
NC
NC

NC
NC

VIDEO OUT MUTEC 2 1

AS

5%
5%
5 5 C24 10 470NF

22
SDA 10K MBRS130LTR

1
6 6
SCL

5%

5%
7 7 10K C15
1R1 C16

21
SIF1_OUT
1
2
3
4
5
6
7
8
9

22pF

2
10
11

12
13
14
TH1
TH2

TH3
TH4

1R21 8
20 NC D2 C17

1
TU_CVBS 1 2 TV AF1_OUT CON7 100NF
9 R15 47K 6.2V 390PF
1 2 X7R

1
18 1R3 10 NPO
TV_GND 5%
56 11
TV

2
12
CON12

1
GNDS GNDS 1R41 20 D13 J3
TV_GND

12
C21
GNDS FB1 TU_12V
1
VCC 0 2 2 1
FB2 1N4001
3
TU_SCL
D12 22pF NPO
4

2
0 9V
5
TU_SDA 6 2 5% 1
2
GNDS 1N4001
SIF1_IN TU_CVBS
CON6 R14
82K +24V
GNDS R16
AF1_IN +24V
1 2

1
5%

5%
R36 R17 100K

1
R37 10K 100K C27 +

2
R70 10K 4.7uF C29 C25

5%
J6 5% C19 NPO X5R C28 100UF/25V
J5 1UF

5%
0R/NC

2
MUTE 1 VIDEO OUT 22UF/16V 4.7nF 100NF X7R

2
1 U2B C30 U3
2 LMUTE X7R

1
2
AUDPR 3 PMUTE 5 1 2 1 8 C39
3 + C31 R18 PIN PGND L6 10uH
AUDPL 4 AGND 5%
4
AUSPL 7 1 22 1 2 7 1 2 1 2 ROUT
5 OUT NIN SW
AUSPR

+
6 R39
4x1 W/HOUSING AUDPR 2 R33 21 R45 21 R46 1 1 26 1UF 10K 3 6
- AGND VPP 1000UF/25V
RC4558 X5R C32

1
CON6 C40 1K8 4K7 4K7 4K7 5%
10UF 5% 5% 5% 4 5 1 2
R19 EN BS R20

1
Audio Input 5% R21
C52 C53
TUNER1 SIF1 BPF SIF_12V 100K 1n 1n
AGND
MUTEC 2 1
ATA-120
1UF
X5R R22 R23 D3
C33
470NF
10

5%
5%

NTSC 4.5MHz PAL 6MHz C41 10 FILM

22
10K MBRS130LTR

1
C C34 C

5%

5%

2
10K
C35
1

21
22pF NS

2
VCC D4 C36 100NF
1R7 1R8
D11 SR240 L1
+24V 47K 6.2V 390PF
1 2 X7R

1
1.8K 1k
1 2 R38 NPO
2mH
J2
5%
+ + C57 EXTR

2
1C1 10nF J1 C23 1 A
1 1000UF/35V 1000UF/35V PGND
2
1 2 SIF1 2
2

3
3 EXTL
BL1 4

2
1C4 10nF 1R9 0 1C5 1NF(22P/27P) 1L2 3.3UH(47uH/22uH) 1C6 10nF 1Q3 1 2 4 PGND
5
SIF1_IN 1 2 1 2 1 2 1 2 1 2 2N3904 600 OHM K1
CON5
4x1 W/HOUSING
EXTL
1

LOUT
2

1C7 1L3 1C8 1L4

INTL
1R10 1R11
EXTR
820pF/560pF 1.5uH/1.2uH 820pF/560pF 1.5uH/1.2uH 220 0R
ROUT
INTR
1

J7 J8
2

12

+24V
1

INTL INTR 1
1 1
2

GND V GND V 2 Q9 G6A-234P

1R12 1C9 CE6
2 2
GND V GND V + 7805
82R NC
3
10uF/25v NS
CON3
9V TU_VCC D10
1

C58 C62 C63 C61

2

330U/16V 100U/16V 100n

100n 1N4148
Q8
GND V GND V GND V GND V R31
PMUTE 1 2 2N3904

2
3K3 5%
INT: 0

1
EXT: 1 C56
100NF
X7R R32 R68

1
0R NC/0R
5% 5%

2
R54 10K R55 10K

1
1 2 1 2
+24V
5% 5%
C22 C2 C13
100U/35V 100N
TU_VCC VCC U5A R24

2
1L5 FB 22U/16V 3 2 3K 1 MUTEC
1R5 100 +

1
1 2 5%
1 C26 R13
1

2
TU_SCL 1 2 2 1
SCL CE4 CE5 R48 1k8 R49 4K7 R50 4K7 R51 4K7 OUT 5% R25

2
B 1R6 C60 47K 5%
B
100 + CE3 CB3 + + CB4 CB5 AUSPL 2 1 1 2 1 2 1 2 1 2 2 10U/16V R65 10K C37
100uF/16V 0.1uF 0.1uF 0.1uF - 47K
2

TU_SDA 1 2 1UF
SDA 10UF 5% 5% 5% 5% +24V
5%

100uF/16V 100uF/16V RC4558

X5R X5R
2

1
5%
R53 C45 C46 Q1 Q3
2

100K 1n 1n 1 C49 2 AGND D6 2N3906 R40 Q2

1
R52 47K 22P 2 10K 1 2N3904 2 R29 1 MUTE
2

2
2

1
GNDS 1 2 AGND LOUT 1K
1

GNDS 5%
1N4148 5%
1C2 1C3 ROUT + R41
2N3904
47pF R62 R63 C42 5%
47pF 10K
1 10K 2 1 10K 2 100UF/25V
1

+24V 5%

2
5% 5%
R42
AGND 1k
TU_12V SIF_12V C44 U5B AGND AGND AGND
1L6 FB 22U/16V 5
+
TU_12V 1 2 SIF_12V C43
R26
1

7 2 1
R56 R57 R58 R59 OUT 5%

2
C59 47K D8 LOUT
+ CE8 CB6 + CE9 CB7 AUSPR 2 1 1 1k8 2 1 4K7 2 1 4K7 2 1 4K7 2 6 10U/16V R61
100uF/16V 0.1uF 220uF/16V 0.1uF - 47K
2

10UF 5% 5% 5% 5%
RC4558 1N4148 D7 Q5
X5R
2

5%
R60 C47 C48 4.7V 2 R34 1 2N3904
2

100K 1n 1n 5%
1K

1
5%
1 C50 2 AGND
2

R64 22P R43

GNDS GND V AGND
1

1 47K 2 4K7
Q4 AGND
5%
D5 1015

1
MUTEB

NC +
C18
ROUT
NC

AF1_IN CE7
1 2
AF1
+

R44

2
M1 M2 M3 M4
33uF/16V R28 Q6
1k R35
9 2 9 2 9 2 9 2 1 2 AGND 1 2 2N3904
9 2 9 2 9 2 9 2 5%
8 3 8 3 8 3 8 3 5% 1K
8 3 8 3 8 3 8 3 0 R30

1
7 4 7 4 7 4 7 4
7 4 7 4 7 4 7 4
6 5 6 5 6 5 6 5 10k
6 5 6 5 6 5 6 5 +
NC

NC

NC

NC
D9
C51
GND V GNDS AGND
AF1 1R14
1 02 AF1_OUT GND HOLE GND HOLE GND HOLE GND HOLE 220UF/25V
AF1_OUT
AUDIO GROUND VIDEO GROUND 1N4148
1

2
SIF1 1R15
1 02 SIF1_OUT TU_12V
SIF1_OUT TU_12V
AGND
SIF1_IN 1R16
1 0/NC
2 SIF1_OUT Q7
TU_VCC GNDS GNDS 1015
TU_VCC
LMUTE
A A

R27
1K

AGND

Title

Size Number Revision

D
Date: 21-Sep-2005 Sheet of
File: D:\正在进行的项目\LCD TV\LCD TV.DdbDrawn By:

1 2 3 4 5 6 7 8
 A B C D E

MT5351RA-V2

MT5111 / MT5351 REFERENCE DESIGN - 4 LAYERS J1

BEAD/SMD/1206
L1 FB
+12V

1 + CE1 CB142
220uF/16v 0.1uF
Rev History P# DATE 2
C220UF16V/D6H11 C0603/SMD
3
4
RA-V1 INITIAL VERSION 2005/06/15 5 L19 FB
4 6 +5V 4
7 L2 FB +12V
2 +12V
RA-V2 ADDED AUDIO SWITCH / REFINE POWER CIRCUIT 2005/07/14 8 BEAD/SMD/1206
2,6 +5V
+5V
DV33
+ CE2
8x1 W/HOUSING 220uF/16v 2,5,6,8 DV33
DIP8/W/H/P2.54 C220UF16V/D6H11 GND
2,3,4,5,6,7,8 GND
+3.3V
ORESET#
4,5,8 ORESET#
POWER INPUT FROM MAIN BOARD
REQUEST#
5 REQUEST# R EADY#
5 READY#

DV33 GLOBAL SIGNAL

01. INDEX AND INTERFACE NS : NON-STUFF R1
02. POWER 4.7K
R0603/SMD

03. TUNER AUD_CTRL 1 S

U1
YA 4 5 ASPDIF
ASPDIF

04. MT5111 ASIC

15 OE YB 7
YC 9
AO1SDATA0 2 12
05. MT5351 ASIC AO1LRCK IA0 YD U0RX
5 IB0 5,8 U0RX
AO1BCK 11 DV33 U0TX
IC0 5,8 U0TX
06. MT5351 PERIPHERAL
AO1MCLK 14 16 U2TX
ID0 VCC 5,8 U2TX U2RX
CB1 5,8 U2RX
3
3
07. DDR MEMORY 6
10
IA1
IB1
0.1uF
C0603/SMD
UART (RS232)
3

IC1
08. NOR FLASH / JTAG / UART 13 ID1 GND 8

NC/IDTQS3VH257 VOR[0..7]
TSSOP16/P0.65/SMD HA1 5 VOR[0..7] VOG[0..7]
5 VOG[0..7] VOB[0..7]
U0TX 5 VOB[0..7]
7 RN1 8 1 5 VOPCLK
VOPCLK
U0RX 5 6 2 VO HSYNC
U2RX 5,8 VOHSYNC VOVSYNC
3 4 3 5,8 VOVSYNC
U2TX 1 2 4 VODE
33x4 RN0603/SMD 5 VODE
5
AO1MCLK
AO1BCK
R2
R3
75
75
6 DIGITAL VIDEO OUTPUT
7
AO1LRCK R49 75 8
AO1SDATA0 R50 75 9
10 AO1MCLK
5 AO1MCLK
NAME TYPE DEVICE VOB0
VOB1
7 RN3
5
8
6
11
12
5 AO1LRCK
AO1LRCK
AO1BCK
VOB2 5 AO1BCK AO1SDATA0
3 4 13 5 AO1SDATA0
+12V POWER +12V POWER SUPPLY VOB3 1
33x4
2
RN0603/SMD
14
15 ASPDIF
5 ASPDIF
+5V POWER +5V POWER SUPPLY VOB4 7 RN4 8 16
VOB5
VOB6
5 6 17 DIGITAL AUDIO INTERFACE
3 4 18
VOB7 1 2 19
+5V_tuner POWER +5V TUNER POWER 33x4 RN0603/SMD 20
VOG0 7 RN5 8 21
DV33_DM POWER +3V3 MT5111 POWER VOG1 5 6 22 5 AUD_CTRL
AUD_CTRL
VOG2
DV18 POWER +1V8 MT5111 POWER 3 4 23

BOTTOM
VOG3 1 2 24
2
DV33 POWER +3V3 MT5351 POWER VOG4
33x4
7 RN6
RN0603/SMD
8
25
26
2

AV33 POWER +3V3 MT5351 ANALOG POWER VOG5

VOG6
5
3
6
4
27
28
DV25 POWER +2V5 MT5351 DDR POWER VOG7 1
33x4
2
RN0603/SMD
29
30
DV12 POWER +1V2 MT5351 POWER VOR0 7 RN7 8 31
VOR1 5 6 32
VOR2 3 4 33
VOR3 1 2 34
33x4 RN0603/SMD 35
VOR4 7 RN8 8 36
GND GROUND GROUND VOR5
VOR6
5
3
6
4
37
38
VOR7 1 2 39
33x4 RN0603/SMD 40
VO HSYNC 7 RN9 8 41
VOVSYNC 5 6 42
4
8

VODE 3 4 43
R4 6 VOPCLK 1 2 44
K1
8

ASPDIF 6 33x4 RN0603/SMD

3 IN 45
33 2 ORESET# 7 RN10 8 46
R0603/SMD VCC R EADY#
1 G 5 6 47
7 REQUEST# 3 4 48
K2

G
9

1 2 49
P1 33x4 RN0603/SMD 50
5
9

S/PDIF OUT
+5V RCA/SPDIF/5P/DIP
FB1 HEADER 50 SMD0.5 BOTTOM
H50S/P0.5
FB
1 BEAD/SMD/0603 CB2 1
0.1uF
C0603/SMD DIGITAL OUTPUT

SPDIF CIRCUIT
Title POWER

Size Document Number Rev

Date: Sheet of
A B C D E
 A B C D E

FB L17 BEAD/SMD/0805/NC

+5V U2 DV33

9V L3

ADJ/GND
3 IN OUT 2

+12V FB
U3 L4 +5V_TUNER + CE3 CB3 R5 BEAD/SMD/0805 + CE4 CB4
3 2 220uF/16v 0.1uF AZ1117/adj 110 220uF/16v 0.1uF +12V
IN OUT 1 +12V

1
FB C220UF16V/D6H11 C0603/SMD SOT223/SMD R0603/SMD C220UF16V/D6H11 C0603/SMD +5V
BEAD/SMD/0805 1,6 +5V DV33
VOUT 4 1,5,6,8 DV33

ADJ
4 + CE5 CB5 + CE6 CB6 4
220uF/16v 0.1uF 220uF/16v 0.1uF +5V_TUNER
C220UF16V/D6H11 C0603/SMD C220UF16V/D6H11 C0603/SMD 3,4 +5V_TUNER DV33_DM
4 DV33_DM

1
AP1084/TO220-DIP/5V R6 DV18
TO220/DIP 4 DV18
180
R0603/SMD
1.25 x (1+180/110) = 3.3V AV33
5,6 AV33 DV25
5,6,7 DV25
POWER SUPPLY +5V FOR TUNER POWER SUPPLY +3V3 FOR MT5351 5,6 DV12
DV12

GND
1,3,4,5,6,7,8 GND
L18
U4 BEAD/SMD/0805/nc
+5V DV33_DM DV33 AV33
FB L5 L6
ADJ/GND

3 IN OUT 2

FB FB
+ CE7 CB7 R7 BEAD/SMD/0805 + CE8 CB8 + CE9 CB9 BEAD/SMD/0805 + CE10 CB10 GLOBAL SIGNAL
220uF/16v 0.1uF AZ1117/adj 110 220uF/16v 0.1uF 220uF/16v 0.1uF 220uF/16v 0.1uF
1

C220UF16V/D6H11 C0603/SMD SOT223/SMD R0603/SMD C220UF16V/D6H11 C0603/SMD C220UF16V/D6H11 C0603/SMD C220UF16V/D6H11 C0603/SMD

R8
180
R0603/SMD
1.25 x (1+180/110) = 3.3V

POWER SUPPLY +3V3 FOR MT5111 POWER SUPPLY +3V3 FOR MT5351 (ANALOG)

DV33_DM
3 U5 DV18 +5V U6 DV25 3
L7 L8
ADJ/GND

ADJ/GND
3 IN OUT 2 3 IN OUT 2

FB FB
R9 BEAD/SMD/0805 + CE12 CB12 + CE13 CB13 R10 BEAD/SMD/0805 + CE14 CB14
AZ1117/adj 270 220uF/16v 0.1uF 220uF/16v 0.1uF AZ1117/adj 100 220uF/16v 0.1uF
1

1
SOT223/SMD R0603/SMD C220UF16V/D6H11 C0603/SMD C220UF16V/D6H11 C0603/SMD SOT223/SMD R0603/SMD C220UF16V/D6H11 C0603/SMD

R11 R12
120
R0603/SMD
1.25 x (1+120/270) = 1.8V 100
R0603/SMD
1.25 x (1+100/100) = 2.5V

POWER SUPPLY +1V8 FOR MT5111 POWER SUPPLY +2V5 FOR MT5351 AND DDR

+5V +5V_TUNER DV33 U7 DV12

L32 L9

ADJ/GND
3 IN OUT 2

FB FB
+ CE30 CB146 BEAD/SMD/1206/NC
+ CE31 CB147 + CE15 CB15 R13 BEAD/SMD/0805 + CE16 CB16
470uF/16v/NC 0.1uF/NC 470uF/16v/NC 0.1uF/NC 220uF/16v 0.1uF AZ1117/adj 100 220uF/16v 0.1uF

1
C220UF16V/D6H11 C0603/SMD C220UF16V/D6H11 C0603/SMD C220UF16V/D6H11 C0603/SMD SOT223/SMD R0603/SMD C220UF16V/D6H11 C0603/SMD

R14
2 2
0
R0603/SMD
1.25 x (1+0/100) = 1.25V

ADD POWER SUPPLY +1V2 FOR MT5351

L33 4.7UH
DV25

MP2105 FB R112
+5V U21 499k
4 3 R0603/SMD
IN SW
1 EN FB 5
GND

CB150
CB151 10uF
10uF C0805/SMD
2

C0805/SMD R113
249k
R0603/SMD

Compatible With U6
1 1

Title
POWER
Size Document Number Rev
Custom MT5351RA-V2 1

Date: Monday, September 26, 2005 Sheet 2 of 8

A B C D E

TwinSon Chan
 A B C D E

U8

+5V_TUNER
L10

TH1 FB
GND CB17 + CE17 BEAD/SMD/0805 +5V_TUNER
4 GND TH2 4
0.1uF 10uF/16v
1 C0603/SMD C10UF16V/D5H11
Outdoor PS
VS_splitter_+5V 2
OOB_OP 3
4 R15 R16
NC 10K 10K
RF_AGC 5
6 R0603/SMD R0603/SMD
NC R17 NS R0603/SMD
AS 7
8 R18 100 R0603/SMD TUNER_SCLO
SCL R19 100 R0603/SMD TUNER_SDAO
SDA 9
NC 10
11 L11 +5V_TUNER
VS_Tuner_+5V
Broad_IF_OP 12
13 FB
IF_AGC CB18 + CE18 BEAD/SMD/0805
Narrow_IF_OP1 14
15 0.1uF 10uF/16v
Narrow_IF_OP2 C0603/SMD C10UF16V/D5H11
GND TH3
GND TH4
R20 IF_AGC
4.7K
PORT TUNER TD1336/FGHP C3 R0603/SMD
10nF
3 C0603/SMD 3

+5V_TUNER
2,4 +5V_TUNER

+5V_TUNER G ND
1,2,4,5,6,7,8 GND

R22
C4
1nF
C5
0.1uF
GLOBAL SIGNAL
510/1% C0603/SMD C0603/SMD
R0603/SMD

2nd_IF- RF_AGC
4 RF_AGC IF_AGC
R21 4 IF_AGC
510/1% 2nd_IF+
R0603/SMD 4 2nd_IF+ 2nd_IF-
U9 C6 U10 4 2nd_IF-
1 5 1uF 1 8 2nd_IF+ TUNER_SCLO
IN+ OUT+ C0603/SMD VCC_+5V GND 4 TUNER_SCLO
2 IN- OUT- 4 2 IN_1 OUT_1 7 TUNER_SDAO
L12 3 6 4 TUNER_SDAO
NS IN_2 OUT_2
3 GND 4 VAGC GND 5
L/IND/SMD/0805
PORT SAW FILTER X6965D SIP5K C7 upc3218
SIP5K/DIP 1uF TSSOP8/SMD
2 C0603/SMD 2

C8
TUNER INTERFACE
10nF
IF SAW FILTER AND AMPLIFIER C0603/SMD
RF_AGC

ROUTE SYMMETRICALLY
R23
4.7K
R0603/SMD

1 1

Title
TUNER
Size Document Number R ev
Custom MT5351RA-V2 1

Date: Monday, September 26, 2005 Sheet 3 of 8

A B C D E

TwinSon Chan
 A B C D E

+5V_TUNER
2,3 +5V_TUNER DV33_DM
2 DV33_DM DV18
2 DV18
GND
1,2,3,5,6,7,8 GND

ORESET#
DVDD33 1,5,8 ORESET#

GLOBAL SIGNAL

R25 4.7K R0603/SMD/NC

R27 4.7K R0603/SMD
MT5111_RF_AGC R24 R F_AGC R F_AGC

DVDD18

DVDD33

DVDD18

DVDD33

DVDD18

DVDD33
MT5111_RF_AGC
3 RF_AGC

MT5111_IF_AGC
1K C9 IF_AGC
4 R0603/SMD 47nF 3 IF_AGC 4

TUNER_SDA
TUNER_SCL
C0603/SMD 2nd_IF+
3 2nd_IF+ 2nd_IF-
3 2nd_IF-
MT5111_IF_AGC R26 IF_AGC TUNER_SCLO
1K C10 3 TUNER_SCLO TUNER_SDAO
R0603/SMD 47nF 3 TUNER_SDAO
C0603/SMD
TUNER INTERFACE
U11
Close to MT5111

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MT5111AE

TUNER_CLK
TUNER_DATA

ANTIF
DVDD18
DGND

SA1
SA0

DVDD33
RF_AGC
IF_AGC
DGND
DVDD33

DGND
DVDD18
DGND

DGND
DVDD33

DVDD18
NC
NC
NC
DGND

NC
NC

DGND
TS1DATA[0..7]
5 TS1DATA[0..7] TS1SYNC
5 TS1SYNC TS1VALID
2nd_IF- C11 ADVDD33_1 5 TS1VALID TS1ERROR
76 ADVDD33 NC 50 5 TS1ERROR
1uF 77 49 TS1CLK
C0603/SMD NC NC ORESET# 5 TS1CLK
78 NC RESET_ 48
L13 C12 79 47 OSCL_MST TS INPUT
NS/220nH NS/47pF AVDD33 AVSS HOST_CLK
80 AVDD DGND 46
L/IND/SMD/0805 C0603/SMD 81 45 DV DD18
2nd_IF+ C13 IN- DVDD18 OSDA_MST
82 IN+ HOST_DATA 44
1uF AVDD33 83 43 OSDA_MST
C0603/SMD C14 0.1uF AVDD DGND33 DV DD33 6 OSDA_MST OSCL_MST
84 NC DVDD33 42 6 OSCL_MST

MT5111AE
C0603/SMD 85 41
C15 0.1uF REFBOT AVSS DGND DV DD18

100-LQFP
86 REFBOT DVDD18 40
C0603/SMD C16 VCMEXT 87 39 1 RN11 2 TS1ERROR
10uF/10v VCMEXT TS_ERR TS1VALID
88 REFTOP TS_VAL 38 3 4
C17 0.1uF C0805/SMD REFTOP 89 37 5 6 TS1CLK
C0603/SMD AVSS TS_CLK TS1SYNC
90 AVDD18 DGND 36 7 8
AVDD33 91 35 DV DD33 33x4
DVDD18 FB2 AVDD3 AVDD DVDD33 RN0603/SMD
92 AVDD TS_SYNC 34
AVDD33 93 33
FB C18 AVDD TS_DATA0 TS1DATA0
94 AVSS TS_DATA1 32 1 RN12 2
BEAD/SMD/0603 0.1uF 95 31 3 4 TS1DATA1
C0603/SMD XTAL2 AVSS DGND DV DD18 TS1DATA2
96 XTAL2 DVDD18 30 5 6
XTAL1 97 29 7 8 TS1DATA3
XTAL1 TS_DATA2 33x4
3 98 AVSS TS_DATA3 28 3
C19 AVDD33 99 27 RN0603/SMD
Y1 18pF AVDD DGND DV DD33
100 AVSS DVDD33 26
C0603/SMD

TS_DATA7
TS_DATA6
TS_DATA5
TS_DATA4
25MHz R28

ADVDD33

DVDD33
DVDD18
CRYS/DIP/SMD 1M C20

DGND

DGND
R0603/SMD 18pF
AVDD

AVDD

AVDD
AVSS

AVSS
C0603/SMD
NC
NC

NC
NC
NC

NC
NC

NC
NC

NC
NC
MODIFIED IN V3

AVDD5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DV33_DM

CB148
U12A 0.1uF U12B

10
4
C0603/SMD

ADVDD33_2

2
4
6
8
TS1SYNC 2 14 12 14

PR

PR
D VCC D VCC

DVDD33
DVDD18
5 9
AVDD33

AVDD33

RN13 TS1CLK Q TS1CLK# Q

3 CLK Q 6 11 CLK Q 8
33x4
RN0603/SMD 7 7

CL

CL
GND GND TS1DATA7_T R111 TS1DATA7

1
3
5
7
NS/0

13
74HC74 74HC74 R0603/SMD

TS1DATA7_T
SOP14/SMD SOP14/SMD

TS1DATA6
TS1DATA5
TS1DATA4

DV33_DM

CB149
0.1uF
C0603/SMD

14

14

14

14
U20A U20B U20C U20D
2
1 4 9 12 2
3 TS1CLK# 6 8 11 TS1DATA7
TS1CLK 2 TS1DATA7_T 5 TS1ERROR 10 13

74HC00 74HC00 74HC00 74HC00

7
SOP14/SMD SOP14/SMD SOP14/SMD SOP14/SMD

DV18 DVDD18 DVDD18

AVDD33 AVDD3
L14 FB3 +5V_TUNER DV33_DM
FB CB19 CB23 CB24 CB25 CB20 CB21
BEAD/SMD/0805 + CE19 CB22 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF FB CB26
10uF/16v 0.1uF C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD BEAD/SMD/0603 0.1uF
C10UF16V/D5H11 C0603/SMD C0603/SMD
Digital 1.8V Bypass Caps R29 R30 R31 R32
10K 10K 4.7K 4.7K
AVDD33 AVDD5 R0603/SMD R0603/SMD R0603/SMD R0603/SMD
FB4
DV33_DM DVDD33 DVDD33 TUNER_SDA1 3 QF1 1 TUNER_SDA
FB CB27
L15 BEAD/SMD/0603 0.1uF 2N7002
FB CB29 CB30 CB31 CB32 CB33 CB83 C0603/SMD N-MOSFET
2

BEAD/SMD/0805 + CE20 CB28 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

10uF/16v 0.1uF C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD
C10UF16V/D5H11 C0603/SMD AVDD33 ADVDD33_1 TUNER_SCL1 3 QF2 1 TUNER_SCL
Digital 3.3V Bypass Caps FB5
2N7002
1 FB CB34 N-MOSFET 1
2

0.1uF
DV33_DM AVDD33 AVDD33
BEAD/SMD/0603
C0603/SMD SIF LEVEL SHIFTER
L16
FB CB35 CB36 CB37 CB38 CB39 AVDD33 ADVDD33_2
BEAD/SMD/0805 + CE21 CB40 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF FB6
10uF/16v 0.1uF C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD TUNER_SDA1 R33 TUNER_SDAO
C10UF16V/D5H11 C0603/SMD FB CB41 10
Analog 3.3V Bypass Caps BEAD/SMD/0603 0.1uF R0603/SMD
C0603/SMD
TUNER_SCL1 R34 TUNER_SCLO
10 Title
R0603/SMD MT5111 ASIC
Size Document Number Rev
C MT5351RA-V2 TwinSon Chan 1

Date: Monday, September 26, 2005 Sheet 4 of 8

A B C D E
 5 4 3 2 1

TP1
IOR _Y6
TP/SMD/D1.0
TP2 R
IOB_Y5 8 R B
TP/SMD/D1.0 8 B G
TP3 8 G
IOG_Y4
TP/SMD/D1.0
DV33

AVDD_DMPLL1
AVDD_DMPLL0
1,2,6,8 DV33 DV25

AVDD_APLL0
AVDD_APLL1
AVDD_VPLL
2,6,7 DV25

AVDDBGKP

TS1ERROR
DV12

CAPVGND
APLLCAP0
APLLCAP1

AVDDRKP

AV DDYKP

TS1DATA7
TS1DATA6
TS1DATA5
TS1DATA4
TS1DATA3
TS1DATA2
TS1DATA1
TS1DATA0

T S1SYNC
TS1VALID
2,6 DV12

CAPVPLL

DV DDKP
OXTALO

OPWM0

TS1CLK
OXTALI

PDA22
PDA21
PDA20
PDA19
PDA18
PDA17
PDA16
PDA15
PDA14
PDA13
PDA12
PDA11
PDA10
G ND

PD D7
PD D6
PD D5
PD D4
PD D3
PD D2
PD D1
PD D0
PDA9
PDA8
PDA7
PDA6
PDA5
PDA4
PDA3
PDA2
PDA1
PDA0
1,2,3,4,6,7,8 G ND

ATP2
ATP1

FS
DV12

G
R
B
ORESET#
1,4,8 ORESET# REQUEST#
1 REQUEST# REA DY#
D D
1 READY#

AE14
AE15
M11
M12
M13

M24
N11
N12
N13

D10
C10

D11
C11

D12
C12

D13
C13

D14
C14

C15
D15

C16
D16

C17
D17

C18
D18

C19
D19

C20
D20

C21
D21

C22
D22

C23
D23

C24
D24

C25

N24
U24
B10
A10

B11
A11

B12
A12

B13
A13

B14
A14
A15
B15

A16
B16

A17
B17

A18
B18

A19
B19

A20
B20

A21
B21

A22
B22

A23
B23

A24
B24

A25
B25

A26
B26
A27
A28

E10
E19
L11
L12
L13
OSDA0

M5
D4

D5
D1
D2
C2

D3
C1

C3

C4

C5

C6
D6

D7

C7

C8
D8

D9
C9

N5
U5
E4

E5

B1
A1

A2
B2

B3
A3

B4
A4

B5
B6
A5
A6
B7
A7

A8
B8

B9
A9
U14 6 OSDA0 OSCL0
6 OSCL0

APLLCAP0
APLLCAP1

CAPVPLL
ATP2
ATP1
AVDD_APLL0
AVDD_APLL1

OXTALO
AVDD_VPLL
AVDD_DMPLL1
AVDD_DMPLL0

AVDDRKP
IOR_Y6
IOB_Y5
IOG_Y4
IOX_Y3
IOY_Y2
IOC_Y1
AVDDYKP
AVDDBGKP

FS

CIN_Y0
DVDDKP

ORTCO
ORTCVSS

OPWM1
OPWM0

T1DATA7
T1DATA6
T1DATA5
T1DATA4
T1DATA3
T1DATA2
T1DATA1
T1DATA0

T1CLK
T0DATA7
T0DATA6
T0DATA5
T0DATA4
T0DATA3
T0DATA2
T0DATA1
T0DATA0

T0CLK

PDCD2#
PDIOIS16#
PDREG#
PDINPACK#
PDWAIT#

PDIREQ#
PDWE#
PDIOWR#
PDIORD#
PDOE#
PDCE2#
PDCE1#
PDA25
PDA24
PDA23
PDA22
PDA21
PDA20
PDA19
PDA18
PDA17
PDA16
PDA15
PDA14
PDA13
PDA12
PDA11
PDA10
PDA9
PDA8
PDA7
PDA6
PDA5
PDA4
PDA3
PDA2
PDA1
PDA0
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
PDCD1#
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND

CAPVGND

OXTALI

NC

DACVREF

NC

ORTCVDD
ORTCI

T1VALID
T1SYNC

T0VALID
T0SYNC

PDENPOD

PDRESET

CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
OPWM0
DV33 6 OPWM0
OXTALI
6 OXTALI OXTALO
POWE# 6 OXTALO
P5 IOVDD POWE# B27
R1 B28 POCE0# VCXO0
IOVDD POCE0# POOE0# 6 VCXO0
R2 IOVDD POOE0# C26
R3 IOVDD POCE1# C27 GLOBAL SIGNAL
R4 IOVDD POOE1# C28
R5 D25 VCXO0 TP4
IOVDD POCE2# VCXO1 VCXO1
T5 IOVDD POOE2# D26
E11 TP/SMD/D1.0 TS1DATA[0..7]
IOVDD 4 TS1DATA[0..7]
E12 IOVDD PARB# D27 TEST PURPOSE 4 TS1SYNC
TS1SYNC
TS1VALID
E13 IOVDD PARE# D28 4 TS1VALID
E14 E25 TS1ERROR
IOVDD PACE# 4 TS1ERROR TS1CLK
E15 IOVDD PACLE E26 4 TS1CLK
E16 IOVDD PAALE E27
E17 IOVDD PAWE# E28 TS INPUT
E18 IOVDD
P24 IOVDD ELREQ F25
R24 IOVDD ECLK F26
R25 F27 RDQ[0..31]
IOVDD ECNTL0 7 RDQ[0..31] RDQS[0..3]
R26 IOVDD ECNTL1 F28 7 RDQS[0..3]
R27 G25 RDQM[0..3]
IOVDD EDATA0 7 RDQM[0..3] RA[0..13]
R28 IOVDD EDATA1 G26 7 RA[0..13]
T24 G27 RBA[0..1]
IOVDD EDATA2 DV33 7 RBA[0..1] RCLK0
EDATA3 G28 7 RCLK0
OSDA0 E1 H25 RCLK0#
OSCL0 OSDA0 EDATA4 7 RCLK0# RCS#
F4 OSCL0 EDATA5 H26 7 RCS#
E3 H27 RRAS#
OSDA1 EDATA6 R35 7 RRAS# RCAS#
E2 OSCL1 EDATA7 H28 7 RCAS#
J25 4.7K RWE#
U0TX ELPS R0603/SMD 7 RWE# RCKE
F3 U0TX ELINKON J26 7 RCKE
U0RX F2 RCLK1
U1TX U0RX ORESET# 7 RCLK1 RCLK1#
F1 U1TX ORESET# J27 7 RCLK1#
U1RX G4 J28 OI RI TP5 RVREF
U2TX U1RX OIRI IR 6 RVREF
G3 U2TX OIRO K25
U2RX
U2CTS
G2 U2RX
TP/SMD/D1.0 + CE22
47uF/16v
DDR MEMORY
G1 U2CTS ICS1# K26
TP6 TUNER_SW H4 K27 C10UF16V/D5H11
C
TUNER_SW U2RTS ICS0# C
IDA2 K28
TP/SMD/D1.0 H3 L25 POCE0#
AO1SDATA3 IDA0 8 POCE0# POOE0#
H2 AO1SDATA2 IDA1 L26 8 POOE0#
H1 L27 POWE#
AO1SDATA0 AO1SDATA1 IINTRQ 8 POWE#
J4 AO1SDATA0 IDMACK# L28
AO1LRCK J3 M25 PDA[0..22]
AO1BCK AO1LRCK IIORDY 8 PDA[0..22] PD D[0..7]
J2 AO1BCK IDIOR# M26 8 PDD[0..7]
AO1MCLK J1 M27
AO1MCLK IDIOW#
K1 AO2SDATA0 IDMARQ M28 FLASH INTERFACE
K2 AO2LRCK IDD15 N25
K3 AO2BCK IDD0 N26
K4 AO2MCLK IDD14 N27
ASPDIF L3 N28 AO1MCLK
AUD_CTRL ASPDIF IDD1 1 AO1MCLK AO1LRCK
L4 ASPDIF2 IDD13 P25 1 AO1LRCK
P26 AO1BCK
VOB0 IDD2 1 AO1BCK AO1SDATA0

MT5351
L2 VOB0 IDD12 P27 1 AO1SDATA0
VOB1 L1 P28
VOB2 VOB1 IDD3 ASPDIF
M4 VOB2 IDD11 T28 1 ASPDIF
VOB3 M3 T27
VOB3 IDD4
VOB4
VOB5
M2 VOB4 IDD10 T26 AUDIO INTERFACE
M1 VOB5 IDD5 T25
VOB6 N4 U28
VOB7 VOB6 IDD9
N3 VOB7 IDD6 U27
VOG0 N2 U26 JTRST#
VOG1 VOG0 IDD8 8 JTRST# JTDI
N1 VOG1 IDD7 U25 8 JTDI
VOG2 P4 V28 JTMS
VOG3 VOG2 IRESET# 8 JTMS JTCK
P3 VOG3 8 JTCK
VOG4 P2 V27 JRTCK
VOG5 VOG4 DDETECT 8 JRTCK JTDO
P1 VOG5 DCLK V26 8 JTDO
VOG6 T1 V25
VOG6 DCMD
VOG7
VOR0
T2 VOG7 DDATA0 W28 JTAG PORT
T3 VOR0 DDATA1 W27
VOR1 T4 W26
VOR2 VOR1 DDATA2
U1 VOR2 DDATA3 W25
VOR3 U2 U0RX
VOR4 VOR3 1,8 U0RX U0TX
U3 VOR4 MDETECT Y28 1,8 U0TX
VOR5 U4 Y27 U1RX
VOR6 VOR5 MCLK 8 U1RX U1TX OI RI
V1 VOR6 MBS Y26 8 U1TX 6 OIRI
VOR7 V2 Y25 U2TX
VOPCLK VOR7 MDATA0 1,8 U2TX U2RX U2CTS
V3 VOPCLK MDATA1 AA28 1,8 U2RX 6 U2CTS
VOH SYNC V4 AA27
VOHSYNC MDATA2
V OVSYNC
VODE
W1 VOVSYNC MDATA3 AA26 UART (RS232)
W2 VODE
AA25 DONE
JTRST# STSCLK REQUEST# VOR[0..7]
B W3 JTRST# STSDOUT AB28 1 VOR[0..7]
B
JTDI W4 AB27 REA DY# FS VOG[0..7]
JTMS JTDI STSDIN 6 FS 1 VOG[0..7] VOB[0..7]
Y1 JTMS SPWRSEL AB26 1 VOB[0..7]
JTCK Y2 AB25 DVDDKP VOPCLK
JRTCK JTCK SDETECT 6 DVDDKP 1 VOPCLK VOH SYNC
Y3 JRTCK SCMDVCC AC28 1,8 VOHSYNC
JTDO Y4 AC27 R36 AVDDBGKP V OVSYNC
JTDO SRST 330 2,6 AVDDBGKP A VDDYKP 1,8 VO VSYNC VODE
SCLK AC26 2,6 AVDDYKP 1 VODE
L14 AC25 R0603/SMD AVDDRKP
GND SDATA 2,6 AVDDRKP
L15 GND AVDD_DMPLL0
DIGITAL VIDEO OUTPUT
L16 GND GND T11 2,6 AVDD_DMPLL0
L17 T12 LED1 AVDD_DMPLL1
GND GND LED DIP2.54 2,6 AVDD_DMPLL1 AVDD_VPLL
L18 GND GND T13 2,6 AVDD_VPLL
M14 T14 LED/DIP/P2.54 AVDD_APLL1
GND GND 2,6 AVDD_APLL1 AVDD_APLL0
M15 GND GND T15 2,6 AVDD_APLL0
M16 T16 CAPVPLL
GND GND 6 CAPVPLL CAPVGND
M17 GND GND T17 6 CAPVGND
M18 T18 APLLCAP1 AUD_CTRL
GND GND 6 APLLCAP1 APLLCAP0 1 AUD_CTRL
N14 GND GND U11 6 APLLCAP0
N15 GND GND U12
N16 U13 ATP1
GND GND 6 ATP1 ATP2
N17 GND GND U14 6 ATP2
N18 GND GND U15
P11 GND GND U16 ANALOG PART
P12 GND GND U17
P13 GND GND U18
P14 GND GND V11
P15 GND GND V12
P16 GND GND V13
P17 GND GND V14
P18 GND GND V15
R11 GND GND V16
R12 GND GND V17
R13 GND GND V18
R14 DV12
GND
R15 GND
R16 GND
R17 GND
R18 C116 C117 C118
GND 0.1uF 0.1uF 0.1uF
C0603/SMD C0603/SMD C0603/SMD
DVREF2
DVREF0
DVREF1
DVREF3

RCLK0#

RCLK1#
RDQM4
RDQM5

RDQM0
RDQM1

RDQM2
RDQM3

RDQM6
RDQM7
RDQS4

RDQS5

RDQS0

RDQS1

RDQS2

RDQS3

RDQS6

RDQS7
RDQ32
RDQ33
RDQ34
RDQ35
RDQ36
RDQ37
RDQ38
RDQ39

RDQ40
RDQ41
RDQ42
RDQ43
RDQ44
RDQ45
RDQ46
RDQ47

RDQ10
RDQ11
RDQ12
RDQ13
RDQ14
RDQ15

RCAS#
RRAS#

RDQ16
RDQ17
RDQ18
RDQ19
RDQ20
RDQ21
RDQ22
RDQ23

RDQ24
RDQ25
RDQ26
RDQ27
RDQ28
RDQ29
RDQ30
RDQ31

RDQ48
RDQ49
RDQ50
RDQ51
RDQ52
RDQ53
RDQ54
RDQ55

RDQ56
RDQ57
RDQ58
RDQ59
RDQ60
RDQ61
RDQ62
RDQ63
RCLK0

RCLK1
RWE#

RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7

RDQ8
RDQ9

RCKE
RCS#
RBA0
RBA1
RA10

RA11
RA12
RA13
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9

MT5351
A A
AE8
AE9
AE20
AE21

AA1
AA2
AA3
AB1
AB2
AB3
AC1
AC2
AC3
AD1
AD2
AD3
AE1
AE2
AE3
AF1
AF2
AF3
AG1
AG2
AH1
AH2
AH3
AG3
AH4
AG4
AF4
AH5
AG5
AF5
AH6
AG6
AF6
AH7
AG7
AF7
AH8
AG8
AF8
AH9
AG9
AF9
AH10
AG10
AF10
AH11
AG11
AF11
AH12
AG12
AF12
AH13
AG13
AF13
AH14
AG14
AF14
AH15
AG15
AF15
AH16
AG16
AF16
AH17
AG17
AF17
AH18
AG18
AF18
AH19
AG19
AF19
AH20
AG20
AF20
AH21
AG21
AF21
AH22
AG22
AF22
AH23
AG23
AF23
AH24
AG24
AF24
AH25
AG25
AF25
AH26
AG26
AH27
AH28
AG28
AG27
AF28
AF27
AF26
AE28
AE27
AE26
AD28
AD27
AD26

AA4
AB4
AC4
AD4
AE4
AE5
AE6
AE7
AE10
AE11
AE12
AE13
AE16
AE17
AE18
AE19
AE22
AE23
AE24
AE25
AD25
BGA471/SMD Add by Ada
DV25
RCLK0#

RCLK1#
RDQM0
RDQM1

RDQM2
RDQM3
RVR EF

RDQS0

RDQS1

RDQS2

RDQS3
R DQ10
R DQ11
R DQ12
R DQ13
R DQ14
R DQ15

R CAS#
R RAS#

R DQ16
R DQ17
R DQ18
R DQ19
R DQ20
R DQ21
R DQ22
R DQ23

R DQ24
R DQ25
R DQ26
R DQ27
R DQ28
R DQ29
R DQ30
R DQ31
R CLK0

R CLK1
RW E#
RD Q0
RD Q1
RD Q2
RD Q3
RD Q4
RD Q5
RD Q6
RD Q7

RD Q8
RD Q9

RC KE
RC S#
RBA0
RBA1
RA10

RA11
RA12
RA13
R A0
R A1
R A2
R A3
R A4
R A5
R A6
R A7
R A8
R A9

Title
MT5351 ASIC
Size Document Number R ev
Custom MT5351RA-V2 TwinSon Chan 1

D ate: Monday, September 26, 2005 Sheet 5 of 8

5 4 3 2 1
 5 4 3 2 1

FS

R37
NS/560
R0603/SMD

R38
NS/10M
R0603/SMD DV33

Y2 4 3 R39 U2CTS
OXTALI OXTALO CB42 VCC OUT NS/10
D 0.1uF 1 2 R0603/SMD D
NS/27MHz C0603/SMD NC GND +5V
C23 TP7 AV33 AV33 CRYS/DIP/SMD 1,2 +5V
OSC1
CAPVPLL CAPVGND APLLCAP1 APLLCAP0 C21 C22 NS/74.25MHz DV33
TP/SMD/D1.0 NS/20pF NS/20pF 1,2,5,8 DV33 AV33
OSC/SMD/A 2,5 AV33
5600pF C24 C25 R40 R41 C0603/SMD C0603/SMD DV25
C0603/SMD 1500pF 1500pF NS/50 NS/50 2,5,7 DV25 DV12
C0603/SMD C0603/SMD R0603/SMD R0603/SMD 2,5 DV12
CAPVGND GND
ATP1 ATP2 1,2,3,4,5,7,8 GND

OSDA0
5 OSDA0 OSCL0
5 OSCL0
DV33 OSDA_MST
X1 4 OSDA_MST OSCL_MST
OPWM0 R42 4 OSCL_MST
1 CVIN VDD 6
8.2K
R0603/SMD C26 C27 C28
CB43
0.1uF
GLOBAL SIGNAL
2 TRI-STATE NC 5
DV33 10nF 1nF 47pF C0603/SMD
C0603/SMD C0603/SMD C0603/SMD 3 4 R43 OXTALI
GND OUT 10 FS
VCXO FR270003 R0603/SMD 5 FS
C29 CB44 CB45 CB46 CB47 CB48 CB49 CB50 CB51 CB52 CB53 CB54
10uF/10v 4.7uF 0.1uF 0.1uF 4.7uF 0.1uF 0.1uF 4.7uF 0.1uF 0.1uF 0.1uF 0.1uF OSC/6P/SMD/7X5 D VDDKP
C0805/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD R44 VCXO0 5 DVDDKP
NS/10 AVDDBGKP
R0603/SMD 2,5 AVDDBGKP
LEFT SIDE RIGHT SIDE TOP SIDE 2,5 AVDDYKP
AV DDYKP
AVDDRKP
2,5 AVDDRKP
AVDD_DMPLL0
DV25 2,5 AVDD_DMPLL0 AVDD_DMPLL1
2,5 AVDD_DMPLL1 AVDD_VPLL
DV33 2,5 AVDD_VPLL AVDD_APLL1
2,5 AVDD_APLL1 AVDD_APLL0
C101 C138 C140 CB57 C183 C184 C185 C186 C104 C179
10uF/10v 4.7uF 0.1uF 4.7uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 2,5 AVDD_APLL0 CAPVPLL
C C0805/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD 5 CAPVPLL CAPVGND C
IR1 5 CAPVGND APLLCAP1
5 APLLCAP1
LEFT SIDE BOTTOM SIDE R45 R46 NS/IR
5 APLLCAP0
APLLCAP0
4.7K 4.7K IR
R0603/SMD R0603/SMD ATP1
5 ATP1

1
2
3
+5V ATP2
DV12 JP1 5 ATP2
O IRI 1 2 ANALOG PART
C31 CB65 CB66 CB67 CB68 CB69 CB70 CB71 CB72 CB73 CB74 CB75 CB76 OSDA0 R47 OSDA_MST 2x1 CB77
10uF/10v 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 100 0.1uF
JP2/DIP/P2.54
C0805/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD R0603/SMD C0603/SMD MEM_VREF
7 MEM_VREF RV REF
5 RVREF
LEFT SIDE RIGHT SIDE TOP SIDE BOTTOM SIDE
OSCL0 R48 OSCL_MST OPWM0
100 5 OPWM0
R0603/SMD OXTALI
5 OXTALI OXTALO
5 OXTALO
DV12 FB7 DVDDKP VCXO0
AV33 5 VCXO0
DV33 U2CTS
FB AVDDBGKP 5 U2CTS
CB78 CB79
BEAD/SMD/0603 4.7uF 0.1uF O IRI
C0603/SMD C0603/SMD 5 OIRI
CB80
0.1uF
C0603/SMD CB81 U13
0.1uF 1 8
C0603/SMD NC VCC
2 NC WP 7
AV DDYKP 3 6 OSCL_MST
NC SCL OSDA_MST
4 GND SDA 5
L31 CB82
MEM_VREF RV REF 0.1uF EEPROM 24C16
C0603/SMD SOP8/SMD/NC
FB C129 C128
B L0603/SMD 0.1uF 0.1uF B
C0603/SMD C0603/SMD AVDDRKP
MT5351 SYSTEM EEPROM
CB85
0.1uF
C0603/SMD

AVDD_DMPLL0

CB86
0.1uF
C0603/SMD

AVDD_DMPLL1

CB87
0.1uF
C0603/SMD

AVDD_VPLL

CB88
0.1uF
C0603/SMD

AVDD_APLL1

CB89
0.1uF
C0603/SMD
A A

AVDD_APLL0

CB90
0.1uF
C0603/SMD

Title
MT5351 PERIPHERAL
Size Document Number Rev
Custom MT5351RA-V2 TwinSon Chan 1

Date: Monday, September 26, 2005 Sheet 6 of 8

5 4 3 2 1
 5 4 3 2 1

+1V25_DDR +1V25_DDR

DV25 DV25 DV25 DV25

RW E# 7 RN14 8 22x4 MEM_WE# MEM_ADDR5 7 RN15 8 75x4 RD Q0 7 RN16 8 47x4 MEM_DQ0 7 RN17 8 75x4
RCAS# 5 6 MEM_CAS# MEM_ADDR4 5 6 RD Q1 5 6 MEM_DQ1 5 6
R CS# 3 4 MEM_CS# MEM_ADDR13 3 4 RD Q2 3 4 MEM_DQ2 3 4 U15 U18
RBA0 1 2 MEM_BA0 MEM_WE# 1 2 RD Q3 1 2 MEM_DQ3 1 2 1 66 1 66
RA10 VDD VSS VDD VSS
7 RN18 8 22x4 MEM_ADDR10 MEM_ADDR10 7 RN19 8 75x4 RD Q4 7 RN20 8 47x4 MEM_DQ4 7 RN21 8 75x4 MEM_DQ0 2 DQ0 DQ15 65 MEM_DQ15 MEM_DQ16 2 DQ0 DQ15 65 MEM_DQ31
RA0 5 6 MEM_ADDR0 MEM_ADDR0 5 6 RD Q5 5 6 MEM_DQ5 5 6 3 64 3 64
RA2 MEM_ADDR2 MEM_ADDR1 RD Q6 MEM_DQ6 MEM_DQ1 VDDQ VSSQ MEM_DQ14 MEM_DQ17 VDDQ VSSQ MEM_DQ30
3 4 3 4 3 4 3 4 4 DQ1 DQ14 63 4 DQ1 DQ14 63
RA3 1 2 MEM_ADDR3 MEM_ADDR2 1 2 RD Q7 1 2 MEM_DQ7 1 2 MEM_DQ2 5 62 MEM_DQ13 MEM_DQ18 5 62 MEM_DQ29
RA5 DQ2 DQ13 DQ2 DQ13
7 RN22 8 22x4 MEM_ADDR5 MEM_ADDR9 7 RN23 8 75x4 RDQS0 R55 47 MEM_DQS0 R56 75 6 VSSQ VDDQ 61 6 VSSQ VDDQ 61 2,5,6 DV25
DV25
RA6 5 6 MEM_ADDR6 MEM_ADDR8 5 6 RDQM0 R57 47 MEM_DQM0 R58 75 MEM_DQ3 7 60 MEM_DQ12 MEM_DQ19 7 60 MEM_DQ28
RA8 MEM_ADDR8 MEM_ADDR7 RDQM1 R59 47 MEM_DQM1 R60 75 MEM_DQ4 DQ3 DQ12 MEM_DQ11 MEM_DQ20 DQ3 DQ12 MEM_DQ27 G ND
3 4 3 4 8 DQ4 DQ11 59 8 DQ4 DQ11 59 1,2,3,4,5,6,8 GND
RA9 1 2 MEM_ADDR9 MEM_ADDR6 1 2 RDQS1 R61 47 MEM_DQS1 R62 75 9 58 9 58
RD Q8 VDDQ VSSQ VDDQ VSSQ
D
7 RN24 8 47x4 MEM_DQ8 7 RN25 8 75x4 MEM_DQ5 10 DQ5 DQ10 57 MEM_DQ10 MEM_DQ21 10 DQ5 DQ10 57 MEM_DQ26
D
RA12 R63 22 MEM_ADDR12 MEM_ADDR12 R64 75 RD Q9
RDQ10
5 6 MEM_DQ9
MEM_DQ10
5 6 MEM_DQ6 11 DQ6 DQ9 56 MEM_DQ9 MEM_DQ22 11 DQ6 DQ9 56 MEM_DQ25 GLOBAL SIGNAL
3 4 3 4 12 VSSQ VDDQ 55 12 VSSQ VDDQ 55
RA13 R65 22 MEM_ADDR13 MEM_CAS# R66 75 RDQ11 1 2 MEM_DQ11 1 2 MEM_DQ7 13 54 MEM_DQ8 MEM_DQ23 13 54 MEM_DQ24
RDQ12 DQ7 DQ8 DQ7 DQ8
7 RN26 8 47x4 MEM_DQ12 7 RN27 8 75x4 14 NC NC 53 14 NC NC 53
RDQ13 5 6 MEM_DQ13 5 6 15 52 15 52
RDQ14 MEM_DQ14 MEM_DQS0 VDDQ VSSQ MEM_DQS1 MEM_DQS2 VDDQ VSSQ MEM_DQS3
3 4 3 4 16 LDQS UDQS 51 16 LDQS UDQS 51
RDQ15 1 2 MEM_DQ15 1 2 MEM_ADDR13 17 50 MEM_ADDR13 17 50 RDQ[0..31]
NC NC MEM_VREF NC NC MEM_VREF 5 RDQ[0..31] RDQS[0..3]
18 VDD VREF 49 18 VDD VREF 49 5 RDQS[0..3]
RDQ16 7 RN28 8 47x4 MEM_DQ16 7 RN29 8 75x4 19 48 19 48 RDQM[0..3]
RDQ17 MEM_DQ17 MEM_DQM0 NC VSS MEM_DQM1 MEM_DQM2 NC VSS MEM_DQM3 5 RDQM[0..3] RA[0..13]
5 6 5 6 20 LDM UDM 47 20 LDM UDM 47 5 RA[0..13]
RRAS# 1 RN30 2 22x4 MEM_RAS# MEM_BA1 1 RN31 2 75x4 RDQ18 3 4 MEM_DQ18 3 4 MEM_WE# 21 46 MEM_CLKA# MEM_WE# 21 46 MEM_CLKB# RBA [0..1]
RBA1 MEM_BA1 MEM_BA0 RDQ19 MEM_DQ19 MEM_CAS# WE CLK MEM_CLKA MEM_CAS# WE CLK MEM_CLKB 5 RBA[0..1] RCLK0
3 4 3 4 1 2 1 2 22 CAS CLK 45 22 CAS CLK 45 5 RCLK0
RA1 5 6 MEM_ADDR1 MEM_CS# 5 6 RDQ20 7 RN32 8 47x4 MEM_DQ20 7 RN33 8 75x4 MEM_RAS# 23 44 MEM_CLKEN MEM_RAS# 23 44 MEM_CLKEN RCLK0#
RA4 MEM_ADDR4 MEM_RAS# RDQ21 MEM_DQ21 MEM_CS# RAS CKE MEM_CS# RAS CKE 5 RCLK0# R CS#
7 8 7 8 5 6 5 6 24 CS NC 43 24 CS NC 43 5 RCS#
RDQ22 3 4 MEM_DQ22 3 4 25 42 MEM_ADDR12 25 42 MEM_ADDR12 RRAS#
RA7 R67 22 MEM_ADDR7 MEM_ADDR3 R68 75 RDQ23 MEM_DQ23 MEM_BA0 NC A12 MEM_ADDR11 MEM_BA0 NC A12 MEM_ADDR11 5 RRAS# RCAS#
1 2 1 2 26 BS0 A11 41 26 BS0 A11 41 5 RCAS#
RDQS2 R69 47 MEM_DQS2 R70 75 MEM_BA1 27 40 MEM_ADDR9 MEM_BA1 27 40 MEM_ADDR9 RW E#
RA11 R71 22 MEM_ADDR11 MEM_ADDR11 R72 75 RDQM2 R73 47 MEM_DQM2 R74 75 MEM_ADDR10 BS1 A9 MEM_ADDR8 MEM_ADDR10 BS1 A9 MEM_ADDR8 5 RWE# R CKE
28 A10/AP A8 39 28 A10/AP A8 39 5 RCKE
RDQM3 R75 47 MEM_DQM3 R76 75 MEM_ADDR0 29 38 MEM_ADDR7 MEM_ADDR0 29 38 MEM_ADDR7 RCLK1
R CKE R77 22 MEM_CLKEN MEM_CLKEN R78 NS/75 RDQS3 R79 47 MEM_DQS3 R80 75 MEM_ADDR1 A0 A7 MEM_ADDR6 MEM_ADDR1 A0 A7 MEM_ADDR6 5 RCLK1 RCLK1#
30 A1 A6 37 30 A1 A6 37 5 RCLK1#
RDQ24 7 RN34 8 47x4 MEM_DQ24 7 RN35 8 75x4 MEM_ADDR2 31 36 MEM_ADDR5 MEM_ADDR2 31 36 MEM_ADDR5 MEM_VREF
RDQ25 MEM_DQ25 MEM_ADDR3 A2 A5 MEM_ADDR4 MEM_ADDR3 A2 A5 MEM_ADDR4 6 MEM_VREF
5 6 5 6 32 A3 A4 35 32 A3 A4 35
RDQ26 3 4 MEM_DQ26 3 4 33 34 33 34
VDD VSS VDD VSS
CLOSED TO MT5351 CLOSED TO DDR RDQ27 1 2 MEM_DQ27 1 2 DDR MEMORY
RDQ28
RDQ29
7 RN36
5
8 47x4 MEM_DQ28
6 MEM_DQ29
7 RN37
5
8 75x4
6
16M x 16 DDR TSOP-66
TSOP_0D65_22D6LX9D7W_66SP
16M x 16 DDR TSOP-66
TSOP_0D65_22D6LX9D7W_66SP EQUAL LINE LENGTH
RDQ30
RDQ31
3 4 MEM_DQ30
MEM_DQ31
3 4 DDR#1 DDR#2
1 2 1 2
RCLK0 R102 MEM_CLKA
47
R0603/SMD R103
100
CLOSED TO MT5351 CLOSED TO DDR
R0603/SMD
RCLK0# R105 MEM_CLKA#
47
R0603/SMD
C C

RCLK1 R106 MEM_CLKB

47
R0603/SMD R107
100
R0603/SMD
RCLK1# R108 MEM_CLKB# +1V25_DDR
47
R0603/SMD

CB91 + CE23 R104

0.1uF 220uF/16v
CLOSED TO MT5351 CLOSED TO DDR C0603/SMD C220UF16V/D6H11
4.7K
R0603/SMD

U19
1 8 DV25
GND VTT
2 SD PVIN 7
3 VSENSE AVIN 6
MEM_VREF 4 5
+1V25_DDR DV25 VREF VDDQ
C139 IC LP2996 DDR Termination SOP-8 + CE24
C168 C169 CB95 C171 C170 C180 C181 C141 C142 C143 C144 C145 0.1uF SOP8/SMD 47uF/16v
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C0603/SMD C47UF16V/D5H5
C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD + CE25 C153 C154 C155 C156 C157 C158 C159 C172 C152
220uF/16v 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C220UF16V/D6H11 C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD

+1V25_DDR FOR DDR#1

BYPASS CAP. FOR DIMM
C146 C147 C148 C150 C151 C160 C161 C162 C163 C164 C165 C166
DV25
+1V25_DDR FOR DDR TERMINATOR
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
0.1uF
C0603/SMD
MEM_VREF FOR DDR AND MT5351 VREF
+ CE26 CB125 CB126 C173 C174 C175 C176 C177 C178
220uF/16v 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
+1V25_DDR C220UF16V/D6H11 C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD
B
CB133 C167 BYPASS CAP. FOR TERMINATOR FOR DDR#2 +1V25_DDR B
0.1uF
C0603/SMD
0.1uF
C0603/SMD (EVERY 2 RESISTOR PUT 1 BYPASS CAP.)
BYPASS CAP. FOR DDR

+ CE28 + CE29
220uF/16v 220uF/16v
DV25 C220UF16V/D6H11 C220UF16V/D6H11
C182
C102 C105 C106 C107 C108 C109 C110 C111 C103 0.1uF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C0603/SMD
C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD C0603/SMD

ADD by Ada

A A

Title
DDR MEMORY
Size Document Number R ev
C ustom MT5351RA-V2 TwinSon Chan 1

Date: Monday, September 26, 2005 Sheet 7 of 8

5 4 3 2 1
 5 4 3 2 1

U17
PDA1 25 29 PDD0
PDA2 A0 D0 PDD1
24 A1 D1 31
PDA3 23 33 PDD2 DV33 DV33 +5V
PDA4 A2 D2 PDD3 1,2,6 +5V DV33
22 A3 D3 35 1,2,5,6 DV33
PDA5 21 38 PDD4
PDA6 A4 D4 PDD5 G ND
20 A5 D5 40 1,2,3,4,5,6,7 GND
PDA7 19 42 PDD6 R82 R83
PDA8 A6 D6 PDD7 NS/4.7K NS/4.7K
18 A7 D7 44
PDA9 8 30 R0603/SMD R0603/SMD ORESET#
PDA10 A8 D8 PDA0 PDA1 PDA2 1,4,5 ORESET#
7 A9 D9 32
D
PDA11
PDA12
6 A10 D10 34
R84 R85
GLOBAL SIGNAL D
5 A11 D11 36
PDA13 4 39 ORESET# NS/4.7K
PDA14 A12 D12 0 R0603/SMD
3 A13 D13 41
PDA15 2 43 R0603/SMD C32 POCE0#
PDA16 A14 D14 PDA0 NS/10pF 5 POCE0# POOE0#
1 A15 D15/A-1 45 5 POOE0#
PDA17 48 C0603/SMD POWE#
DV33 PDA18 A16 NOR_WP# R86 5 POWE#
17 A17 WP/ACC 14
PD D[0..7]
PDA19
PDA20
16 A18 RY/BY 15 NOR_R Y_BY0#
NS/4.7K
TRAP CIRCUIT 5 PDD[0..7] PDA[0..22]
9 A19 BYTE 47 5 PDA[0..22]
PDA21 10 R0603/SMD FB9 DV33
A20
R87
4.7K
PDA22
POCE0#
13 A21 VCC 37
FB
FLASH INTERFACE
26 CE
R0603/SMD POOE0# 28 27 CB145 + CE27 BEAD/SMD/0603
POWE# OE GND1 0.1uF 10uF/16v DV33
11 WE GND2 46
R88 C0603/SMD C10UF16V/D5H11 JTRST#
ORESET# NOR_RST# 5 JTRST# JTDI
12 RESET 5 JTDI
0 JTMS
R0603/SMD IC FLASH MX29LV320 32Mb TSOP-48 R89 R90 5 JTMS JTCK
C33
10pF TSOP48/SMD 4.7K 4.7K 5 JTCK JRTCK
R0603/SMD R0603/SMD 5 JRTCK
C0603/SMD
NOR FLASH #0 1
J2
5 JTDO
JTDO

U0RX
U0TX
2 JTAG PORT
3
4

CLI OUTPUT 4x1 W/HOUSING

DIP4/W/H/P2.0 1,5 U0RX
U0RX
U0TX
1,5 U0TX U1RX
5 U1RX U1TX
DV33 5 U1TX U2TX
C 1,5 U2TX U2RX C
1,5 U2RX
2
4
6
8

R91 RN38 R92 R93 DV33

UART (RS232)
1K 1Kx4 4.7K 4.7K
R0603/SMD RN0603/SMD R0603/SMD R0603/SMD
R
J3 R94 R95 5 R B
5 B
1
3
5
7

TVTREF#1 1 2 4.7K 4.7K G

JTRST# R0603/SMD R0603/SMD J4 5 G VOHSYNC
3 4 1,5 VOHSYNC
JTDI 5 6 1 VOVSYNC
JTMS U1RX 1,5 VOVSYNC
7 8 2
JTCK 9 10 U1TX 3
JRTCK R96 0 R0603/SMD 11 12 4
JTDO R97 0 R0603/SMD 13 14
15 16 4x1 W/HOUSING
JTAG_DBGRQ
JTAG_DBGACK
17
19
18
20
SOFTWARE DEBUG PORT DIP4/W/H/P2.0

R98 R99 10x2

4.7K 4.7K DIP10X2/W/H/IDE/P2.54
R0603/SMD R0603/SMD
DV33

R100 R101
4.7K 4.7K
R0603/SMD R0603/SMD J5
1
B U2RX 2 B
U2TX 3
4

FOR SOFTWARE LINK 4x1 W/HOUSING

DIP4/W/H/P2.0

J6

R 1
2
B 3
4
G 5
6
VOHSYNC 7
VOVSYNC 8

CON8

ADD
A A

Title
NOR FLASH / JTAG / UART
Size Document Number R ev
Custom MT5351RA-V2 TwinSon Chan 1

Date: Monday, September 26, 2005 Sheet 8 of 8

5 4 3 2 1
Basic Operations & Circuit Description

MODULE
There are 1 pcs panel and 8 pcs PCB including 2 pcs Y/Z Sustainer board, 2 pcs Y Drive
board, 2 pcs X (left and right) Extension PCB, 1 pcs Control (Signal Input) and 1 pcs Power
board in the Module.
SET
There are 6 pcs PCBs including 1 pcs Tuner/Audio board, 1 pcs Keypad board, 1 pcs
Remote Control Receiver board, 1 pcs L/R Speakers and 1 pcs Main (Video) board, 1 pcs ATSC
1 pcs ATSC board in the SET.
 Parts position

Internal Speaker (Right) Power Supply Internal Speaker (Left)

Y-Drive Top

Z-Sustainer
Y-Sustainer

Y-Drive External Speaker

Bottom Terminal

X Left
Extension Power SW

ATSC Main EMI Filter + AC Inlet

Local Key Tuner/Audio X Right Extension

remote control
receiver
Control (Signal Input)
PCB function
1. Power:
(1). Input voltage: AC 110V~240V, 47Hz~63Hz.
Input range: AC 90V(Min)~265V(Max) auto regulation.
(2). To provide power for PCBs.
2. Main board: To converter TV signals, S signals, AV signals, Y Pb/
Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit to
Control board.
3. Control board: Dealing with the digital signal for output to panel.
4. Y-Sustainer / Z-Sustainer board:
(1). Receiving the signals from Control and high voltage supply.
(2). Output scanning waveform for Module.
5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning wave-
form to the panel.
6. X (left and right) extension board: Output addressing signals.
7. Tuner/Audio Board: : Amplifying the audio signal to the internal or external speakers
of which selected.
To convert TV RF signal to video and SIF audio signal to Main board.
8. ATSC Board: Receiver and converter ATSC TV signal to transmit to main board.
PCB failure analysis

1. CONTROL: a. Abnormal noise on screen. b. No picture.

2. MAIN : a. Lacking color, Bad color scale.
b. No voice.
c. No picture but with signals output, OSD and back light.
d. Abnormal noise on screen.
3. POWER: No picture, no power output.
4. Z - Sustainer: a. No picture.
b. Color not enough.
c. Flash on screen.
5. Y - Sustainer: Darker picture with signals.

6. Tuner/Audio : a. No voice. (Make sure status: Mute / Internal, External speaker)

b. Noise
c. No ATV signals
7. Y/Z - Sustainer: The component working temperature is about 55oC.
If the temperature rises abnormal, this may be a error point.

8. ATSC: a. No ATSC TV signal

Basic operation of Plasma Display

1. After turning on power switch, power board sends 5Vst-by Volt to Main
IC MT8205 waiting for ON signals from Key Switch or Remote Receiver.

2. When the ON signal from Key Switch or Remote Receiver is detected, MT8205 will send
ON Control signals to Power. Then Power sends (5Vsc, 9Vsc, 12Vsc, 24V and RLY
ON, Vs ON) to PCBs working. This time VIF will send signals to display back light,
OSD on the panel and start to search available signal sources. If the audio signals
input, them will be amplified by Audio AMP and transmitted to Speakers.

3. If some abnormal signals are detected (for example: over volts, over current, over
temperature and under volts), the system will be shut down by Power off.
Main IC Specifications

- MT8205
- SiI169
- M13S128168A
- MP7720
 MT8205/8203
Specifications are subject to change without notice Application Notes

History
2004/09/12 Runma Chen for customer design-in V1.0
2004/09/30 Dragon Chen Add feature list V1.1
2004/09/30 Runma Chen Modify for PIP/POP 444 support V1.2
2004/10/01 Runma Chen PIP/POP hardware limitation-I V1.3
2004/10/18 Dragon Chen & PIP/POP hardware limitation-II & video front end component V1.4
Wen Hsu
2004/10/20 Dragon Chen Update functional block V1.5
2004/10/21 Dragon Chen Correct function block fault to V1.4 V1.6
2004/11/04 Dragon Chen 1. Delete power spec. (About power spec, please reference another document) V1.7
2. Add AC & DC characteristics
3. Add pin description
4. Add audio out mapping rule
2004/11/05 Dragon Chen Descript more detail for pin power initial state & remove some description to V1.8
another document (MT8205 product brief)

Page 1 October, 2004

 MT8205/8203
Specifications are subject to change without notice Application Notes

MT8205/8203 Application Notes

MT8205/8203 is a highly integrated single chip for LCD TV supporting video input and output format up to HDTV.
It includes 3D comb filter TV Decoder to retrieve the best image from popular composite signals. On-chip
advanced motion adaptive de-interlacer converts accordingly the interlace video into progressive one with overlay
of a 2D Graphic processor. Optional 2nd HDTV or SDTV inputs allows user to see multi-programs on same screen.
Flexible scalar provides wide adoption to various LCD panel for different video sources. Its on-chip audio
processor decodes analog signals from Tuner with lip sync control, delivering high quality post-processed sound
effect to customers. On-chip microprocessor reduces the system BOM and shortens the schedule of UI design by
high level C program. MT8205/8203 is a cost-effective and high performance HDTV-ready solution to TV
manufactures.

FEATURES

Video Input
Input Multiplexing:
Without external switch, it supports
1x Component,
1x S-video,
1x VGA/Component, (dual function ports)
1x Digital and
3x Composite inputs
All the input sources can be flexibly routed to Main/PIP internally
Input Formats:
Support VGA input up to SXGA (1280x1024@60Hz) including SOG VGA
Support HDTV 480p/720p/1080i input
Support DVI 24-bit RGB digital input
Support CCIR-656/601 digital input

TV decoder
For PIP/POP:
Dual identical TVD on chip (Single on MT8203)
3D-Comb for both path.
Dual VBI decoders for the application of V-Chip
Supporting formats:
Support PAL (B,G,D,H,M,N,I,Nc), PAL(Nc), PAL, NTSC, NTSC-4.43, SECAM
Automatic Luma/Chroma gain control
Automatic TV standard detection
NTSC/PAL Motion Adaptive 3D comb filter
Motion Adaptive 3D Noise Reduction
VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS
Macrovision detection

Page 2 October, 2004

 MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

2D-Graphic/OSD processor
Two OSD planes. (For example, Teletext and V-Chip will occupy one planes)
Support alpha blending among these two planes and video
Support Text/Bitmap decoder
Support line/rectangle/gradient fill
Support bitblt
Support color Key function
Support Clip Mask
65535/256/16/4/2-color bitmap format OSD,
Automatic vertical scrolling of OSD image
Support OSD mirror and upside down

Host Micro controller

Turbo 8032 micro controller
Built-in internal 373 and 8-bit programmable lower address port
2048-bytes on-chip RAM
Up to 4M bytes FLASH-programming interface
Supports 5/3.3-Volt. FLASH interface
Supports power-down mode
Supports additional serial interface
IR control serial input
Support RS232 interface
Support single interface directly supporting SD/MS/MMC memory card
Support 2 PWM output
Support DDC2Bi/DDC2B/DDC1/DDCCI
Maximum 48 programmable GPIO pins
DRAM Controller
Supports up to 32M-byte SDR/DDR DRAM
Supports 16 bit DDR or 32 bit SDR/DDR bus interface
Build in a DRAM interface programmable clock to optimize the DRAM performance
Programmable DRAM access cycle and refresh cycle timings
Maximum DRAM clock rate is 166MHz
Support 3.3/2.5-Volt SDR/DDR Interface

Video Processor
Color Management
Flesh tone and multiple-color enhancement. (For skin, sky, and grass…)
Gamma/anti-Gamma correction
Color Transient Improvement (CTI)
Saturation/hue adjustment
Contrast/Brightness/Sharpness Management
Sharpness and DLTI/DCTI
Brightness and contrast adjustment
Black level extender
White peak level limiter
Adaptive Luma/Chroma management
De-interlacing
Automatic detect film or video source

Page 3 July, 2004

 MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

3:2/2:2 pull down source detection

Advanced Motion adaptive de-interlacing
Scaling
Arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X
Advanced linear and non-linear Panorama scaling.
Programmable Zoom viewer
Picture-in-Picture (PIP)
Picture-Out-Picture (POP)
Display
12/10, 10/8, 8/6 Dithering processing for LCD display
10bit gamma correction
Support Alpha blending for Video and two OSD planes
Frame rate conversion

Audio Input/Output
2 path TV audio in.
Support AF/SIF decode from Tuner.
2 channel audio L/R digital line in.
Total support 12 channel digital outputs optional for general stereo, 2.1 channel with subwoofer, 5.1 channel, and
headphone out.

Audio Features
Support BTSC/EIAJ/A2/NICAM decode
Stereo demodulation, SAP demodulation
Mode selection (Main/SAP/Stereo)
Equalizer
Sub-woofer/Bass enhancement
MTK proprietary 3D surround processing (Virtual surround)
Audio and video lip synchronization
Support Reverberation

JPEG Decoder
Decode base-line/progressive JPEG file thru memory card i/f
SD/MS/MMC, Maximum 1000 files (depend on DRAM size), FW is not finished yet. (10/E will be ready)

Video Output
480i/576i/480p/576p/720p/1080i
Up to (1280x1024@75Hz) (1366x768@60Hz)
Dual-channel 6/8-bit LVDS/TTL output
Support video output mirror and upside down

DRAM Usage
For features of 8205, 2pcs of 8x16 DDR166 is necessary
For features of 8203, 2/1pcs of 8x16 DDR (limited PIP/POP features)
Here is a comparison chart between (2xDDR) and (1xDDR)

Page 4 July, 2004

 MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

DDR*1(16Mb) DDR*2(32Mb)
NR Y Y
3D-Comb Y Y
MDDi 480i/576i 1080i
PIP *Y Y
POP *Y Y
Display 1024x768 1920x1080

For 1080i input, 8203 only support bob mode de-interlacing.

With single DDR, we could support very limited PIP/POP mode.

Flash Usage
Flash is used to store FW code, fonts, bitmaps, big tables for VGA, Video, Gamma..
In our demo system, we can support 2-4 languages within 1MB flash.
For single country, we need around 20KB to store font data.
For more bitmaps, we need more flash space to store them.
2Mbytes is recommended to build a general TV model.

Outline
388-pin BGA package
3.3/1.8-Volt. Dual operating voltages
0.18um UMC process

Page 5 July, 2004

 MT8205
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

BLOCK DIAGRAM

CVBS (AV) Analog Front End

(x3) 8032
ADC 3D TVD
S Main Path
(Customer) ADC 3D TVD MDDi
DS
External YPbPr MLC
ADC HDTVD
Switches

MUX
PIP Path
VGA (aRGB) ADC VGAD PLC

DRAM
DS
Analog Path DI
Digital Digital Path
2D Graph
Control Signal (GPIO, …) OSD OSD
Merge
TTL
Color US
LVDS LVDS Tx Gamma

Dithering DSP

Page 6 July, 2004

 ®

Technology

SiI 169
HDCP PanelLink Receiver

Data Sheet

Document # SiI-DS-0049-B
SiI 169 HDCP PanelLink Receiver
Data Sheet

Silicon Image, Inc.

SiI-DS-0049-B
August 2002

Application Information
To obtain the most updated Application Notes and other useful information for your design, contact your local
Silicon Image sales office. Please also visit the Silicon Image web site at www.siliconimage.com.

Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.

Trademark Acknowledgment
® ®
Silicon Image, the Silicon Image logo, PanelLink and the PanelLink Digital logo are registered trademarks of
TM ®
Silicon Image, Inc. TMDS is a trademark of Silicon Image, Inc. VESA is a registered trademark of the Video
Electronics Standards Association. All other trademarks are the property of their respective holders.

Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.

Revision History

Revision Date Comment

A 07/18/2002 Release to Production with complete parametric information.
B 08/14/2002 Correction to DDC bus voltage level-shifting diagram; add Pb-free part number.

© 2002 Silicon Image. Inc.

ii SiI-DS-0049-B
 SiI 169 HDCP PanelLink Receiver
Data Sheet

TABLE OF CONTENTS

Functional Description .................................................................................................................................... 2

PanelLink TMDS Core ................................................................................................................................ 2
2
I C Interface and Registers ......................................................................................................................... 2
HDCP Decryption Engine and XOR Mask .................................................................................................. 3
HDCP Keys EEPROM................................................................................................................................. 3
Panel Interface Logic and Configuration Logic ........................................................................................... 3
Electrical Specifications .................................................................................................................................. 4
Absolute Maximum Conditions.................................................................................................................... 4
Normal Operating Conditions...................................................................................................................... 4
DC Specifications ........................................................................................................................................ 5
AC Specifications ........................................................................................................................................ 6
Timing Diagrams ......................................................................................................................................... 8
Input Timing ............................................................................................................................................. 8
Output Timing .......................................................................................................................................... 8
Pin Descriptions .............................................................................................................................................11
Digital Output Pins......................................................................................................................................11
Configuration Pins ......................................................................................................................................11
HDCP Pins ................................................................................................................................................ 12
Power Management Pins .......................................................................................................................... 12
Differential Signal Data Pins...................................................................................................................... 12
Reserved Pin............................................................................................................................................. 12
Power and Ground Pins ............................................................................................................................ 13
Feature Information ...................................................................................................................................... 14
HSYNC De-jitter Function ......................................................................................................................... 14
Clock Detect Function ............................................................................................................................... 14
Sync Detect Function ................................................................................................................................ 14
OCK_INV Function.................................................................................................................................... 14
TFT Panel Data Mapping .......................................................................................................................... 16
Power Management .................................................................................................................................. 22
HDCP Operation ....................................................................................................................................... 23
HDCP Authentication............................................................................................................................. 23
SiI 169 HDCP Implementation .............................................................................................................. 24
2
HDCP DDC / I C Interface..................................................................................................................... 24
2
Video Requirement for I C Access ........................................................................................................ 25
2
I C Registers.......................................................................................................................................... 25
Using SiI 169 in SiI 161B Designs ............................................................................................................ 28
EXT_RES Resistor Choice ....................................................................................................................... 29
Power Control............................................................................................................................................ 30
Receiver DDC Bus Level-Shifting ............................................................................................................. 30
Voltage Ripple Regulation ......................................................................................................................... 31
Decoupling Capacitors .............................................................................................................................. 32
ESD Protection.......................................................................................................................................... 32
Receiver Layout ........................................................................................................................................ 33
EMI Considerations ................................................................................................................................... 33
PCB Thermal Design ................................................................................................................................ 33
Determining Heat Dissipation Requirements ........................................................................................ 33
Implementation Guidelines for Thermal Land Design ........................................................................... 34
Board Mounting Guidelines ................................................................................................................... 36
Stencil Design........................................................................................................................................ 37
Package........................................................................................................................................................ 38
Ordering Information..................................................................................................................................... 38

SiI-DS-0049-B iii
SiI 169 HDCP PanelLink Receiver
Data Sheet

LIST OF TABLES
Table 1. One Pixel per Clock Mode Data Mapping ....................................................................................... 16
Table 2. Two Pixel per Clock Mode Data Mapping ....................................................................................... 16
TM
Table 3. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2 Compliant.................... 17
Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 18
Table 5. 24-bit One Pixel per Clock Input with 24-bit Two Pixel per Clock Output TFT Mode...................... 19
Table 6. 18-bit One Pixel per Clock Input with 18-bit Two Pixel per Clock Output TFT Mode...................... 20
Table 7. Two Pixel per Clock Input with One Pixel per Clock Output TFT Mode.......................................... 21
Table 8. Power Management Functionality Table ......................................................................................... 22
2
Table 9. I C Register Mapping ...................................................................................................................... 26
2
Table 10. I C Register Definitions ................................................................................................................. 27
Table 11. Link Impedance vs EXT_RES Value (all values in Ohms) ............................................................ 29
Table 12. Power Consumption Characteristics ............................................................................................. 30
Table 13. Recommended Components ........................................................................................................ 32

LIST OF FIGURES
Figure 1. SiI 169 Pin Diagram......................................................................................................................... 1
Figure 2. Functional Block Diagram................................................................................................................ 2
Figure 3. Channel-to-Channel Skew Timing ................................................................................................... 8
Figure 4. Digital Output Transition Times ....................................................................................................... 8
Figure 5. Receiver Clock Cycle/High/Low Times............................................................................................ 8
Figure 6. Output Signals Setup/Hold Times.................................................................................................... 9
Figure 7. Output Signals Disabled Timing from PD# Active ........................................................................... 9
Figure 8. Output Signals Disabled Timing from Input Clock Inactive.............................................................. 9
Figure 9. Input Clock Active to Output Active ................................................................................................ 9
Figure 10. SCDT Timing from DE Inactive/Active......................................................................................... 10
Figure 11. TFT Two Pixels per Clock Staggered Output Timing Diagram .................................................... 10
2
Figure 12. I C Data Valid Delay (driving Read Cycle data) ........................................................................... 10
Figure 13. Block Diagram for OCK_INV ....................................................................................................... 15
Figure 14. HDCP System Architecture ........................................................................................................ 23
2
Figure 15. I C Byte Read .............................................................................................................................. 24
2
Figure 16. I C Byte Write .............................................................................................................................. 24
Figure 17. Short Read Sequence ................................................................................................................. 25
Figure 18. Design Using SiI 161B or SiI 169 ................................................................................................ 29
Figure 19. DDC Bus Voltage Level-Shifting using Fairchild NDC7002N ...................................................... 30
Figure 20. Voltage Regulation using Texas Instruments TL431 ................................................................... 31
Figure 21. Voltage Regulation using National Semiconductor LM317.......................................................... 31
Figure 22. Decoupling and Bypass Schematic ............................................................................................. 32
Figure 23. Decoupling and Bypass Capacitor Placement ............................................................................ 32
Figure 24. DVI to Receiver Routing - Top View ............................................................................................ 33
Figure 25. Bottom View of Thermally Enhanced 100-pin TQFP Package.................................................... 34
Figure 26. TQFP Thermal Land Design on PCB .......................................................................................... 35
Figure 27. Thermal Pad Via Grid .................................................................................................................. 36
Figure 28. Recommended Stencil Design .................................................................................................... 37
Figure 29. Package Diagram ........................................................................................................................ 38

iv SiI-DS-0049-B
SiI 169 HDCP PanelLink Receiver
Data Sheet
General Description Features

The SiI 169 Receiver uses PanelLink Digital • Integrated 25-165MHz PanelLink core to support
technology to support HDTV and high-resolution VGA to UXGA resolutions
digital displays for DTV and PC applications. It • Supports HDTV resolutions (720p/1080i)
features High-bandwidth Digital Content Protection • Integrated HDCP decryption engine for viewing
(HDCP) for secure delivery of high-definition video in protected content
consumer electronics products. • Pre-programmed HDCP keys provide highest
level of key security, simplify manufacturing
The SiI 169 comes with integrated, pre-programmed
• Enhanced jitter tolerance
HDCP keys, greatly simplifying manufacturing and
• Time staggered data output for reduced ground
providing the highest level of security. For improved
bounce
ease of use, the SiI 169 has enhanced jitter
• High Skew Tolerance: 1 full input clock cycle
tolerance and a low-power standby mode.
(6ns at 165MHz)
PanelLink Digital technology is the world’s leading • Backwards compatible with SiI 161B
DVI solution, providing a digital interface solution that • Sync Detect for “Hot Plugging”
is easy to implement and cost-effective. PanelLink • Flexible low power modes with automatic power
further simplifies the display interface design by down when input clock is inactive
resolving many of the system level issues associated • Low power 3.3V core operation
with high-speed mixed signal circuits. • Compliant with DVI 1.0
• Standard and Pb-free packages (see page 38).

SiI 169 Pin Diagram

OUTPUT
CLOCK

CONTROLS
EVEN 8-bits RED
HS_DJTR
OCK_INV
HSYNC
VSYNC

OGND
OGND

OVCC
ODCK
OVCC

QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16

QE15
QE14
CTL3

GND
VCC
QO1
QO0

DE

EVEN 8-bits GREEN

ODD 8-bits BLUE

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
QO2 51 26 25 QE13
QO3 52 24 QE12
QO4 53 23 QE11
QO5 54 22 QE10
QO6 55 21 QE9
QO7 56 20 QE8
OVCC 57 19 OGND
OGND 58 18 OVCC
QO8 59 17 QE7
QO9 60 16 QE6
ODD 8-bits GREEN

EVEN 8-bits BLUE

SiI 169
QO10 61 15 QE5
QO11 62 14 QE4
QO12 63 100-pin TQFP 13 QE3
QO13 64 (Top View) 12 QE2
QO14 65 11 QE1
QO15 66 10 QE0
VCC 67 9 PDO#
GND 68 8 SCDT
QO16 69 7 STAG_OUT
QO17 70 6 VCC
CONFIG. PINS

QO18 71 5 GND
QO19 72 4 PIXS
ODD 8-bits RED

QO20 73 3 SDA
QO21 74 2 PD#
QO22 75 1 RESET#
100
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
RESERVED
AVCC

PGND

SCL
QO23

PVCC
OGND

RX2-

RX1-

RX0-

RXC+
RXC-
RX2+

RX1+

RX0+

EXT_RES
OVCC
AGND

AGND

AGND

AGND

AGND
AVCC

AVCC

AVCC

DIFFERENTIAL SIGNALS PLL

Figure 1. SiI 169 Pin Diagram

SiI-DS-0049-B 1
SiI 169 HDCP PanelLink Receiver
Data Sheet

Functional Description
The SiI 169 is a DVI 1.0 compliant digital-output receiver with built-in High-bandwidth Digital Content Protection
(HDCP). It provides a simple, cost effective solution for DTVs implementing DVI-HDCP. Pre-programmed HDCP
keys simplify manufacturing while providing the highest level of security. There is no need to use encrypted keys,
program EEPROMs, or cure epoxy coating.
Figure 2 shows the functional blocks of the chip.

STAG_OUT

HS_DJTR
OCK_INV

RESET#

PDO#
PIXS

PD#
Registers HDCP HDCP
-------------- Decryption Keys
Configuration Logic Engine EEPROM

SCLS I2C
SDAS Slave
CTL3
QE[23:0]
RXC±
PanelLink 24 24
XOR Panel QO[23:0]
RX0± TMDSTM / /
encrypted Mask unencrypted Interface ODCK
RX1± Digital data data
RX2± Core Logic DE
HSYNC
control
EXT_RES VSYNC

SCDT

Figure 2. Functional Block Diagram

PanelLink TMDS Core

The PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
core senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
the necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a display enable (DE) signal that drives high
when video pixel data is present. The SCDT signal is output when there is active video on the DVI link and the
PLL has locked on to the video. SCDT can be used to trigger external circuitry, indicating that an active video
signal is present; or used to place the device outputs in power down when no signal is present (by tying SCDT to
PDO#). A resistor tied to the EXT_RES pin is used for impedance matching.

2
I C Interface and Registers
2
The SiI 169 uses a slave I C interface, capable of running at 400kHz, for communication with the host. HDCP
2
authentication is managed by reading and writing to registers through the I C interface. This bus, called DDC in
the DVI specification, is also tied to the EDID EEPROM that contains information about the display’s capabilities
2
(resolution, aspect ratio, etc.). The I C address of the SiI 169 is 74h as specified by HDCP. This interface is not
5V tolerant and it is recommended that a voltage level shifter be used between the SiI 169 and the DVI connector
as the DDC bus is specified to support 5V signaling.

2 SiI-DS-0049-B
 SiI 169 HDCP PanelLink Receiver
Data Sheet

HDCP Decryption Engine and XOR Mask

The HDCP decryption engine contains all the necessary logic to decrypt an incoming video signal on a pixel-by-
pixel basis. The host system microcontroller initiates an authentication sequence with the receiver to initialize the
SiI 169 HDCP decryption engine. Upon successful completion of the authentication process, the SiI 169 is ready
to decrypt the incoming video via the XOR mask.
Encrypted and unencrypted video will be sent at different times. Therefore the host HDCP transmitter uses the
CTL3 signal to indicate to the SiI 169 receiver whether the incoming video is encrypted or not.

HDCP Keys EEPROM

The SiI 169 comes pre-programmed with a production set of HDCP keys in its internal EEPROM. In this way the
keys are provided the highest level of protection as required by the HDCP specification. Silicon Image manages all
aspects of the key purchasing and programming. There is no need for the customer to purchase HDCP keys from
the licensing authority. For security reasons, the keys cannot be read out of the device.

Samples of the SiI 169 are available with the B1 public keys as listed in the back of the HDCP specification.
These are marked with a -PUB part number as noted in the Ordering Information section. Make sure to request
either “Public” or “Production” keys when requesting samples. Before receiving samples of the SiI 169 with
production keys a customer must have signed the HDCP license agreement.

Panel Interface Logic and Configuration Logic

Unencrypted video data is sent to the display logic by way of a 48-bit output interface. The functionality of this
interface is affected by several of the externally strapped configuration logic options as follows.

• The data output can be presented in either one pixel per clock or two pixels per clock format, depending on
the PIXS configuration setting.

• The polarity of the output clock ODCK can be inverted to accommodate both rising- and falling-edge clocking
through the OCK_INV configuration setting.

• Using the STAG_OUT configuration setting, the odd and even data output groups can be staggered in time to
reduce EMI.

• The HS_DJTR configuration setting can compensate for host-side jitter on the HSYNC input to the transmitter.

• The PD# and PDO# inputs select chip power down modes and allow for disabling of the outputs to the panel.
The RESET# input must be in the HIGH state during normal operation, in both HDCP and non-HDCP modes. Its
primary purpose is to reset the digital block circuitries, including the HDCP engine, and registers at initial chip
power-up time. The VSYNC, HSYNC, DE, and CTL3 signals will be driven low while RESET# is asserted. If it is
necessary to disable the HDCP engine while leaving the chip fully operational for reception of unencrypted video, use the
software reset feature located at bit 0 of register 0xFF by setting it to “1”.

SiI-DS-0049-B 3
ESMT M13S128168A
Revision History

Revision 0.1 (15 Jan. 2002)

- Original

Revision 0.2 (19 Nov. 2002)

-changed ordering information & DC/AC characteristics

Revision 0.1 Revision 0.2

M13S128168A - 5T M13S128168A - 6T
M13S128168A - 6T M13S128168A - 7.5AB

Revision 0.3 (8 Aug. 2003)

-Change IDD6 from 3mA to 5mA.

Revision 0.4 (27 Aug. 2003)

-Change ordering information & DC / AC characteristics.

Revision 1.0 (21 Oct. 2003)

-Modify tWTR from 2tck to 1tck.

Revision 1.1 (10 Nov. 2003)

-Correct some refresh interval that is not revised.
-Correct some CAS Lantency that is not revised.

Revision 1.2 (12 Jan. 2004)

-Correct IDD1; IDD4R and IDD4W test condition.
-Correct tRCD; tRP unit
-Add tCCD spec.
-Add tDAL spec.

Revision 1.3 (12 Mar. 2004)

-Add Cas Latency=2; 2.5

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004

Revision : 1.3 1/48
ESMT M13S128168A

DDR SDRAM 2M x 16 Bit x 4 Banks

Double Data Rate SDRAM
Features

JEDEC Standard

Internal pipelined double-data-rate architecture, two data access per clock cycle

Bi-directional data strobe (DQS)

On-chip DLL

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Quad bank operation

CAS Latency : 2; 2.5; 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for reads; center-aligned with data for WRITE

Data mask (DM) for write masking only

VDD = 2.375V ~ 2.75V, VDDQ = 2.375V ~ 2.75V

Auto & Self refresh

7.8us refresh interval

SSTL-2 I/O interface

66pin TSOPII package

Operating Frequencies :

PRODUCT NO. MAX FREQ VDD PACKAGE

M13S128168A -5T 200MHz
2.5V TSOPII
M13S128168A -6T 166MHz

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004

Revision : 1.3 2/48
ESMT M13S128168A

Functional Block Diagram

CLK
Clock
CLK Generator Bank D
CKE Bank C
Bank B
Address Row

Row Decoder
Address
Mode Register &
Buffer
Extended Mode & Bank A
Register Refresh
Counter

Sense Amplifier
DM
Command Decoder

Column
CS
Address Column Decoder
Control Logic

Buffer
RAS

Input & Output

&

Latch Circuit
CAS Refresh

Buffer
Counter
Data Control Circuit
WE DQ

CLK, CLK DLL DQS DQS

Pin Arrangement

x16 x16
VDD 1 66 VSS
DQ 0 2 65 DQ15
VDDQ 3 64 VSSQ
DQ 1 4 63 DQ14
DQ 2 5 62 DQ13
VSSQ 6 61 VDDQ
DQ 3 7 60 DQ12
DQ 4 8 59 DQ11
VDDQ 9 58 VSSQ
DQ 5
DQ 6
10
11
66 PIN TSOP(II) 57
56
DQ10
DQ 9
VSSQ
DQ 7
12 (400mil x 875mil) 55 VDDQ
13 54 DQ 8
NC 14 (0.65 mm PIN PITCH) 53 NC
VDDQ 15 52 VSSQ
LDQS 16 51 UDQS
NC 17 50 NC
VDD 18 49 VREF
NC 19 48 VSS
LDM 20 47 UDM
WE 21 46 CLK
CAS 22 45 CLK
RAS 23 44 CKE
CS 24 43 NC
NC 25 42 NC
BA0 26 41 A11
BA1 27 40 A9
A10/AP 28 39 A8
A0 29 38 A7
A1 30 37 A6
A2 31 36 A5
A3 32 35 A4
VDD 33 34 VSS

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004

Revision : 1.3 3/48
 MP7720
20W Class D Mono
Single Ended Audio Amplifier
Monolithic Power Systems
PRELIMINARY INFORMATION

General Description Features

The MP7720 is a mono 20W Class-D Audio ƒ 20W output at VDD=24V into a 4Ω load
Amplifier. It is one of MPS’ second generation ƒ THD+N = 0.04% @ 1W, 8Ω
of fully integrated audio amplifiers which ƒ 93% efficiency at 20W
dramatically reduces solution size by ƒ Low noise (190µV typical)
integrating the following: ƒ Switching Frequency to 1MHz
ƒ 9.5V to 24V operation from single supply
ƒ 180mΩ power MOSFETs
ƒ Integrated Start Up and Shut Down
ƒ Start up / shut down pop elimination
Pop Elimination Circuit
ƒ Short circuit protection circuits
ƒ Thermal protection
ƒ Mute / Stand By
ƒ Integrated 180mΩ switches
The MP7720 utilizes a single ended output ƒ Mute / Standby-mode (Sleep)
structure capable of delivering 20W into 4Ω ƒ Tiny 8 Pin SOIC or PDIP Package
speakers. MPS Class-D Audio Amplifiers ƒ Evaluation Board Available
exhibit the high fidelity of a Class A/B amplifier
at efficiencies greater than 90%. The circuit is Applications
based on the MPS’ proprietary variable ƒ Surround Sound DVD Systems
frequency topology that delivers excellent ƒ Televisions
PSRR, fast response time and operates on a ƒ Flat Panel Monitors
single power supply. ƒ Multimedia computers
ƒ Home stereo
Ordering Information
Part Number ∗ Package Temperature
MP7720DS SOIC8 -40°C to + 85°C
MP7720DP PDIP8 -40°C to + 85°C
EV0030 Evaluation Board
∗ For Tape & Reel use suffix - Z (e.g. MP7720DS-Z)
∗ For Lead Free use suffix - LF (e.g. MP7720DS-LF)
20

VDD 10

7.5V to 24V
5

VDD
ON 2
EN
OFF 8Ω
PGND
PIN
1 4Ω
NIN BS %
0.5

AGND
0.2
SW
0.1

0.05

0.02

Audio 0.01
60m 100m 200m 500m 1 2 5 10 20 30
Input W

4 Ω or 8 Ω
Figure 2: THD+N vs. Power (24V, 1KHz)

Figure 1: Typical Application Circuit

MP7720 Rev 1.5 06/17/04 www.monolithicpower.com 1

 MP7720
20W Class D Mono
Single Ended Audio Amplifier
Monolithic Power Systems
PRELIMINARY INFORMATION

Absolute Maximum Ratings (Note 1) Recommended Operating Conditions (Note 2)

Supply Voltage VDD 26V Supply Voltage VDD 9.5V to 24V
BS Voltage VSW-0.3V to VSW+6.5V Operating Temperature TA -40°C to 85°C
Enable Voltage VEN -0.3V to 6V
VSW, VPIN, VNIN -1V to VDD+1V Package Thermal Characteristics
AGND to PGND -0.3V to 0.3V Thermal Resistance ΘJA (SOIC8) 105°C/W
Junction Temperature 150°C Thermal Resistance ΘJC (SOIC8) 50°C/W
Lead Temperature 260°C Thermal Resistance ΘJA (PDIP8) 95°C/W
Storage Temperature -65°C to 150°C Thermal Resistance ΘJC (PDIP8) 55°C/W

Table 1: Electrical Characteristics (VDD=24V, VEN=5V, TA=25°C)

Parameters Condition Typ Max Units
Supply Current
Standby Current VEN = 0V 1 5 µA
Quiescent Current 1.5 3.0 mA
Output Drivers
SW On Resistance Sourcing and Sinking 0.18 Ω
Short Circuit Current Sourcing and Sinking 5.0 A
Inputs
PIN, NIN Input Common Mode VDD
0 VDD-1.5 V
Voltage Range 2
PIN, NIN Input Current VPIN=VNIN=12V 1 5 µA
VEN Rising 1.4 2.0 V
EN Enable Threshold Voltage
VEN Falling 0.4 1.2 V
EN Enable Input Current VEN = 5V 1 µA
Thermal Shutdown
Thermal Shutdown Trip Point TJ Rising 150 °C
Thermal Shutdown Hysteresis 30 °C

Table 2: Operating Specifications (Circuit of Figure 3, VDD=24V, VEN=5V, TA=25°C)

Standby Current VEN = 0V 130 µA
Quiescent Current 13 mA
f=1KHz, THD+N = 10% , 4Ω Load 20 W
Power Output
f=1KHz, THD+N = 10% , 8Ω Load 10 W
POUT=1W, f=1KHz, 4Ω Load 0.08 %
THD+ Noise
POUT=1W, f=1KHz, 8Ω Load 0.04 %
f =1KHz, POUT=1W, 4Ω Load 90 %
Efficiency
f =1KHz, POUT=1W, 8Ω Load 95 %
Maximum Power Bandwidth 20 KHz
Dynamic Range 93 dB
Noise Floor A-Weighted 190 µV
Power Supply Rejection f=1KHz 60 dB
Note 1. Exceeding these ratings may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.

MP7720 Rev 1.5 06/17/04 www.monolithicpower.com 2

 MP7720
20W Class D Mono
Single Ended Audio Amplifier
Monolithic Power Systems
PRELIMINARY INFORMATION

VDD
C6 9.5 to 24V
R3 VDD 470µF, 35V
ON C5
100KΩ EN
OFF 1µF, 35V
C3, 5.6nF PGND
PIN
MP7720 C7, 0.1µF C9
R2 NIN BS 1000µF
D2, 6.2V
100KΩ 25V
AGND L1, 10µH
C2 SW
4.7µF, C8
16V D1 0.47µF
R6 1A, 30V 50V Metal
Audio Input 10KΩ RL
R4, 82KΩ 4Ω

C1 R1, 10KΩ C4 R5
C10
1µF, 16V 10pF 390pF 10kΩ

Figure 3: 20W Mono Typical Application Circuit

MP7720 Rev 1.5 06/17/04 www.monolithicpower.com 3

 Product Specification of PDP Module

0. Warnings and Cautions

9 WARNING indicates hazards that may lead to death or injury if ignored.
9 CAUTION indicates hazards that may lead to injury or damage to property if ignored.

WARNING
1) This product uses a high voltage (450 V max.). Do not touch the circuitry of this product with your hands when
power is supplied to the product or immediately after turning off the power. Be sure to confirm that the voltage
is dropped to a sufficiently low level.
2) Do not supply a voltage higher than that specified to this product. This may damage the product and may cause a
fire.
3) Do not use this product in locations where the humidity is extremely high, where it may be splashed with water,
or where flammable materials surround it. Do not install or use the product in a location that does no satisfy the
specified environmental conditions. This may damage the product and may cause a fire.
4) If a foreign substance (such as water, metal, or liquid) gets inside the product, immediately turn off the power.
Continuing to use the products it may cause fire or electric shock.
5) If the product emits smoke, an abnormal smell, or makes an abnormal sound, immediately turn off the power. If
noting is displayed or if the display goes out during use, immediately turn off the power. Continuing to use the
product as it is may cause fire or electric shock.
6) Do not disconnect or connect the connector while power to the product is on. It takes some time for the voltage
to drop to a sufficiently low level after the power has been turned off. Confirm that the voltage has dropped to a
safe level before disconnecting or connecting the connector. Otherwise, this may cause fire, electric shock, or
malfunction.
7) Do not pull out or insert the power cable from/to an outlet with wet hands. It may cause electric shock.
8) Do not damage or modify the power cable. It may cause fire or electric shock.
9) If the power cable is damaged, or if the connector is loose, do not use the product; otherwise, this can lead to fire
or electric shock.
10) If the power connector or the connector of the power cable becomes dirty or dusty, wipe it with a dry cloth.
Otherwise, this can lead to fire.
 Product Specification of PDP Module

‰ USE
1) Because this product uses a high voltage, connecting or disconnecting the connectors while power is supplied to
the product may cause malfunctioning. Never connect or disconnect the connectors while the power is on.
Immediately after power has been turned off, a residual voltage remains in the product. Be sure to confirm that
the voltage has dropped to a sufficiently low level.

2) Watching the display for a long time can tire the eyes. Take a break at appropriate intervals.

3) PDP ’s brightness and contrast ratio is lower than that of the CRT. The picture is dimmer with surrounding light
and better for viewing in dark condition.

4) Do not cover or wrap the product with a cloth or other covering while power is supplied to the product.

5) Before turning on power to the product, check the wiring of the product and confirm that the supply voltage is
within the rated voltage range. If the wiring is wrong or if a voltage outside the rated range is applied, the
product may malfunction or be damaged.

6) Do not store this product in a location where temperature and humidity are high. This may cause the product to
malfunction. Because this product uses a discharge phenomenon, it may take time to light (operation may be
delayed) when the product is used after it has been stored for a long time. In this case, it is recommended to light
all cells for about 2hours (aging).

7) If the glass surface of the display becomes dirty, wipe it with a soft cloth moistened with a neutral detergent. Do
not use acidic or alkaline liquids, or organic solvents.

8) Do not tilt or turn upside down while the module package is carried, the product may be damaged.

9) This product is made from various materials such as glass, metal, and plastic. When discarding it, be sure to
contact a professional waste disposal operator.

‰ Repair and Maintenance

Because this product combines the display panel and driver circuits in a single module, it cannot be repaired or
maintained at user’s office or plant. Arrangements for maintenance and repair will be determined later
 Product Specification of PDP Module

1. GENERAL DESCRIPTION

‰ DESCRIPTION
The PDP42V6#### is a 42-inch 16:9 color plasma display module with resolution of 852(H) × 480(V) pixels.
This is the display device which offers vivid colors with adopting AC plasma technology by LG Electronics Inc.

‰ FEARURES
High peak brightness (1000cd/m2 Typical) and high contrast ratio (3000:1 Typical) enables user to create
high performance PDP SETs.

‰ APPLICATIONS
9 Public information display
9 Video conference systems
9 Education and training systems
 Product Specification of PDP Module

‰ ELECTRICAL INTERFACE OF PLASMA DISPLAY

The PDP42V6#### requires only 8bits of digital video signals for each RGB color.
In addition to the video signals, six different DC voltages are required to operate the display.
The PDP42V6#### is equipped with P-CUBE function which analyzes display signals to optimize system
control factor for showing the best display performance.

‰ GENERAL SPECFICATIONS
9 Model Name : PDP42V6#### (42V6#### Model)
9 Number of Pixels : 852(H) × 480(V) (1pixel=3 RGB cells)
9 Pixel Pitch : 1080㎛ (H) × 1080㎛ (V)
9 Cell Pitch : 367㎛ (H) × 1080㎛ (V) (Green Cell basis)
9 Display Area : 920.1(H) × 518.4(V) ±0.5mm
9 Outline Dimension : 1005(H) × 597(V) × 61(D)±1mm
9 Pixel Type : RGB Closed type
9 Number of Gradations : (R)256 × (G)256 × (B)256 (16.7 Mega colors)
9 Weight : 14.8 Kg ± 0.5 Kg (Net 1EA)
111 Kg ± 5 Kg (5EA/1BOX)
9 Aspect Ratio : 16:9
9 Peak Brightness : Typical 1000cd/㎡ (1/25 White Window)
9 Contrast Ratio : Average 60:1 (In a bright room with 150Lux at center)
: Typical 3000:1 (In a dark room 1/25 White Window pattern at center)
9 Power Consumption : Typical 220 W (Full White)
9 Life-time : more than 60,000 Hours of continuous operation
☞ Life-time is defined as the time when the brightness level becomes half of its initial value.

9 Display Dot Diagram

1st 2nd 851th 852th

pixel pixel pixel pixel
column column column column pixel
Pixel Pitch(width) Cell pitch R:0.338㎜
1.080㎜ G:0.367㎜
B:0.374㎜ cell

1st pixel R G B R G B R G B R G B
row
pitch(height)

2nd pixel
row R G B R G B R G B R G B
3rd pixel
row R G B R G B R G B R G B
1.080㎜

479th pixel R G B R G B R G B R G B
row
480th pixel
row R G B R G B R G B R G B
 Product Specification of PDP Module

7. CONNECTORS and CONNECTIONS

‰ Power Input Connector
¾ Connector P3001 Pin Assignment
Pin No. Symbol Pin No. Symbol
1 Vs 5 GND
8 7 6 5 4 3 2 1
2 Vs 6 Va

3 nc 7 GND 1-1123723-8 Pin numbers

(Top View, viewed from the pin connection side)
4 GND 8 +5V
9 Module side connector : 1-1123723-8 (Header)
9 Mating Connector : 1-1123722-8 (Housing)
9 Connector Supplier : AMP

¾ Connector P2005 Pin Assignment

Pin No. Symbol
1 VS
2 VS
3 VS
4 nc
Pin No. Symbol
6 GND
7 GND
8 GND
9 nc

5 GND 10 nc

9 Module side connector : 1-1123723-10 (Header)

9 Mating Connector : 1-1123722 –10 (Housing)
9 Connector Supplier : AMP

10 9 8 7 6 5 4 3 2 1

1-1123723-10 Pin numbers

(Top View, viewed from the pin connection side)

¾ Connector P2006 Pin Assignment

Pin No. Symbol Pin No. Symbol
4 3 2 1
1 GND 3 5V

2 GND 4 5V 1-1123723-4 Pin numbers

(Top View, viewed from the pin connection side)
9 Module side connector : 1-1123723-4 (Header)
9 Mating Connector : 1-1123722-4 (Housing)
9 Connector Supplier : AMP
¨ Pin Assignment Product Specification of Power Supply Unit

8. Input/Output pin assignment & specification

10 9 8 7 6 5 4 3 2 1
CN808 CN805 CN807
CN806
1
2
#1 ~ #4 4 3 2 1 8 7 6 5 4 3 2 1
3 : +5Vctrl #1 : Va
4
#5 ~ #8 #1 : Vs
5 #1 ~#2 #2 : Va #2 : Vs
6 : GND : 5Vctrl #3 : GND
7 #3 : NC
8 #3 ~ #4 #4 : GND #4 : GND
: GND #5 : GND
#1 : 9Vsc #5 : GND
CN804 #2 : 9Vsc #6 : GND #6 : Va
1 #3 : GND #7 : NC #7 : GND
2 #4 : 5Vsc #8 : Vs #8 : +5V
3 #9 : Vs
4 #5 : 5Vsc
5
#6 : 5Vsc #10 : Vs
6
7 #7 : GND
8
9 #8 : GND
#9 : GND
CN803 Location No. Specification Vendor
1 CN01 3-176976-2(Red) AMP
2
3 #1 ~ #3 : 5Vsc
4
5 #4 ~ #6 : GND CN02 3-176976-1(Natural) AMP
6 #7, #8 : 12Vsc
7
8 #9, #10 : GND CN03 3-176976-1(Natural) AMP
9
10 #11, #12 : NC
11
12
CN801 171825-7 AMP
CN802 171825-4 AMP
CN809 CN803 1-171825-2 AMP
1 #1 : 9Vsc
#2: GND CN804 171825-9 AMP
2

Selection S/W CN805 1-1123723-4 AMP

CN802 #1 ~#2
1
: 30V or 24V CN806 1-1123723-0 AMP
2 #3 ~ #4
3
4 : GND 24V 30V CN807 1-1123723-8 AMP

#1 : ACD CN808 171825-8 AMP

CN801
#2 : RLY ON
1
2 #3 : 5Vst_by CN809 171825-2 AMP
3 #4 : GND
4
5 #5 : Vs ON * PSU operation method S/W
6
7 #6 : 5VD
#7 : NC 1 2 Auto : Automatic On/Off
without Vsc B/D
Normal : On/Off with Vsc B/D
CN01 CN02 CN03
1 2
Live Live
1
1

From inlet
Neutral Neutral
2
2

Before connecting with S/W After connecting with S/W

¨ Adjustment detail Product Specification of Power Supply Unit

9. Adjustment detail

10 9 8 7 6 5 4 3 2 1
CN808 CN805 CN807
CN806
1 4 3 2 1
2 8 7 6 5 4 3 2 1
3
4
5
6 Vs adj.
7
8
* Vs Voltage Variabe Resistor
- Turn right, increase Voltage
CN804 Turn left, decrease Voltage
1
2
3
4
5
6 Selection S/W
7
8 Va adj.
9
* Va Voltage Variabe Resistor
CN803 24V 30V - Turn right, increase Voltage
1 Turn left, decrease Voltage
2
3
4
5
6
7
8
9
10
11
12
* You can select output Audio Voltage(24V or 30V)

CN809
1 Selection S/W
2

CN802 Normal Auto

1
2
(Mode1) (Mode2)
3
4 * PSU driving method S/W
Auto(Mode2) : Driving without
CN801 1 2 interface B/D
1
2
3
4
Normal(Mode1) : Driving with interface B/D
5
6
7

* Connect with S/W Cable * Connect with S/W Cable

* Connect with Noisefilter Cable
CN02 CN03
1 2 Live Live
1

Neutral Neutral
2

CN01

※ The color of CN01 is red.(The color of CN02, CN03 are natural.)

 Product Specification of PDP Module

8. LABEL
‰ LABEL Sticking Position

Coner Plate

E/X Tube
ⓐ ⓑ ⓒ ⓓ ⓔ ⓕ
P/N
ⓖ 3211QKE008A

(carved)

Y-SUS Z - SUS

CONTROLLER
Signal Input
(R,G,B,H/Vsync.)
X left X right

‰ Identification Label : LABEL ⓐ

7.0 ㎝

②
2.5 ㎝
③ ⑦

④ ⑤ ⑥
① Model Name
② Bar Code (Code 128, Contains the manufacture No.)
③ Manufacture No.
④ The trade name of LG Electronics
⑤ Manufactured date (Year & Month)
⑥ Manufactured place
Trouble Shooting Manual of PDP Module

- Introduction
- Precautions
- Basic
- Trouble shooting
1. Introduction
COMPOSITION OF PDP BOARDS

42” V6 MODEL. PSU

Y-DRIVE
TOP Z-SUS B/D

Y-SUS
B/D

IPM
IPM

Y-DRIVE
BOTTOM

X-RIGHT B/D
COF CONTROL B/D
X-LEFT B/D COF
1. Introduction

Definitions

■ Definition of MODULE position

long 1
* Back side of module

Exhaust
hole short 1
long 2 short 2

COF long2-1 •••••••• COF long 2-7

■ Identification label

① 6#### ① Model Name

② Bar Code (Code 128, Contains the manufacture No.)
② ③ Manufacture No.
③ 402K242V6000266.ASLGA ⑦
④ The trade name of LG Electronics
2004.02 ⑤ Manufactured date (Year & Month)
④ ⑤ ⑥ ⑥ The place Origin
⑦ Model Suffix
1. Introduction
■ Voltage label (Attached on back side of module)

Vsetup -Vy Vsc

■ Part No. label (Attached on board) BOARD ASS`Y
PART NO.

BOARD NAME

BOARD SERIAL NO.

PCB PART NO.

■ COF serial No. label (attached on COF)

COF SERIAL NO.
1. Introduction
■ Terms of defect

Term Appearance

Add short (line on)

Add open (line off)

Sus short (line on)

Sus open (line off)

8 /40
2. Precaution

Safety precautions

Be sure to read this before service. When using/ handling this PDP module, Please pay attention to the
below warning and cautions.
1. Before repairing there must be a preparation for 10 min.
2. Do not impress a voltage that higher than represented on the product.
3. Since PDP module uses high voltages, Be careful a electric shock
and after removing power some current remains in drive circuit.
so you can touch circuit after 1 min.
4. Drive circuits must be protected from static electricity.
5. The PDP module must be Moved by two man.
6. Be careful with short circuit of PDP boards when measuring any voltages.

Before request service

1. Check panel surface and appearance of B/D.

2. Check the model label. Whether it is boards of same model with label.
3. Before requesting Service, please inform us a detail defect phenomenon and history of module.
it can be helpful to us for a smooth sevice.
Ex) COF long 2-1 fail ,address 1 line open, Y b/d problem , mis-discharge.

9 /40
2. Precaution
Handle with care (COF)
COF is the most important component in the PDP module.
Even a little imperfection of COF can make a serious screen problem.

SCRATCHING TEARING BEING PUSHED

BENDING CHOPING
3. Basic
1. X B/D
: receiving LOGIC signal from CONTROL B/D and make ADDRESS
PULSE(generates Address discharge)by ON/OFF operation,
and supplies this waveform to COF(data) Signal part Power part

X LEFT B/D X RIGHT B/D

<COF Separating>

Lift up lock as shown Pull COF

in narrow. as shown in narrow.
 3. Basic

2. Z sustain B/D
: make SUSTAIN PULSE and ERASE PULSE that generates
SUSTAIN discharge in panel by receiving LOGIC signal from
CONTROL B/D.
this waveform is supplied to panel through FPC(Z).
*composed with IPM,FET,DIODE, electrolytic capacitor ,E/R coil.

* IPM (Intelligent Power Module)

<FPC Separating> E/R(Energy recovery)

Separate the fixed Screw of Z-Board. Condition in Lock part is pulled Pull FPC Connector
Pull out Lock as shown in arrow. as shown in arrow.

12 /40
3. Basic

3. Y drive B/D

1) This is a path to supply SUSTAIN ,RESET waveform which made

from Y SUSTAIN B/D to panel through SCAN DRIVER IC.

2) Supply a wave form that select Horizontal electrode (Y SUSTAIN electrode)

sequentially.
- potential difference is 0V between GND and Vpp of DRIVER IC
in SUSTAIN period.
- being generated potential difference between GND and Vpp only
in SCAN period.

* In case of 42” V6 use DRIVER IC IC 8 EA (TOP, BOTTOM: each 4EA)

13 /40
3. Basic

4. Y sustain B/D
: generates SUSTAIN,RESET waveform, Vsc(SCAN)voltage.
and supplies it Y DRIVER B/D.
* Composed with IPM,DIODE, electrolytic capacitor ,FET.

5. Control Board
: creates signal processing (Contour noise,reduction ISM,..)
and an order of many FET on/off of each DRIVER B/D with
R,G,B each 8bit input.
* Use 3.3V/5V 2 kinds of power .

14 /40
3. Basic

DC/DC con.
6. DC/DC Converter part part
: Being impressed 5V, Va ,Vs,
DC/DC converter makes
5V,Va,Vs,Vset_up,Vsc
which is essential for each B/D.
There is no DC/DC B/D in
model 40 〞 /42 〞(1 POWER B/D).
* 50 〞 60 〞embedded DC/DC B/D
separately because of high power
consumption.

15 /40
3. Basic

7. FPC (Flexible Printed Circuit)

: supply a driving waveform to PANEL by connecting a PAD
electrode of PANEL with PCB(Y and Z).
* there is two type of this for Y B/D. One is single-sided,
another is double-side. These are having pattern on it
* for Z B/D, there is no pattern , single-sided, and Beta
type(all of copper surface).

8. FFC (Flat Flexible Cable)

: for connecting a Logic signal between B/D and B/D.
*There is 0.5mm pitch,50pin type
1mm pitch ,30pin type.

16 /40
3. Basic

9. COF (Chip On Film)

: supply a waveform which made from X B/D to panel and select
a output pin that is controlled by COF when be on or off.
96 output pin per IC.
─ the more the resolution higher, the less spare space where
can set IC on it in B/D. without using IC PACKAGE,
we can use a BARE IC , so we can get IC with LOW COST
─ because we do not solder IC on PCB directly,
a soldering defect rate decrease.
* composition Bare IC
1) FPC + Heat /Sink
⇒ FPC for COF must have a Low Spec decline with getting damp
2) CHIP resistor + CHIP CAPACITOR
* 42 V6 COF is the same as 42V5.
3) BARE IC (STV7610A/WAF) + GOLD WIRE/AL WIRE
4) EPOXY MOLDING
3. Basic

10. IPM(Intelligent Power Module)

: composition
HEATSINK,CAPACITOR
DIODE
IC LINEAR
RESISTORTANSISTOR,FETS.
: description
Attached at Z B/D and Y B/D, make Sustain waveform.
Sustainer : supply a square wave to panel to make a video.

IPM

18 /40
4. Trouble shooting.

what kind of
Fast check updefect?

defect
Check model No. of module ,all connectors and cables.

No display? Check panel appearance Check PSU output (Va,Vs,5v) Check Y, Z b/dinput voltage

Replace ctrl b/d Replace Y, Z b/d

vertical defect? Check panel appearance Check COF Replace X b/d Replace ctrl b/d

Horizontal defect? Check FPC Replace Y drv b/d Replace Y sus b/d Replace ctrl b/d

Mis –discharge Replace ctrl b/d

Replace Y drv b/d Replace Y sus b/d
on screen?

19 /40
4. Trouble shooting.

what kind
Logical of defect?
judgment

What kind of defect ?

No display? Please follow the no display trouble shooting.

vertical defect? Bar defect appeared? Please follow bar defect trouble shooting.

Line defect
Horizontal defect?

Please follow the line defect trouble shooting.

Mis –discharge
on screen? Please follow the mis discharge trouble shooting.

20 /40
4. Trouble shooting.
No display

Check each section with following method if there is problem, replace or repair that part.
If not go to the next section.

1. Connector
Confirm every Connector (PSU, Y-SUS, CTRL, Z-SUS)
⇒ module may not be normal by mis-connection which can not send signal and power.
Also Mis connection for a long time has a specific b/d failed.

CTRL B/D + Y-SUS CTRL B/D + Z-SUS CTRL B/D + X-B/D Signal input(LVDS)

21 /40
4. Trouble shooting.

2. Exhaust tip Crack

Confirm exhausting Tip and find Crack with naked eyes to check vacuum state.
If there is problem replace the module .
⇒ in case of vacuum breakdown, module makes a shaking noise because of inside gas ventilation.
(there may be a small crack which could not see with naked eyes. And this noise is different from Capacitor noise. )

NORMAL CRACKED

22 /40
 4. Trouble shooting.
3. PSU(Power Supply Unit)
1. Check each unit part of PSU inside with naked eyes.
(capacitor, FET, a kind of IC, resistor)
2. Check FUSE and SW1 (on Normal).
3. Check Output voltage which is converted from AC V
SW1 Normal
to DC V.
voltage Check (5V, Va, Vs)
※ When PSU Protection occurred. Check Short
between Y-SUS, Z-SUS B/D .

Confirm Adjust Fuse open check

if not same
input voltage voltages

Vs Voltage ADJ Va, 5V(VCC) Voltage ADJ

Multi-meter Touch point (Vs : About 180 ~195 V) ■ Va : About 55 ~65 V
(5V, Va ,Vs must accord with Module Label) ■ 5V(VCC) : 5V~5.5V)
 4. Trouble shooting.

4. Ctrl B/D Diode

1. Confirm LED D17(flashing) ,13 lighting

2. If not CHECK OSC X1 output. Input voltage
3. Check CTRL input voltage
(CONNECTOR P300)
4. CHECK 3.3V, 5V,15V.
5. Check IC 11 3.3V
IC 3 2.5V

OSC(X1)

Probe
Touching
point

Check IC 11,13

DMM +

Check oscillating state. DMM – (GND)

(normal 100 MHZ)
Be careful with physical shock.
 4. Trouble shooting.

5. Y-sus B/D
Vscw
1. Check FUSE [FS1(5v) ,FS2(Vs)]. FS2
2. Check voltages(Vsetup,-Vy, Vscw) Vsetup
3. Check DIODE between GND and Y SUS output. setdn
[SUSUP(OC2) SUSDN(OC1)].
forward=0.4 ,reverse=OVERLOAD.
4. Check whether output voltages agrees
setup
with voltage that represented in label.

-Vy

FS1

25 /40
4. Trouble shooting.

■ Check whether output voltages agrees with voltage that represented in label.

■ Check diode value GND between Y-SUS output.

Normal diode value= 0.4 (forward) Normal diode value = OL (reverse)

 4. Trouble shooting.
6. Z-sus B/D
1. Check the FUSE.
2. Check input voltages.(Va, 5V,15V)
3. Check FPC out put diode value.
4. Check ramp waveform.

■ Check the FUSE ■ Check input voltages

5V FUSE

Va FUSE 6.3A Vs FUSE 2A or 4A

4. Trouble shooting.
■ Variable resistance of Z RAMP

waveform slope.

■ Check FPC output diode value.

caution: check certainly after removing FPC.

Normal diode value=0.375(forward) Normal diode value=OVER LOAD(reverse)

4. Trouble shooting.
◎ Power protection
It is power protection when power is off automatically within 2~3 min. from power on.
Power protection function protect the boards when occurred short on circuits of PDP module or power problem.
If can not impress power even after replacing PSU, find out where the short occurred.

* PSU makers.

DAEGIL PSU UNICON PSU

29 /40
4. Trouble shooting.
Vertical defect (bar)

Check each section with following method if there is problem, replace or repair that part.
If not go to the next section.

1. Connector Check here Bar

Check COF connector.
If not connected well,it will Make a bar defect .

Check here Off

2. Checking COF
Confirm whether COF was torn. And then check input of COF resistor and IC.

COF 6 is torn partly

Tearing

30 /40
4. Trouble shooting.
◎ Checking address COF input of resistor and IC
■ COF resistor checking

Check the both side of resistor With Digital multi meter(DMM) .

If the resistor is normal, the resistor value will be 10.2 ~ 10.8 Ω
But if not, the value will be 0 or infinity and replace the resistor.

31 /40
4. Trouble shooting.
◎ Checking address COF input of resistor and IC
■ IC input checking

Inside of IC , there is 4 ea diodes which separated in 2 series .

(input 2, output 2)
*how to check
1.contact DMM - terminal to a right terminal of condenser(GND)
and DMM + terminal to a right terminal of IC, normal value 0.66 (fig.1)
2.contact DMM - terminal to Output terminal of resistor, and
DMM + terminal to a right terminal of IC , normal value 0.73 (fig.2)

Fig. 1 Fig. 2

DMM(- terminal) ` DMM (+ terminal)

DMM (- terminal)
DMM( + terminal)
4. Trouble shooting.

3. Ctrl B/D
CTRL B/D supplies video signal to COF. So if there is a bar defect on screen,
It may be the ctrl b/d problem.

<Diagram of ctrl b/d>

A flow of address signal
In this figure, we can easily suppose
what will be appeared on screen when a specific part failed. MCM

Buffer
IC

Array저항

각각 16 line

COF IC1 COF IC2 COF IC3 COF IC4

96 output
4. Trouble shooting.
Vertical defect (line)

In case of 1 line open or short , check foreign substances in COF connector.

First blow up foreign substances with your mouth. And then if the same line appears, replace the panel.

1 line open or short

This phenomenon is due to COF IC inside short or adherence part of the Film and rear panel electrode problem.
In this case, replace the panel.

1 line open
1 electrode open

Line open or short with same distance.

This is MCM of Ctrl b/d defect. MCM can not be replaced separately. So replace the ctrl b/d.

MCM (Multi Chip Module)

4. Trouble shooting.

line defect from each parts

• Case 1: Buffer IC fail 16 line open
COF IC 1,2 ⇒ 192 line(96+96) open.
COF IC 3,4 ⇒ 64 line open (with fixed interval there is on,off ……. Repetition)

• case 2 : Array resistor fail

COF IC1 ⇒ 16 line , COF IC2 ⇒ 16 line open

• case3 : COF IC fail

96 line open
96 line open.

/40
4. Trouble shooting.
Horizontal (bar)

Most horizontal defects can be repaired. In case of adherence part of the Film and rear panel
electrode defect or panel electrode open,short , replace the panel.

1. Connector
It can make a horizontal bar that connector on Y b/d and Z b/d did not plugged well. Because sustain voltage
can not be supplied to panel. So check connectors (FPC, Y drv –Y drv) first.

Horizontal bar
Disconnected

Disconnected
Screen off
4. Trouble shooting.

2. Scan IC check
Check diode value of the right side part of output pin.

Normal diode value. (in case of Panasonic IC=1.035) Defect diode value= 0.018
* It can be different from each IC Maker. (in case of TI IC= 0.6~0.7)
Check here with DMM(either forward or reverse is ok)
DMM + DMM -

37 /40
4. Trouble shooting.

Horizontal (line)

1. Check FPC
In case of horizontal 1 or more line, it is due to FPC or panel inside .
ctrl b/d, Y b/d is just normal.

FPC electrode open

Panel electrode
Insulation break down
Horizontal 1 line.

2. Check scan IC
Check with same method that presented in Horizontal (bar).

38 /40
4. Trouble shooting.
◎ How to check IPM

Forward : test 1 GND(＋) , Sus-out(－)

2 Sus-out(＋),Vs(－)
3 ER-DN(－),ER-COM(＋)
4 ER-COM(－),ER-UP(＋)

when each 4 TEST Diode value is over 0.4V => OK

Reverse : test 1 GND(－) , Sus-out(＋)

2 Sus-out(－),Vs(＋)
3 ER-DN(＋),ER-COM(－)
4 ER-COM(＋),ER-UP(－)

when each 4 nodes TEST Diode value is infinity => OK

※ Specially, the value of ER-UP,COM,DN in the Y/Z board, should be

checked all of them. but, the terminal of Vs,Sus-out,GND,
we must aware to know after check one of IPM because it is parallel.
Æ if no problems, check 15V(Y,Z B/D) with GND, Î Forward value 0.3V,
Reverse value infinite. If no problems,

40 /40
 Product Specification of PDP Module

CAUTION
‰ General
1) Do not place this product in a location that is subject to heavy vibration, or on an unstable surface such as an
inclined surface. The product may fall off or fall over, causing injuries.

2) When moving the product, be sure to turn off the power and disconnect all the cables. While moving the
product, watch your step. The product may be dropped or fall, leading to injuries of electric shock.

3) Do not place this product in a location that is subject to heavy vibration, or on an unstable surface such as an
inclined surface. The product may fall off or fall over, causing injuries.

4) Before disconnecting cable from the product, be sure to turn off the power. Be sure to hold the connector when
disconnecting cables. Pulling a cable with excessive force may cause the core of the cable to be exposed or
break the cable, and this can lead to fire or electric shock.

5) This product should be moved by two or more persons. If one person attempts to carry this product alone, he/she
may be injured.

6) This product contains glass. The glass may break, causing injuries, if shock, vibration, heat, or distortion is
applied to the product.

7) The temperature of the glass surface of the display may rise to 80°C or more depending on the conditions of use.
If you touch the glass inadvertently, you may be burned.

8) Do not poke or strike the glass surface of the display with a hard object. The glass may break or be scratched. If
the glass breaks, you may be injured.

9) If you glass surface of the display breaks or is scratched, do not touch the broken pieces or the scratches with
bare hands. You may be injured.

10) Do not place an object on the glass surface of the display. The glass may break or be scratched.
Spare Part List for PDP4210EA

Part Number Part Description Usage Unit

Item / Unit

1 E6205-001003 42” ED PDP Module 1 Piece

2 900-420103-01B 42” Glass Filter 1 piece

3 E7801-100001 Main PCBA 1 set
4 E7801-100002 Audio PCBA 1 set
5 771S42D101-01 ATSC PCBA 1 set
7 771-42D111-01 Control PCBA 1 set
8 771-42D111-02 IR PCBA 1 set
9 E4101-027001 Power Switch 1 piece
10 E4801-116002 Speaker 2 piece
11 E3301-028005 Speaker Terminal (without cable) 1 piece
12 E3404-157004 AC Power Cord 1 piece
13 E3421-926080 LVDS Cable 1 piece
14 E3421-925049 Connection Cable 1 1 piece
15 E3421-926083 Connection Cable 3 1 piece

16 E3421-926084 Connection Cable 4 1 piece

17 E3421-927001 Power Switch Cable 1 1 piece
18 E3421-927002 Power Switch Cable 2 1 piece
19 E3421-926081 Control PCBA Cable 1 piece
20 E3421-926094 IR PCBA Cable 1 piece
21 E7501-051007 Remote Control 1 set
22 E7301-010002 AAA size Battery 1 pair
Spare Part List for PDP4210EA

Part Number Part Description Usage Unit

Item / Unit

23 200-42D131-MTK02AV Front Plastic Frame 1 piece

24 277-42D101-01S Function Knob 1 piece
25 263-42D101-01S Power Lens 1 piece
26 269-42D101-01L IR Lens 1 piece
27 481-42D107-01S PCBA Shield Box 1 piece
28 483-42D103-01 PCBA Shield Top Cover 1 piece
29 436-42D118-01S Terminal Frame 1 piece
30 402-42D114-01S Metal Back Cover 1 piece
31 423-42D11E-01S Power Switch Metal Frame 1 piece
32 510-42D101-MTU02K Top Carton Box 1 piece
33 511-42D111-01K Bottom Carton Box 1 piece
34 300-42D106-02C Top Cushion 1 piece
35 300-42D105-02C Bottom Cushion 1 piece
36 244-34B811-01 Carton Box Handle 2 piece
37 310-504004-01 Poly bag for Main Unit 1 piece
38 310-111404-07V Poly bag for Instruction Manual 1 piece
39 580-P42AAEM-TU02L Instruction Manual 1 piece
40 388-42SB04-01H Power Socket Plate 1 piece
41 388-42D103-01H Caution Plate 1 piece
42 387-42AA01-MTU02H Model Plate 1 piece
43 388-42SB02-01H Speaker Terminal Plate 1 piece
44 384-42D103-MTU01H Terminal Plate 1 piece
45 590-42AA01-04 Warranty Sheet 1 piece
Spare Part List for PDP4210EA

Part Number Part Description Usage Unit

Item / Unit

46 579-42D102-09 Model Plate Serial Number 1 piece

47 579-42AA01-05 Bar Code Label 1 pair
48 579-42D103-02 ON/OFF Label 1 piece
49 568-P46T02-02 Warning Label 1 piece
50 734-BP0302-01 Duck Feet Stand 1 set
Exploded View
If you forget your V-Chip Password
- Omnipotence V-Chip Password: 8205.

Using the “Change Password” item

When enter the “Parental” menu, select “Change Password”.
Press ▲ or ▼ button to highlight the “Change Password” item.
Press Enter button to confirm and pop up a menu.

Use 0~9 buttons input the omnipotence password(8205), then Press Enter button to enter and
pop up a menu.

Use 0~9 buttons input your new password.

Press ▼ button to move to confirm blank.
Use 0~9 buttons input your new password again.
Press Enter button to confirm
-Suggest: Change to your familiar Password again.
Software upgrade
Process of update MT8205AE

Preparing :
1) Connect RS232-VGA download line, One connector is connected to VGA connect port of
Plasma TV while another side is connected to PC COM port.
2) Store the MtkTool into the PC .

Downloading :
3) Turn on AC power and wait TV entering standby mode, while the color of the power
indicator is Red.
4) Execute MTKtool and select the chipset as MT8205. (the software of MTKtool will be sent to
your side)

5) Select current COM port. (please try to check the COM port of your PC).
6) Choose the bit rate as 115200.
7) Select the update binary by pressing browse button. For exemple,the binary file name is
PDP4210EA_VIORE_XXXXXX_XXXX_VXX.bin. (this update firmware will be sent
to your side)
8) Press Upgrade button and start update process.
9) The update process is successful as the progress bar is 100%. After the update process is ok,
turn off power and wait indicator light is off. Turn on power and TV can work.

Checking
It is needed to check the version of the firmware for MT8205AE which has been
download into the Plasma TV .
Press Menu button of the remote control for a little long time and the OSD menu
for Factory Setting is appeared on the screen .
Use the remote control and select the mode of the Factory Setting then enter the
mode of the Factory Setting .
Use the remote control and select the mode of Firmware Version and then enter the
mode of Firmware Version . It is easy to be found the version of the current firmware
for MT8205AE is as the following : “Firmware Version : VXX ”

Process of update MT5351AG

Preparing :
1) Connect RS232-VGA download line, One connector is connected to VGA connect port of
Plasma TV while another side is connected to PC COM port.
2) Store the MtkTool into the PC

Downloading :
3) Turn on AC power switch of the Plasma TV and then press the button “standby” of the remote
control . The image could be found on the screen of the Plasma TV while the color of the
power indicator is green . (the mode of the Plasma TV will be standby mode if after turn on
the main power switch only . )
4) Execute MTKtool and select the chipset as MT5351AG. (the software of MTKtool will be sent
to your side)
5) Select current COM port. (please try to check the COM port of your PC).

6) Choose the bit rate as 115200.

7) Select the update binary by pressing browse button. For exemple,the binary file name is
 XXXX_PDP4210EA_ATSC_IT_000000XX_X_P.bin. (this update firmware will be sent
to your side)

8) Press Upgrade button and start update process.

9) The update process is successful as the progress bar is 100%. After the update process is ok,
turn off power and wait indicator light is off. Turn on power and TV can work.

Checking :
It is needed to check the version of the firmware for MT5351AG which has been
download into the Plasma TV .
Press Menu button of the remote control and the main OSD menu is appeared on
the screen .
Use the remote control and select the mode of the adjustment .
Use the remote control and select the mode of DTV
Entry the mode of DTV
Input “0000” (zero , zero , zero , zero) of the remote control while the Plsama TV is
under the above condition . Then enter the mode of factory after input the digits .
It is easy to be found the version of the current firmware for MT5351AG is
“XXXX_PDP4210EA_ATSC_IT_000000XX_X_P”under the mode of factory .

PC PDP

RXD 2 11 RXD
RS232-VGA download line TXD 3 4 TXD
GND 5 5 GND

D-Sub 9(RS232) D-Sub 15A(VGA)