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    Types of Processor

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    nirmalendusaha27
    Processor types

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    © All Rights Reserved
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    4 TYPES OF PROCESSORS 4.0 INTRODUCTION Powerful General purpose microprocessors may be divided into two groups i.e., (i) Pure complex instruction set computer (CISC) processors. (ii) Pure reduced instruction set computer (RISC) processors. Examples of CISC processors are the 8086, 80186, 80286 and 80286 belonging to INTEL family and 68000 and 68040 from MOTOROLA family. Please note that 80386 is the last pure CISC model of the Intel family because 80486 has the facility of RISC technology partially. The CISC microprocessors have : @ Complex machine instructions. © Micro-encoding of machine instructions. Best addressing capability. Smaller number of useful registers. Reduced Instruction Set Computer (RISC) have faster clock rates, ranging from 20 to 120 MHz. For example: Intel i860, SPARC, IBM RS/6000 etc. are some of the RISC processors. In this chapter, we shall study all these advanced processors including super scalar processors, very long instruction word (VLIW) and vector processors. 4.1. ADVANCED PROCESSOR TECHNOLOGY By the year 2010 (the year of common wealth games!!!), a single VLSI chip will have more than 1 billion transistors. Pipelining has been used in RISC machines. RISC processors have been succeeded by super scalar processors that execute multiple instructions in one clock cycle. Very Large Instruction word (VLIW) processors are those in which one instruction word encodes more than one operation. As per the Moore’s Law —“The number of transistors which can be integrated in a chip has been doubling every 18 months”. To enhance the speed of PEs we now make use of multithreading, VLIW and vector processors. What we actually observe is that as technology evolves rapidly, the clock rates of PEs also slowly ove from lower to higher speeds. We shall also study about the super pipelined Processors. These computers use multiphase clocks with clock rate ranging from 100 to 500 MHz, Vector computers (to be discussed) use this approach. We should also understand that a scalar processor is different from a vector processor. This is shown in Fig. 4.1 below. a shown in Fig. 4.2 is the working of a vector processor. What we observe from Fig. 1 and Fig. 4.2 is that in case of a scalar processor ~ one-result/many clock cycles is Produced while in case of vector processors one result/clock is produced. 125 @ 128 ADVANCED COMPUTER ARCHITECT p t Herein, 2 phases have been merged. Similarly, F; E) and write lases i.e., Fetch (F) and Decode (D) have bee Y. Bxecy v : Fite-back resul od, But this also results ipelii ack results (W) phases have been merge — ipeline utilization. eae Pog, Please note here that the effective CPI for case I is 1 (ideal pipeline). Whereas cE case I, it is 2 and in case III, it is + (half) only. What we observe here is that 4, ipeli 7 : 2 Pipeline utilization is falling down only and not increasing 4.2 INSTRUCTION-SET ARCHITECTURES One of the important aspects of Computer architecture is the design of the instructi, set for a processor. It is the instruction set chosen for a particular computer that determing the way in which machine language program are constructed. A computer with a larg number of instructions is called as a complex instruction set computer (CISC), 4 computer that uses a few instructions with simple constructs are called as Reduces instruction set computer (RISC). These instructions can be executed at a faster rat within the CPU with minimum memory references 3.3. CISC SCALAR PROCESSOR A scalar processor will execute with a scalar data: Today's scalar processor have bo integer and floating point unit within single CPU. This is shown in Fig. 4.6 below Control unit Fig 4.6 A. CISC architecture, We can use a single chip or many chips to construct a CISC scalar processor. Ples® note that ideally, a CISC scalar processor should have a performance equal to that“! 2 base scalar processor (discussed earlier). However, in CISC machines under pipeliti®$ may oceur due to data dependence, resource conflicts, branches, jumps and other reas For example : VAX 8600, 1486, M68040 are CISC processors. Others include 80 80186 /286 /386, M68000 etc. By convention—CISC architecture (Fig. 4.6) uses a unified cache. A unified holds both instructions and data. So, same bus is used. 44 ‘Risc SCALAR PROCESSORS ‘These processors issue one instructions per cycle, Some of the features of RISC *™ (a) Reduced instruction set. (b) Simpler instructions. (c) Hardwired control unit. (d) Few addressing modes. (e) Instruction pipelining. -ypes OF PROCESSORS 129 For example : Intel i860, M88100, AMD 29000 are some RISC processors. A RISC architecture is shown in Fig. 4.7 Main memory Data cache ee }¢—») Data path Instruction cache Hardwired control unit Fig. 4.7. A RISC architecture. In RISC machines, we have separate instruction (I) and data (D) caches. Say, we want to multiply 2 numbers being stored in a 2D-memory Mbsigant gowigiihs: Main memory a ON o At memory location (2,3) = 5 is stored. At memory location (3,2) is stored. Then, CISC machine will multiply them in one instruction as follows : MULT 2: 3,3:2 Whereas RISC machine will use many instructions as follows : | Load A, 2:3 ; Get First number | Load B, 3:2 ; Get Second number | Prod A, B ; Multiply them ie, A A*B Store 2:3, A ; Move results from A to ; mem. Loc. 2:3 In CISC approach, very little RAM is required to store instruction. The emphasis is on building complex instructions directly into the hardware, But in RISC approach, more RAM is required. 4.5 COMPARISON OF CISC AND RISC IN TABULAR FORM cisc RISC 1. These computers use large set of 1. These computers use small set of instructions. instructions. 2. They support 12-24 addressing modes. 2, They support only 3-5 addressing mode. 130 ADVANCED COMPUTER ARCHIE, m GieThey web S24 yahetal pardons tepisiow |. 3. They use 92-192 CPRS. |] (GPRS). 4. They mostly have a unified cache 4, They use separate (split) data ang i instruction cache ! 5. Clock rates are between 33-50 MHz 5. Clock rates are between 50-150 Miiz | | 6. CPI is between 2 and 15. 6. Average CPI is less than 1.5. 7. It uses micro coded control logic 7, tt uses hardwired control logic. 8. They use variable format instructions i¢.,| 8. They use fixed instruction format je, 16-64 bits per instruction. bits per instruction Eee cen Se 20Ey U8 Examples : SUN SPARC, i860 etc Note : Pentium has features of CISC and RISC, both. 4.6 SUPERSCALAR PROCESSORS A processor in which many instructions are executed concurrently is known as, super scalar processor. These processors exploit more instruction level parallelism (Ip in user programs. The instruction issue degree (m) is limited by this formula : 2

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