ECE 612

Design of Digital Integrated Circuits

Spring 2014
Lecture 7
Modern SRAMs and DRAMs

S. A. Ibrahim
Ain Shams University
ICL
 Outline

 Introduction to Datapath
 Single-bit Addition
 Carry-Ripple Adder
 Carry-Bypass Adder
 Carry-Select Adder
 Carry-Lookahead Adder
 Tree Adder

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Design Abstraction Levels

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 A Generic Digital Processor

MEMORY

INPUT-OUTPUT
CONTROL

DATAPATH

 Arithmetic Unit
 Adders, shifter, multipliers, ..etc.
 Memory
 RAM, ROM, Buffers, Shift Registers, ..etc.
 Control
 Finite State Machines, Counters, ..etc.
 Input-Output
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 Bit-Sliced Design
Control

Bit 3

Data-Out
Mul tipl exer
Bit 2
Data-In

Register

A dder

Shi fter
Bit 1
Bit 0

 Bit slicing is a technique for constructing a processor

from modules of smaller bit width.
 Each of these components processes one bit field or
"slice" of an operand.

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 Single-Bit Addition

A B A B
Half Adder Full Adder
𝑆 = 𝐴⨁𝐵 Cout 𝑆 = 𝐴⨁𝐵⨁𝐶 Cout C
𝐶𝑜𝑢𝑡 = 𝐴𝐵 𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶
S S
(Majority Gate)
A B Cout S A B C Cout S
0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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 Carry-Ripple Adder
 Simplest design: cascade full adders
 Critical path goes from Cin to Cout
 Design full adder to have fast carry delay

A3 B3 A2 B2 A1 B1 A0 B0

Cout Cin
C2 C1 C0


S3 delay linear
Worst case S2 with the
S1 number S
of0 bits t = O(N)
d

tadder = (N-1)tcarry + tsum

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 Full Adder Design I
 Brute force implementation from eqns

𝑆 = 𝐴⨁𝐵⨁𝐶
𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶 (Majority)

A A B B C C

A A

B B
B
C C
A B B
S
C C C A
Cout
B
B B C A
A B B
A A

32 Transistors
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 Full Adder Design II
 Factor S in terms of Cout
𝑆 = 𝐴𝐵𝐶 + (𝐴 + 𝐵 + 𝐶)𝐶𝑜𝑢𝑡
 Critical path is usually C to Cout in ripple adder
VDD
VDD
C A B
A B
A
B
C B
VDD
A
X
C
C A S
C
A B B VDD
A B C A

Co B

28 Transistors
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 Inversion Property

A B A B

Ci FA Co Ci FA Co

S S

S  A B C i  = S A B  Ci 

C o A B C i  = Co A B  Ci 

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 Using Inversions
 Critical path passes through majority gate
 Built from minority + inverter
 Eliminate inverter and use inverting full adder
 This reduces critical path delay

A3 B3 A2 B2 A1 B1 A0 B0

Cout Cin
C2 C1 C0

S3 S2 S1 S0

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 PGD
 For a full adder, define what happens to carries in
terms of A and B
 Propagate:
Cout = C
P=𝐴⊕𝐵 A B C Cout S PGD
0 0 0 0 0 D
 Generate:
0 0 1 0 1 D
Cout = 1 independent of C
0 1 0 0 1 P
G = 𝐴. 𝐵 0 1 1 1 0 P
 Delete: 1 0 0 0 1 P
Cout = 0 independent of C 1 0 1 1 0 P
D = 𝐴 .𝐵 1 1 0 1 0 G
 𝐶𝑜𝑢𝑡 = 𝐺 + 𝑃𝐶 1 1 1 1 1 G

 𝑆 = 𝑃⨁𝐶
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Full Adder Design III: The Mirror Adder
VDD

VDD VDD A

A B B A B C B
Delete
"0"-Propagate A C
Co
C S
A C
"1"-Propagate Generate
A B B A B C A

P=𝐴+𝐵 24 transistors
Used here.

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 Advantages of the Mirror Adder
 The NMOS and PMOS chains are completely symmetrical.
 A maximum of two series transistors can be observed in the carry-
generation circuitry.
 When laying out the cell, the most critical issue is the minimization
of the capacitance at node Co. The reduction of the diffusion
capacitances is particularly important.
 The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell.
 The transistors connected to C are placed closest to the output.
 Only the transistors in the carry stage have to be optimized for
optimal speed. All transistors in the sum stage can be minimal
size.

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 Full Adder Design IV
 Complementary Pass Transistor Logic (CPL)
 Slightly faster, but more area

B C B C
A

B C B C
S Cout
A
B C B C

A
B C B C
S Cout

B
A

34 Transistors
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 Full Adder Design V
 Dual-rail domino
 Very fast, but large and power hungry
 Used in very fast multipliers

 
Cout _h Cout _l
C_h A_h C_l A_l
A_h B_h B_h A_l B_l B_l

S_l  S_h
C_l
C_h C_h

B_l
B_h B_h

A_h A_l

38 Transistors
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 Full Adder Design VI: TG FA
P
P=𝐴⊕𝐵
VDD
VDD Ci 𝑆 = 𝑃⨁𝐶
A
P S Sum Generation
A A P Ci

A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P
 Remember
 G = 𝐴. 𝐵 = 𝐴𝑃
 𝐶𝑜𝑢𝑡 = 𝐺 + 𝑃𝐶
24 Transistors
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 Manchester Carry Chain

VDD
Pi
VDD 
Pi
Ci Co
Gi
Co Gi
Ci

Di
Pi 

𝐶𝑜𝑢𝑡 = 𝐺 + 𝑃𝐶

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 Manchester Carry Chain
VDD

P0 P1 P2 P3
C3

Ci,0
G0 G1 G2 G3

C0 C1 C2 C3

𝐺𝑖 = 𝐴𝑖 𝐵𝑖
𝑃𝑖 = 𝐴𝑖 ⊕ 𝐵𝑖

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 Carry-Bypass Adder (1)

Also called
P0 G0 P1 G1 P2 G2 P3 G3 Carry-Skip
Ci,0 C o,0 C o,1 Co,2 Co,3
FA FA FA FA

P0 G0 P1 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2

Mul tiplexer
FA FA FA FA
Co,3

Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C0, else “kill” or “generate”.

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 Carry-Bypass Adder (2)

Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15

Setup tsetup Setup Setup Setup
tbypass

Carry Carry Carry Carry

propagation propagation propagation propagation

Sum Sum Sum tsum Sum

M bits

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

 Carry-ripple is slow through all N stages.

 Carry-skip allows carry to skip over groups of M bits.
 Decision based on M-bit propagate signal.

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Carry Ripple versus Carry Bypass

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 Carry-Select Adder
Setup

P,G

"0" "0" Carry Propagation

"1" "1" Carry Propagation

Co,k-1 Multiplexer Co,k+3

Carry Vector

Sum Generation

 Trick for critical paths dependent on late input X

 Precompute two possible outputs for X = 0, 1
 Select proper output when X arrives
 Carry-select adder precomputes n-bit sums
 For both possible carries into n-bit group
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 Carry-Select Adder: Critical Path

Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15

Setup Setup Setup Setup

0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry

Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7 Co,11 Co,15

Sum Generation Sum Generation Sum Generation Sum Generation

S0–3 S4–7 S8–11 S12–15

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Linear Carry-Select Adder

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 Square Root Carry-Select Adder

M bits

P stages

𝑡𝑎𝑑𝑑𝑒𝑟 = 𝑡𝑠𝑒𝑡𝑢𝑝 +𝑀𝑡𝑐𝑎𝑟𝑟𝑦 +𝑃𝑡𝑀𝑈𝑋 +𝑡𝑠𝑢𝑚

𝑁 = 𝑀 + 𝑀 + 1 + 𝑀 + 2 + … + (𝑀 + 𝑃 − 1)
𝑃 𝑃−1 𝑃2 1 𝑃2
𝑁 = 𝑀𝑃 + = +𝑃 𝑀− ≈ 𝑖𝑓 𝑀 ≪ 𝑁
2 2 2 2
𝒕𝒂𝒅𝒅𝒆𝒓 = 𝒕𝒔𝒆𝒕𝒖𝒑 +𝑴𝒕𝒄𝒂𝒓𝒓𝒚 + 𝟐𝑵𝒕𝑴𝑼𝑿 +𝒕𝒔𝒖𝒎
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Carry Ripple vs. Carry Select

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Carry-Lookahead Adder (1)

(Another definition for P)

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Carry-Lookahead Adder (2)

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Logarithmic Lookahead

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 Carry-Lookahead Trees

Co  0 = G0 + P0 Ci  0
C o 1 = G1 + P1 G0 + P1 P0 Ci 0
C o 2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C i 0
=  G2 + P2 G1 +  P2 P1   G0 + P0 Ci  0  = G 2:1 + P2:1 C o 0

Can continue building the tree hierarchically.

 If lookahead is good, lookahead across

lookahead!
 Recursive lookahead gives O(log N) delay
 Many variations on tree adders
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 Generate Propagate Notations

• Equations often factored into G and P

• Generate and propagate for groups spanning i:j

𝐺𝑖:𝑗 = 𝐺𝑖:𝑘 + 𝑃𝑖:𝑘 𝐺𝑘−1:𝑗

𝑃𝑖:𝑗 = 𝑃𝑖:𝑘 𝑃𝑘−1:𝑗
0 GCP
0:00:0 in

• Base case
𝐺𝑖:𝑖 ≡ 𝐺𝑖 = 𝐴𝑖 𝐵𝑖
𝑃𝑖:𝑖 ≡ 𝑃𝑖 = 𝐴𝑖 ⊕ 𝐵𝑖

• Sum
𝑆𝑖 = 𝑃𝑖 ⊕ 𝐺𝑖−1:0 & 𝑆0 = 𝑃0 ⊕ 𝐶𝑖𝑛

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 Carry-Ripple Revisited

𝐺𝑖:0 = 𝐺𝑖 + 𝑃𝑖 𝐺𝑖−1:0 & 𝐺0:0 = 𝐺0 + 𝑃0 𝐺𝑖𝑛

𝑆𝑖 = 𝑃𝑖 ⊕ 𝐺𝑖−1:0 & 𝑆0 = 𝑃0 ⊕ 𝐶𝑖𝑛
A3 B3 A2 B2 A1 B1 A0 B0 Cin

1: Bitwise PG logic
G3 P3 G2 P2 G1 P1 G0 P0

2: Group PG logic

G2:0 G1:0 G0:0

C2 C1 C0

3: Sum logic

C3

Cout S3 S2 S1 S0

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PG Diagram Notation

Black cell Gray cell Buffer

i:k k-1:j i:k k-1:j i:j

i:j i:j i:j

Gi:k Gi:k
Gi:j Gi:j
Pi:k Pi:k Gi:j Gi:j
Gk-1:j Gk-1:j
Pi:j Pi:j
Pi:j
Pk-1:j

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 Carry-Ripple PG Diagram

Bit Position

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

tripple  t pg  ( N  1)t AO  txor

Delay
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

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 Brent-Kung Tree Adder
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0

15:12 11:8 7:4 3:0

15:8 7:0

Critical Path
11:0

13:0 9:0 5:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
𝑡𝑡𝑟𝑒𝑒 = 𝑡𝑝𝑔 + (2 ∗ 𝑙𝑜𝑔2 (𝑁) −1)𝑡𝐴𝑂 +𝑡𝑋𝑂𝑅
• PG FO < 2 • Wiring Tracks between levels = 1
• Maximum interconnect span = N/2

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 Sklansky Tree Adder

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0

15:12 14:12 11:8 10:8 7:4 6:4 3:0 2:0

15:8 14:8 13:8 12:8

Critical Path

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

𝑡𝑡𝑟𝑒𝑒 = 𝑡𝑝𝑔 + 𝑙𝑜𝑔2 (𝑁)𝑡𝐴𝑂 + 𝑡𝑋𝑂𝑅

• PG FO < N/2+1 • Wiring Tracks between levels = 1
• Maximum interconnect span = N/2

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 Kogge-Stone Tree Adder

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 14:13 13:12 12:11 11:10 10:9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2:1 1:0

15:12 14:11 13:10 12:9 11:8 10:7 9:6 8:5 7:4 6:3 5:2 4:1 3:0 2:0

15:8 14:7 13:6 12:5 11:4 10:3 9:2 8:1 7:0 6:0 5:0 4:0
Critical Path

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

𝑡𝑡𝑟𝑒𝑒 = 𝑡𝑝𝑔 + 𝑙𝑜𝑔2 (𝑁)𝑡𝐴𝑂 + 𝑡𝑋𝑂𝑅

• PG FO < 2 • Wiring Tracks between levels = N/2
• Maximum interconnect span = N/2

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 Tree Adders Summary

• Adder architectures offer area / power / delay tradeoffs.

• Choose the best one for your application.
Architecture Logic Max Tracks
Levels Fanout
Carry-Ripple N-1 1 1
Brent-Kung 2log2N – 1 2 1
Sklansky log2N N/2 + 1 1
Kogge-Stone log2N 2 N/2

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Adders Comparison

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 Reading
 Rabaey: sections 11.1 – 11.3
 Weste: sections 11.1 – 11.2

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