SMT AND PTH DESIGN FOR

MANUFACTURABILITY GUIDELINES
BY
KANTESH DOSS

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1. Purpose

The purpose of this document is to provide a single uniform design guideline for all rigid PWBs
(printed wiring boards) released at SE&A, Johnson City, thereby, providing consistency in the
PWB design and meeting the quality requirements of the printed wiring board assemblies.

2. Scope

This document defines Design for Manufacturability (DFM) guidelines for the printed wiring board
assemblies at SE&A.

3. Reference Documents :

3.1. IPC Documents :

IPC-T-50 Terms and Definition for Interconnecting and
Packaging Electronic Circuits.

IPC-A-610 Acceptability of Electronic Assemblies

IPC-2220 Design Specification

IPC-SM-782 Surface Mount Design and Land Pattern Standard

IPC-D-330 Design Guide

3.2. JEDEC Documents :

PUBLICATION 95 JEDEC Registered and Standard Outlines for
Semiconductor Devices.

3.3. Siemens Documents :

2588023 Specification, PWB Acceptance

2457744 General Requirements, Component Parts Qualification

2807238 PWB Design Guidelines for ICT

VA E562-805 “L4” Layout Symbols.

2800432 Solder Paste Stencil Design SOI

2608032 Specification, Solderpaste Stencil Fabrication

2807104 SMT Adhesive Stencil Design SOI

2491751 SOP for Creating and Formatting SOPs, SOIs, & DSOPs

4. Definitions :

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 4.1. Terminology and abbreviations used in this document :
DSOP Department Standard Operating Procedure
SOI Standard Operating Instruction
SOP Standard Operating Procedure
ECN Engineering Change Notice
FDR Final Design Review
PWB Printed Wiring Board
PTH Plated Through Hole. Conductive through holes of PWBs.
NPTH Non Plated Through Hole. Non conductive through holes of PWBs.
(Design) Preanalysis, Analysis performed on the PWB design prior to formal
release to manufacturing to ensure manufacturability and
compliance to the design guideline.
Raw Cards Unpopulated PWBs. Same as “bare boards”.
PWB Fabrication : Manufacturing of the bare boards or raw cards.
PWB Assembly : Populating PWB with components or PWB populated with components.

4.2. All other technical terms, definitions and abbreviations used in this document shall follow
IPC-T-50, Terms and Definitions.

5. Prerequisites :

Non required.

6. Responsibilities :

6.1. PWB Design :

Familiarity with the manufacturability guidelines delineated in this document before
PWB design project to insure a highly producible PWB layout.
Design PWBs per these guidelines. Consult with Manufacturing Engineering if a PWB
design will require a deviation from these guidelines.
Maintain active communication throughout the layout stages and beyond.

6.2. Design Engineering :

Perform pre-release analysis (preanalysis) of the PWB design with manufacturing to
insure guidelines have been observed and incorporated into the PWB.
Perform final design review (FDR). Coordinate preanalysis with Manufacturing and
PWB designers.

6.3. Manufacturing Engineering :

6.3.1 Process Development / Technology :
Responsible for the upkeep of this PWB Assembly Design Guideline. Performs
preanalysis. Provides inputs and recommendations on component selection and
PWB layout issues.
Evaluate proposed changes to this document and determine if the proposed
change is to be accepted as a standard change for all products, accepted as a
deviation for a specific product, or declined.

6.3.2. Manufacturing Support :

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 Responsible for maintaining the list of all current manufacturing equipment and
machines and their capabilities and tolerances.

6.4. Product Engineering :

Champion conformance to the manufacturability guidelines delineated in this
document to insure that PWBs released to production are cost effective and meet the
quality standards.

6.5 Manufacturing :
Provide timely feedback on any PWB assembly manufacaturability problems as they
are identified.

7. Procedures :

7.1. Factors in PWB Design :

(1) PWB
FABRICATION
(BARE BOARD)

(4) ASSEMBLY
PROCESS
DESIGNING FOR
- Machine/equipment
PWB capabilities & tolerances
(2) COMPONENTS MANUFACTURABILITY - solderability/refllow/wave
- Inspectability
- Repairability
- Testability

(3) PANELIZATION
when applicable

Fig. 1

It needs to be understood that demands from each of the differing areas may have conflicting
requirements placed on the design of the PWB. These conflicts need to be addressed and
analyzed and a compromise reached for optimizing the PWB design

7.1.1. PWB fabrication (bare board/raw card) requirements.

PWB fabrication (bare board requirements) is the basis for all design requirements.
Design requirements from other areas are inputted into the bare board design.
“Bare Board Design” not only has to meet the functional and electrical
requirements of the PWB but also the bare board manufacturability (PWB
fabrication) requirements. Design requirements of bare boards are
covered under IPC-2220 design specification.

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 7.1.2. Components :
In addition to their obvious effect on density and conductor routing, components also
impact assembly, solder joint integrity, reparability and testing. It is therefore,
important that the pwb design reflect appropriate tradeoffs that recognize
these and other significant manufacturing considerations. Mounting and attachment
of components will have the greatest impact on the lay out of the circuits
and will determine to a large extent the design of the pwb.

7.1.3. Panelization (when applicable)

Panelization has minimum impact on the individual PWB design. Impact of
panelization to the PWB design will be the addition of panel design
requirements..

7.1.4. PWB Assembly Processes

PWB design requirements set forth by the assembly process are of two types.
First is the requirement to overcome the limitations of the assembly processes
by designing in “allowances” to compensate for the “inherent process
limitations and/or process variations” (Ex. PWB size handling limitations,
component placement tolerances). Second type of design requirement is the
“assembly assist” to help ease and enhance the assembly processes (Ex. Fiducials,
Silk screens)

7.2. Ground Rules for PWB Design :

7.2.1. Bare boards meet the IPC’s Bare Board Design Guideline, IPC-2220.
Any conflict between the Bare Board Design Guild with design requirements of
other areas shall be reviewed by the preanalysis group for proper resolution.

7.2.2. All unique design requirements cannot be covered by this design guideline. I t should
be decided at preanalysis to determine whether a unique design requirement should be
made into a standard design guideline.

7.2.3. PWB Design shall not be used, applied, and/or adapted to compensate for
bad/faulty processes or materials.

7.2.4. Redesign or design modification has to be justified by cost analysis and feasibility
study.
Impact to other process areas has to be investigated and understood prior to redesign.

7.2.5. Tolerances and limitations of all current manufacturing equipment and

machines shall be incorporated into the PWB design when applicable.
7.2.6. All components used in SE&A, Johnson City shall be listed in the component
Library. Component Library shall be the primary source for determining the design
and layout of the PWB.

7.3. Inputs Into the PWB Design.

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 7.3.1 Bare board / Raw card manufacturability design requirements.
All PWBs have to meet the basic “Bare board / raw card” design requirements before
meeting the design requirements of the other factors (components, panels,
assembly process). Bare board design requirements are covered under IPC-2220.
Any conflicting design requirements which may arise shall be reviewed and
resolved by the preanalysis group (Design Engr, Manufacturing, Process Development).

Optimum Bare Board Size

20.32 cm ≤ W ≤ 35.56 cm
(8”) (14”)

PWB W 30.48 cm ≤ L ≤ 40.64 cm

(12”) (16”)

Fig. 2

Consult Manufactuirng for “L” & “W” outside the min, max dimensions.

7.3.2. Components :
All components used for manufacturing shall be listed in the Component Library.

7.3.2.1. THT (PTH) Components :

Axial Components
16.5 mm
( 0.65”)
Max
Max = Max D=
0.813 mm 5 mm
(0.032”) (0.20”)
Min =
0.38 mm
(0.015”) Component body
12.7 mm
(0.500”) diameter
preferred grid

Fig. 3

Radial Components

Max 8.90 mm
Max =16.51 mm (0.350”)
(0.650”)

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5.08 mm (0.200”) Max 8.90 mm Page 7
OF to (0.350”)
7.62 mm (0.300”)
 Max
10.90
(0.430”)
mm

Fig. 4

Dips & Dip Sockets

2.54
mm
grid
(0.100”)
7.62 mm (0.300)
&
15.24 mm (0.600)

Fig. 5

7.3.2.1.1. Component Size Limitations :

a) Axial Components (for machine inserted axials)

Max body length = 16.5 mm (0.650” )
Max component diameter = 5 mm (0.200”)

b) Radial components
Radial inserted parts should only be used where circuit performance
requires a radial part or where axial parts are impractical. This is
due to component cost and machine availability.
Max height = 16.5 mm (0.650”) includes preformed lead.

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 Max width / diameter = 8.9 mm (0.350”)
Max body length (for rectangular body) = 10.9mm (.430”)

c) DIP / Socket
Pin count & size (2.54 mm / 0.100” grid)
7.62 mm (0.300”) pin row to pin row = 20 pins max.
15.24 mm (0600”) pin row to pin row = 40 pins max.

7.3.2.1.2. Lead Dimensions :

a) Axial components :
Min = 0.38 mm (0.015”)
Max = 0.813 mm (0.032”)

b) Radial components :
Round lead : 0.36 to 0.71 mm (0.014” to 0.028”)
Square lead : 0.28 to 0.66 mm (0.11” to 0.026”)

7.3.2.1.3. Grid / Component lead spacing / Hole to hole distance for leads ::

a) Axial :
Range can be from 7.62mm to 20.32 mm (0.300” to 0.800”)
12.7 mm (0.500”) is preferred.

b) Radial :
2 leaded radial : 5.08 mm (0.200”)
Machine inserted transistors : 2.54 mm (0.100”)
Stand off prepped resistors : 7.62 mm (0.300”)

7.3.2.1.4. PTH (Plated through hole) sizes for component leads :

For manual insertion : 0.254 mm (0.010”) over max lead
width / diameter.
For Auto insertion : 0.406 mm (0.016”) over max lead width /
diameter.

7.3.2.1.5. Component / component spacing requirements

a) Axial to axial :
Parallel to each other (side to side)
between component bodies. ≥ 0.25mm (0.010”)
Axial hole perpendicular to another component hole ≥ 2.54 mm
(0.100”) from hole center to hole center.
End to end (in serial) ≥ 2.54 mm (0.100”) between hole
centers.

2.54mm (0.100”) 0.25mm (0.010”)

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 2.54
mm
(0.100”)

2.54mm
(0.100”)

Fig. 6

b) Radial to radial

Parallel to each other (side to side)

between component bodies ≥ 0.635mm (0.025”)

End to end (in serial) ≥ 5.08mm (0.200”) between hole centers.

Components (ends) vertical (to each other) ≥ 3.81mm (0.150”) from

hole center to hole center.

3.81mm
(0.150”)

mm
(0.025”)

5.08 mm
(0.200”)

c) Axial to radial :Fig. 7

3.81mm
(0.150”)

0.635mm
(0.025”)
3.81 mm
(0.150”)

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 Fig. 8
Side to side min component spacing ≥ 0.635mm (0.025”)

End to end (hole center to hole center same axis) ≥ 3.81mm (0.150”)

End holes vertical to each other (between hole centers) ≥ 3.81mm

( 0.150”)

d) DIP to DIP : .
Parallel to each other ≥ 4.45mm (0.175”) between hole centers.

End to end ≥ 0.250mm (0.010”) component to component

Perpendicular ≥ 5.00mm (0.200”) hole to hole

4.45mm (0.175”)
3.81mm (0.150)

2.54mm
(0.100”)

0.254mm
(0.010”) 5.08mm (0.200”)

0.254mm
(0.010”) 5.00mm (0.200”)

Fig. 9
e) DIP body end to axial body ≥ 0.254 mm (0.010”)

f) DIP to socket / Socket to socket ≥ 2.54 mm (.100”)

g) THT components to SMT components. See section 7.3.2.2.4 .

7.3.2.1.6. THT component hole to via hole spacing :

3.175mm Any clinched lead

(.125”)
3.175mm 3.175mm
2.54mm 1.27mm (,125”) (,125”)
(.100”) (,050”)

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 2.54mm
(.100”)

2.54mm 2.54mm
(.100”) (.100”)

Fig. 10

a) via to clinched hole (not in direction of clinch) : 2.54mm (0.100”) min

b) via to clinched hole (in direction of clinch) : 3.175mm (0.125”) min

c) via to radial hole (same axis from body end) : 3.175mm (125”) min

d) via to radial hole (not same axis ) : 1.27mm (0.050”), min

e) via to Dip hole same axis : 3.175mm (0.125”) (both outside & inside Dip
profile)

f) via to (on axis between Dip hole) Dip hole : 2.54mm (0.100”) (both outside &
inside Dip profile)

7.3.2.1.7. Other / misc requirements

See section 7.3.2.1.5

DIP hole to Axial hole (lead) : 3.81mm (0.150”) min

DIP body end to axial hole : 2.54mm (0.100”) min. See 7.3.2.1.5 d).
7.3.2.2. SMT Components

7.3.2.2.1. Component Size Limitation.

a). For reflow (solder paste reflow)
- Chip type smt components : RC805 or larger & Mini Melf.
- Other SMT components : height limitation ≤ 8 mm (0.315”)

b). For Wave solder :

- Chip type components
RC805, 1206, 1210, SOT23, MELF, MINIMELF
- ICs : Not permissible.
(Exceptions allowed if approved by Process Engineer.
Will require solder traps.) Ref. Section 7.3.4.1.8. c).

7.3.2.2.2. Smt fine pitch component : lead pitch ≤ 0.50 mm (0.020”)

Fiducials requirements : See section 7.3.4.1.8.

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 7.3.2.2.3. SMT component / smt component spacing requirements

a) Top side. (Solder paste) Reflow side :

Chip ≥ 0.635mm (0.025”) pad to pad

MELF ≥ 0.635mm (0.025”) pad to pad

SOIC/SOIC : Pad to pad (parallel) ≥ 1.27mm (0.050”)

Head to head (body) ≥ 1.27mm (0.050”)

1.27mm (0.050”)

1.27mm
(0.050”)

Fig. 11

PLCC/PLCC : Between leads : 1.5 x comp height.

PLCC w/other comp : 2.54mm (0.1”) + height of comp.

1.5 x H

PLCC PLCC

2.54mm PLCC
(.100”)
+ H
h COMP
x
Component X
h

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 Fig. 12

SOT23 : Minimum pad to pad spacing :

0.66mm (0.026)
b

0.66mm
a
(0.26”)

Fig. 13

b). Wave solder side :

MELF & mini MELF : same as reflow (top) side
SOT23 to SOT23 & SOT to chip ≥ 0.66mm (0.026”)

7.3.2.2.4. THT component to SMT component spacing:

a) Top side. (Solder paste) Reflow side :

Smt chip 1.52mm

(0.060”)
1.52mm
(0.060”)

DIP

1.52mm
(0.060”)
+½H

SOCKET

H
2.921mm (0.115”) + ½ H

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 Fig. 14

- DIP to smt comp :

- Minimum clearance from DIP hole center to smt component :

1.524 mm (0.060”) +1/2 H (smt component height)

- Minimum clearance from socket hole center to smt component :

2.921mm (0.115”) + 1/2 H (smt component height.)

- Minimum clearance between smt chip and DIP ends.

See section 7.3.4.2.1

- Smt components to axial components :

A A
A

Fig. 15

Hole center (pth) to pad (smt) ≥ 2.54mm (0.100”)

Tht comp body to smt comp body ≥ 2.54mm (0.100”)

- Smt components to radial components

TOP VIEW

Fig. 16

Minimum distance
Radial hole to smt component on radial end :
A & B ≥ 2.80mm (0.110”)
Radial hole to smt component on radial component side.

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 C & D ≥ 2.54mm (0.100”)

b) Wave solder (bottom) side :

Reference Section 7.3.4.2.
Smt chip to axial component (leads/holes) :
Reference Section 7.3.4.2.3.
Smt chip to radial component (leads/holes) :
Reference Section 7.3.4.2.5
- Smt chip to DIP.
Reference Section 7.3.4..2.4.
- DIPs : reference Section 7.3.4.2.4.

7.3.2.2.5. SMT component pads to via holes :

Smt pad 0.30 mm (0.012”)

0.30 mm
(0.012”)

Fig. 17
Smt Component pad to via ≥ 0.30 mm (0.012”)
( = 0.009” soldermask coverage + 0.003” soldermask clearance
around via.).
Bottom (wave solder) side :
- Distance between isolated via and smt pad ≥ 0.30 mm
(0.012”)
- Vias connected to smt pads.
Vias in pads for wave soldering are acceptable.

via

Component
outline

Smt pads

Fig. 18

7.3.2.3. Preferred Component orientation (for r/c layout)

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 Also reference component orientation for wave solder Section 7.3.4.1.6.

7.3.2.3.1. THT components

DIP

Radial

Axial
PWB

Tooling hole
⇒ ⇒ ⇒ Direction of Wave

Fig. 19

7.3.2.3.2. SMT components :

a) b)

Fig. 20

a) Single mounting position is preferred

b) For polarized components polarized end should face same direction.

7.3.2.4. Component Foot Print Land Design (for smt components) :

Foot print land design for effective soldering (reflow and wave) shall be determined by
”L4” (Layout Symbols, design guide) and/or by Process Development Dept..

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 7.3.3. Panels :
Panel’s input into the PWB design is mostly for the panel layout.

Panel Global fiducial (for smt pwb)

tooling
hole

PWB
tooling
hole

PWB Component free

Datum zone
&
tooling
hole
a

b
Datum to edge of board :
a & b = 2.84 mm (0.112”)

Fig. 21
7.3.3.1. Tooling hole requirements :
See Section 7.3.4.1.2.

7.3.3.2. Datum reference to edge of board :

a : ≥ 2.84 mm (0.112)
b : ≥ 2.84 mm (0.112)

7.3.3.3. Component/circuit free zones around the edge of board/panel = 5.0 mm (0.200”)

7.3.3.4. Component orientation for wave soldering.

See Section 7.3.4.1.6
Component orientations on the panel have the same requirements as the
individual PWBs. Panels should be treated as single boards in regards
to component orientation.

7.3.3.5. Fiducials For smt boards : See Section 7.3.4.1.8.

7.3.3.5.1. Fiducial placement location : Ref. 7.3.3.

7.3.3.5.2. Fiducial geometry : See 7.3.4.1.8

7.3.3.6. PWB size on panel ≥ 10.16 cm x 5.08 cm (4” x 2”)

7.3.3.7. Spacing between PWBs on panel

Preferred = 5.08 mm (0.200”)

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 Minimum = 1.25 x router bit diameter or 2.54 mm (0.100”).

7.3.3.8. Requirements for partial pre-milling, pre-scribing, scoring of panels :

7.3.3.8.1. For panels routed after assembly :

The object is to reduce or minimize the routing area. There still has to
be sufficient support of the individual boards during normal
assembly operations. Boards with edge connectors should have pre milled
area for the connector overhang and have sufficient clearances around it not to
interfere with the router during routing operation.

7.3.3.8.2. For panels with manual break aways (break off) for boards :

The object is to maximize support of the individual boards with the least
amount of board connection and making the boards easy to
break off (separate from the panel) after assembly.
The break-off residue (rough edges after break off) areas on the board
should not interfere with the subsequent higher assembly.

1.2 mm (0.047”) 0.80mm (0.031”) holes

radius dia.

PWB side 0.80mm

(0.031”)

Outside PWB
1.84mm (0.072”)

1.27mm (0.050”)

EXAMPLE OF BREAK OFF

Fig. 22

7.3.4. Designing for PWB Assembly :

7.3.4.1. General Requirements :

7.3.4.1.1. Component location silk screen requirements. Silk screen is not mandatory but
is preferred.
Must meet r/c design and acceptability requirements. (Controlled by silk screen
artwork).
Character height ≥ 1mm (0.040”)
Line width : 0.20 mm (0.008”)
Spacing between silk screen component character to pad ≥ 0.006”
Spacing between component outline to pad ≥ 0.010”

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 7.3.4.1.2. Tooling holes :

Tooling Component free zone

holes.

Datum Preferred Label location

Fig. 23
- Min of three npt (non plated through) tooling holes.

- Two holes to be on datum reference line

- Holes to be spaced as far apart as practically possible on panel.

- Hole size : 0.098” + 0.002” / -0.000

- Min of two tooling holes each for boards on panel array.

7.3.4.1.3. Datum reference to edge of board : 2.84 mm (0.112”) min,

7.3.4.1.4. Component/circuit free zones around the edge of board/panel = 5.03 mm

(0.200”)
Consult Manufacturing for wave soldered boards with requirement of 7.62 mm
(0.300”) component/circuit free zone on the leading edge of board.

7.3.4.1.5. Label area : Top side preferred

27.94 x 3.175 mm (1.100” x 0.125”) solder mask free non critical area.
(Area free of components, holes, vias, & circuitry).

7.3.4.1.6. Component orientation for wave solder

Wave solder direction

DIPs
SOT23 Axials
:

Radials

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 Smt
chips ic PWB
Top Side
Components on
bottom side

Fig. 24

a) Surface mount ICs & radials : perpendicular to travel direction to wave

b) Axials : lateral/parallel to travel direction to wave

7.3.4.1.7. For THT (includes npth single sided boards) & mixed boards :

a) Clearance around tooling holes > 10.16 mm (0.400”)

For DIPs Ref Section 7.3.4.2.2.

PWB

Clearance area
10.16mm
(0.400”)

Tooling hole 10.16mm (0.400”)

Fig. 25

b) Clinch clear area : 2.54 x 2.032 mm (0.100” x 0.080”) (both inward &
outward)

Component lead
pth Clinch direction

pad
2.03 mm (0.080”)

Clinch clear area

Bottom side of PWB 2.54 mm (0.100”)

Fig. 26

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 7.3.4.1.8. For smt boards

a) Fiducial location :

Global or board fiducial :

Maximize distance of 3 global fiducials on board.

Local or component fiducial (for fine pitch components)

For 4 side fine pitch components (quads) :
- for each component two fiducials diagonally placed
equi-distant from center of the component.
- one fiducial placed in center location of the component
and another placed within 5.08 cm (2”) radius from the
center of the component. This exposed fiducial
can be shared with adjacent components within the 5.08 cm (2”) distance of the from center fo the

For two side fine pitch components (duals) :

@ Fiduclals can be within the 5.08 cm (2”) radius from
the center of the component.
These fiducials can be shared (used as common)
fiducials with adjacent components.

Global Two fiducials diagonally equi-distant from

fiducial center of component

Tooling
hole

Component/ local
fiducial

Common
One fiducial on
fiducial
center location of
the component.
The other within
the 5.08 cm r
radius from center r
of the component r = 5.08 cm (2”)
Area for the
PWB common fiducial

Fig. 27

b) Fiducial geometry : (fiducials for board & fine pitch component)

- Preferred fiducial geometry is shown.

radius = 1.27mm (0.050”)

Global fiducial solder mask free area Local fiducial

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(.080”)
 Area to be free of
solder mask

1.52 mm
(.060”)

radius = 3.5 mm
(0.120”)
area free of exposed
circuit. 0.381 mm (.015”)
0.508 mm (0.020”)

Fig. 28
c) Solder traps : (robbers/thieves) Bottom (wave) side ICs.

Direction of Wave

Solder traps / robbers

Fig. 29

d) Component free zone around tooling holes = 3.180 mm (0.125”)

PWB

Tooling hole
3.18 mm (0.125”)

3.18 mm (0.125”)

Fig. 30

7.3.4.2. PWB design restriction and limitations based on process/manufacturing

machine/equipment capabilities.
Because not all PWB products are processed identically through the
manufacturing process their exposure to the type of process machines/
equipment will vary. The design restriction/limitation set by the

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particular machine/equipment will apply only to those PWB products which
are processed through that particular machine/equipment.
Because of the constant updates and enhancement to the process machines
and equipment PWB design requirements set by individual equipments
will not be included in this PWB design guide. However, it is imperative
that Product Engineers, Process Engineers, & Mfg Engineers, convey the
proper processing information (exposure to the type of process equipment/machine)
to the PWB Designers. Mfg Support Dept’s current equipments/machines list
should be referenced for proper input into PWB design.

Following examples are given for awareness purposes.

7.3.4.2.1. Repair tool : Fig 14.

Smt chip between DIP ends

Repair tool
4.83 mm (0.190”)

A ≥ 9.53 mm (0.375”)
A

DIP DIP

smt chip

Fig. 31

7.3.4.2.2. Dip inserter :

a) Smt chips placed within the DIP inserter profile (DIPs with less than
20 leads)
Minimum clearances has to be maintained at x, y, z

14 Pin IC Insertion

z
20 Pin DIP Tooling (Top Side)

Fig. 32

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 b) DIP clearance from tooling holes, & support pins.

Support pin

6.985 mm
(0.275”) 19.5 mm
(0.750”)

19.5 mm
(0.750”)
6.985 mm
(0.275”)

3.48 cm
2.35 cm 2.35 cm (1.20”)
(0.925”) (0.925”)

3.48 cm 6.985 mm
(1.20”) (0.275”)
Tooling hole

Fig. 33

7.3.4.2.3. Axial inserter :

Axial component
A Side view

PWB

Smt
chip
A End view

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 A ≥ 3.30 mm (0.130”)

Fig. 34
a) Smt chip to axial component lead hole :
Depends on smt component height.
Axial component lead hole to smt land/pad
Minimum = 3.30 mm (0.130”)
Preferred = 3.81 mm (0.150”)

7.3.4.2.4. THT component lead clincher. Bottom side (clinch head clearance
requirements).

a) Smt chip to DIP clinch head distance

DIP to smt minimum spacing

Smt component
DIP
PWB
0.762 mm
(0.030”) min

Dip clinch head

Fig. 35

Depends on smt comp height.

Minimum component spacing shall provides 0.762 mm (0.030”)
clearance between component height and clinch head.

b): Radial inserter : Smt chip to radial components

Smt comp height dependent :
Component spacing (between radial lead hole center to smt component)
shall maintain a minimum clearance of 0.762 mm (0.030”) between
(smt) component height and clinch head.

End view Side view

Smt Radial component

component

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 A A
PWB

Clinch head
.

Fig. 36
7.3.4.3. Soldering :

7.3.4.3.1. Component orientation : See Section 7.3.4.1.6

7.3.4.3.2. Component distribution over PWB surface :

Avoid bunching/clustering big components (both tht & smt) on one area
of the PWB. Even distribution of components provide better
thermal characteristic for improved solder reflow.

7.3.4.3.3. Pad design (for solderability) for plated through holes :

Octagonal Pad Round/Oval Pad Square Pad

preferred acceptable special usage only

Fig. 37

octagonal : preferred
round and oval : acceptable
square ; only for special cases (not acceptable for normal use).
7.3.4.3.4. Smt land / pad design for smt components :

Oval
Lands

Rectangular/square
Lands

Fig. 38

Oval shaped lands preferred.

Squared pads acceptable with rounded corners.

7.3.4.3.5. Thermal relief for plated through holes in large conductor area.
To prevent large conductor areas/lands from acting as heat sink, plated
through holes should not be put on large solid conductor area
without thermal reliefs. This requirement (design of thermal relief) should
be covered under the bare board/raw card design.

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 7.3.4.3..6. Smt solder paste stencil design for proper solder paste deposition :
Refer to 2800432 (Solder Paste Stencil Design) & 2608032
(Specification, Stencil Fabrication).
7.3.4.3.7. Component free zone from edge of board/panel ;
Ref 7.3.4.1.4
Consult Manufacturing Engineering for special requirement of the
leading edge of board going through wave solder to meet the
0.762 mm (0.300”) component free zone.

7.3.4.4. Inspectability Requirements :

7.3.4.4.1. Comp/comp spacing

For smt plcc & quad flat packs :
Min. spacing between components = height of the higher comp.

7.3.4.4.2. Solder joint inspection :

There should be no visual block (component interference) when
inspecting the solder joints of the smd components on a viewing
angle of 45°.

Component too close. Line of vision at Line of vision at

Interferes with visual Minimum
45 degrees. spacing 45 degrees.
inspection of adjacent
component solder
joints

∠ = 45° ∠ = 45°

Fig. 39

7.3.4.4.3. Component location silk screen : (Ref Section 7.3.4.1.1.)

Should be covered under the bare board requirements.
Should be able to visually inspect for :
- Component designation
- #1 pin loc.
- Component location.
- Proper component orientation & polarity.

7.3.4.5. Reparability & reworkability Requirements

7.3.4.5.1. Comp/comp spacing for accessibility.

Sufficient to allow for touch up and component replacement without
interference from adjacent components and potential damage.
See component spacing requirements in the component section 7.3.2.
Also reference Manufacturing Machine/equipment List.

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 7.3.4.5.2. Acceptability of solder mask coating.
Should have no soldermask on tabs, pads, lands and other areas where
solder mask is not wanted (fiducials). Soldermask shall not hinder
repairability / reworkability of the PWB.

7.3.4.5.3. Type component :

Needs to meet all component acceptability specifications.
All components should be able to withstand the normal assembly
processes.

7.3.4.5.4. High temp durability and processability : (r/c mat’l requirement)

Board material and components should have been pre-selected during
design. This should be covered under the bare board/raw card
design.
PWB capable of withstanding
- Touch up (solder joint) operations.
- Component replacement operations (solder fountain, hot air
vac, reflow oven, etc.).
- Circuit repairs & deletes, wire adds

7.3.4.6. Testability Requirements :

Ref Dwg #2807238, PWB Design Guidelines for ICT

7.3.4.6.1. Test pad size :

Square pads (when used to distinguish test pads from other
pads) ≥ 0.89 mm (. 0.035”)
Round pads ≥ 1 mm ( 0.040”)

7.3.4.6.2. Test pad to tooling hole location tolerance : ± 0.05 mm (0.002”)

7.3.4.6.3. Test pads.

Test pads to be on bottom side of board.
Test pads on top side is allowed in cases where putting bottom side test
pad is impractical or not feasible

7.3.4.6.4. Test pad accessibility without interference :

Component height
Free area
mm Test pad
(0.125”)

1.27 mm (0.050”)
component Free Area
1.27 mm (0.050”)

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 Fig. 40
Test pad center line to component ≥ 1.27 mm (0.050”)
Component height on probe side ≤ 3.20 mm (0.125”)

7.3.4.6.5. Location tolerance (test pad to PCB datum) : ± 0.05 mm (0.002”)

7.3.4.6.6. Preferred grid (test pad to test pad spacing) : 2.5 mm ( 0.100”)
Min : 1.27 mm (0.050”)

7.3.4.6.7. Test pads ( on probe side) to be min of 3.175 mm (.125”) from edge of
board, tooling holes, slots, and inboard openings.

7.3.4.6.8. No soldermask on test pads

This requirement should be covered under the bare board
acceptability specification.

7.3.4.6.9. No test pad targets within 3.175 mm ( 0.125”) around tooling holes.

7.3.4.6.10. Test pad distribution :

Even distribution over the PWB surface area.

7.3.4.6.11. Vacuum seal for testing

a) Tenting of vias with soldermask.

Proper soldermask artwork needs to be provided. Should
be covered under the bare board/raw card requirement.

b) Solder plugging of vias with solderpaste (smt boards).

Proper solder paste stencil artwork needs to be provided.

c) Non soldermask tented vias to be solder filleted during

wave solder.

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