module operate

input wire [7:0]A,B,

input wire [2:0] S,

output reg [7:0] Y

);

always @ *

if (S==3'b000)

Y=8'b0;

else if (S==3'b001)

Y=A&B;

else if (S==3'b010)

Y=A|B;

else if (S==3'b011)

Y=A^B;

else if (S==3'b100)

Y=A+B;

else if (S==3'b101) }

Y=8'b0;

else if (S==3'b001)

Y=A&B;

else if (S==3'b010)

Y=A|B;

else if (S==3'b011)

Y=A^B;
else if (S==3'b100)

Y=A+B;

else if (S==3'b101)

Y=A-B;

else if (S==3'b110)

Y=~A;

else Y=A*B;

endmodule

module tb_operate_if;

reg [7:0] in1,in2;

reg [2:0] in3;

wire [7:0] out;

operate A1 (.A(in1),.B(in2),.S(in3),.Y(out));

initial

begin

in1=8'b0111_0001; in2=8'b0101_0101; in3=3'b110;

#5 in1=8'b0111_0110; in2=8'b0110_0000; in3=3'b000;

#5 in1=8'b0110_0110; in2=8'b0101_0000; in3=3'b011;

#5 $Stop;

end

endmodule
module opearate

input wire [7:0] A,B,

input wire [2:0]S,

output reg [7:0]Y

);

always @ *

case( S)

3'b000 :Y=8'b0;

3'b001 :Y=A&B;

3'b010 :Y=A|B;

3'b011 :Y=A^B;

3'b100 :Y=A+B;

3'b101 :Y=A-B;

3'b110 :Y=~A;

3'b111:Y=A*B;

endcase

endmodule
module tb_operate_c;

reg [7:0] in1,in2;

reg [2:0] in3;

wire [7:0] out;

reg [7:0] in1,in2;

reg [2:0] in3;

wire [7:0] out;

operate A1 (.A(in1),.B(in2),.S(in3),.Y(out));

initial

begin

in1=8'b0111_0001; in2=8'b0101_0101; in3=3'b110;

#5 in1=8'b0111_0110; in2=8'b0110_0000; in3=3'b000;

#5 in1=8'b0110_0110; in2=8'b0101_0000; in3=3'b011;

#5 $Stop;

end

endmodule