CONCORDIA UNIVERSITY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

LABORATORY MANUAL

COEN 212: DIGITAL SYSTEMS DESIGN I

BY:

TED OBUCHOWICZ

2021

mick
keith
ron
 REVISION HISTORY

This document is a major rewrite of the COEN 212 Laboratory Manual originally authored by Dr.
Asim Al-Khalili and Chris Taillefer in 2001.

This version was written during the March - May, 2021 time period by T. Obuchowicz.

Revised: Corrected typo in Table 1, May 9, 2023.

ii
 EMERGENCY PROCEDURES

1. Emergency Procedure during a Fire Alarm

• Stop your work and secure your area

• Proceed to the nearest Fire Exit
Do not use elevators or escalators - Chimney effect
• General Alarm - Bells ring continuously
Message will be given throught the Public Address System, if available
• Follow the directives from the Fire Monitors (wearing armbands)
• Once outside move away from the building to the gathering location
YOU must evacuate

2. Emergency Procedures in the Event of Fire Discovery

• Sound the alarm by activiating the nearest Pull Station

• Call Security to confirm using
- Fire or Emergency telephones located near exit stairwells, no dialing necessary, or
- Public phones by dialing 848-3717 (no charge), or
- Office phones by dialing 811, or
- Cellular phone by dialing 848-3717
• Give your Name, Location, and Nature of the problem
• Once informed of the situation, Security will call 911
YOU must evacuate

3. What to do in case of Medical Emergency

Serious/Life-Threatening Emergency
• Call 9-911 to alert Urgences Sante
- Give your Name, Location, and Nature of the problem
• You must call Security using (see above instructions)
• Give your Name, Location, and Nature of the problem and them them that you have called the
911
• Provide first-aid assistance if you can or call 4181 to request and Emergency Responder
• Secuirty will send an agent to assist you
- Agents have been trained to provide first-aid assistance
You must always contact Security

None Life-threatening Situation (not requiring Urgences Sante)

• Call Security (see above instructions)
• Provide first-aid assistance if you can or call 4181 to request an Emergency Responder

October 14, 2004

iii
 TABLE OF CONTENTS

p.

The Lab Report ...................................................................................................................... 1

Integrated Circuits, Logic diagrams and Schematic Diagram ............................................... 3

EXPERIMENT 1: Introduction to the Equipment, Logic Gates, and

Debugging Techniques........................................................................................................... 6

EXPERIMENT 2: Combinational Logic Circuit Design ...................................................... 14

EXPERIMENT 3: Design of (Medium Scale Integration) MSI Components ..................... 16

EXPERIMENT 4: Latches..................................................................................................... 23

REFERENCES ...................................................................................................................... 32

APPENDIX: Pinout Diagrams,Data Sheets, Safety Procedures and

Equipment Manuals ............................................................................................................... 33

iv
 1

The Lab Report

A written lab report is required for each experiment performed. The lab report is to include the
following sections:

1. Cover page

Include the experiment number/title, course name, course number and lab section, your name and
ID, the name of the lab instructor and the due date and the date the lab was performed.

2. Objectives

State in your own words the objectives of the experiment. One or two concise sentences shall suf-
fice.

3. Theory and Results/Discussion

Present relevant theory for the experiment. Summarize the salient portion in a few
sentences. As an example, the following shows a well written Theory section:

“A multiplexer is a device which selects one of many possible inputs to a single output based upon
the binary values of one or more select inputs. It is implemented using a combination of AND and
NOT gates with the outputs of the AND gates connected to the output OR gate. A half adder forms
the two bit sum (consisting of the carry and sum bits) of two single input bits. a full-adder forms
the two bit sum of 3 input values (the two bits being added and the carry out bit generated from
the addition of a previous pair of input bits.”

Include all truth tables listing the theoretical and experimental results, any K-maps, etc. used in
the design of the circuits. Discuss the results obtained during the experiment and account for any
discrepancies from the expected values.

4. Questions

Answer any questions posed in the lab manual.

5. Conclusions

State what was achieved in the lab and contrast with the experiment objectives. Conclude on the
salient portions of the lab. Do not write conclusions of the form:

“Overall, this lab was a success but I had some trouble in building some of the circuits. I eventu-
ally found the source of the error and the circuit gave proper values of outputs for all the possible
input combinations.”

A proper conclusion would be written in following style:

 2

“The input/output module connects directly to a solderless breadboard and allows one to provide
inputs to a digital circuit and to observe the state of the outputs via a light emitting diode (LED).
Various configurations of basic logic gates were constructed and shown to work as expected by
the theoretical analysis performed in the pre-lab.”

6. Pre-lab

Include the any pre-lab material as an Appendix to the lab report.

A few tips to keep in mind when writing a lab report:

• All figures and tables are to be numbered and referred to within the text of the report.

• All schematic diagrams are to be drawn with the use of drawing software. Adhere to proper con-
ventions for logic gates.

• Any material from an outside source must be properly referenced. Use you own words when
writing the report.

• Use a word processing package to create the report. Use a 12 point or larger font for ease of
readability.

• Proof read the report prior to its submission.

The lab report should contain all the required information for the reader to be able to reproduce
the results, without referring to any outside source.
 3

Integrated Circuits, Logic Diagrams and Schematic Diagrams

The integrated circuits used in this lab are manufactured with a package type known as dual in-
line pin (DIP). A DIP package is a rectangular housing, typically made of plastic, with two rows
of metal pins which are used to electrically connect the logic gates contained within the package.
A DIP package is typically inserted into the through holes of a printed circuit, or into the tie points
of a solderless breadboard. [1]

All of the integrated circuits used in this lab, contain one or more logic gates. Figure 1 is a picto-
rial representation of the 4 two-input AND gates contained within a 7408 TTL (transistor-transis-
tor logic) integrated circuit chip.

+5V

14 13 12 11 10 9 8

SN74HC08N

1 2 3 4 5 6 7

Ground
SWO SW1 Logic Indicator 5

Figure 1. Pinout diagram of a 7408 integrated circuit.

As indicated in Figure 1, the 7408 chip contains 4 independent two-input AND gates. Pins 1 and 2
of the 14 pin device are connected to the inputs of one of the AND gates, pin 3 is the gate output.
In a similar manner, pins 4 and 5 are the inputs of a second AND gate with pin 6 providing the
output. Also indicated in Figure 1 are wires from pins 14 and 7 used to provide +5 V DC and
ground as well as wires to provide switch inputs to pins 1 and 2, and a wire from the gate output
(pin 3) to a logic indicator. Most TTL chips use pins 14 and 7 for power and ground respectively
(although there are a few exceptions to this general rule).

A note on part numbers:

The astute reader will have noted the part number SN74HC08N in Figure 1. The first two letters
denote the manufacturer (SN for Texas Instruments). The next two digits identify the temperature
range of the device ( 74 for commercial, and 54 for military grade applications), the next several
 4

letters representing the logic sub-family (LS for low-power Schottky, HC for high-speed CMOS
, etc). Two or more trailing digits representing the functionality of the device (00 for a NAND
device, 08 for an AND device, etc.). Additional letters at the end of the part number are used to
represent grade and other information and varies widely according to manufacturer. [2]. In the rest
of this manual, we shall simply refer to part numbers in a shortened manner such as 7408.

Most digital logic textbooks use logic diagrams similar to that shown in Figure 2. A logic diagram
is a method of specifying the functionality of a digital logic circuit using standard conventions for
logic gates and lines to represent the inputs to the circuit, the outputs, and the interconnections
between the various gates which comprise the circuit.

mick
keith
ron

Figure 2: A simple logic diagram.

Figure 2 illustrates a simple combinational logic circuit diagram containing two inputs called
mick and keith, an output called ron. The circuit consists of two AND gates and an exclusive-OR
gate.

A schematic diagram, in addition to the logic gates and connecting wires, contains additional
information: instance numbers, part numbers, and pin numbers. This information is helpful
when prototyping the circuit. An instance number is a unique identifier given to every integrated
circuit contained within the circuit. The part number identifies the various component parts (i.e.
7408, 7486, etc.). Numbers written in parentheses identify which pins of the integrated circuit are
to be connected. In other words, the pin numbers identify a particular gate within an integrated
circuit.

Figure 3 gives the schematic diagram of the logic circuit shown in Figure 2.
 5

part number

mick (1) 7408

(3)
U1
keith (2) (4)
7408 (6) ron
U1
(1) (5)
7486 (3)
U2
(2)

instance number

pin number

Figure 3: A schematic diagram.

Two separate integrated circuits are required to construct the circuit given in Figure 3: a 7408
AND gate and a 7486 exclusive-OR chip. The instance name of U1 has been given to the 7408
chip, and the instance name U2 has been assigned to the 7486. Note how the use of the pin num-
bers distinguish among the two AND gates used from the 7408 instance as well as identifying
which of the gates from within the 7486 chip has been used.

A note on instance names:

A standard convention exists for naming instance names in schematic diagrams. The letter R is
used to represent a resistor. Successive suffix number are used to distinguish among different
components of a specific type. For example: R1, R2. The letter C is used for capacitors, the letter
U is used for integrated circuits. All the schematic diagrams in this lab will contain only inte-
grated circuits, and thus will only contain instance names of the type: U1, U2, etc.

All the schematic diagrams created for any pre-lab must adhere to these proper conventions.
 6

EXPERIMENT 1: Introduction to the Equipment, Logic Gates, and Debug-

ging Techniques.

Objectives

• To introduce the student to the lab equipment.

• To become acquainted with basic digital integrated circuits and logic gates.
• To become familiar with using a solderless breadboard to build digital logic circuits.
• To learn basic debugging skills in order to determine to reason(s) a logic circuit is not function-
ing correctly.

Introduction

The equipment used in the lab is presented in this section.

Solderless Breadboard

A solderless breadboard is a device used to build and test electronic circuits. A pictorial represen-
tation of a typical breadboard is shown in Figure 1.1

Bus strip (ground)

−
+

−
+

Vertical tie points Bus strip (+5 V)

Figure 1.1: A solderless breadboard.

 7

A breadboard contains two sets of vertical tie-points and horizontal bus strips. Each of the 5 tie-
points in a given vertical row are electrically connected to each other (represented by the vertical
dashed oval). Each vertical row is electrically insulated from every other row in a given set. The
two sets of vertical tie points are insulated from each other. Two sets of horizontal bus strips are
provided at the top and bottom portions of the breadboard. All the tie-points in a given horizontal
row are electrically connected to each other. Each horizontal row is electrically insulated from
every other horizontal row. Some breadboards typically have - and + labels identifying a row as a
ground row, or a power supply row respectively. The horizontal bus strips are used to provide
power and ground to each integrated circuit chip.

A DIP integrated circuit is placed in the holes of the breadboard, with the top set of pins in the
holes of the upper set of vertical tie-points and the lower set of pins in the tie points of the lower
vertical tie-points as illustrated in Figure 1.2.

−
+

14 13 12 11 10 9 8

1 2 3 4 5 6 7

−
+

Figure 1.2: An DIP integrated circuit inserted into the breadboard.

As shown in Figure 1.2, a semi-circular notch on one end of a DIP integrated circuit is used to
identify the pins of the integrated circuit. When the notch is oriented such that it is at the left-hand
end, pin 1 is the bottom left pin. The pin numbering continues consecutively in a counter-clock-
wise manner with pin 14 being the top right-most pin.

PB503 Digital Design Workstation

The lab in room H807 is equipped with the model PB503 digital design prototyping stations (one
per each student in the lab) from Global Specialties. It consists of a large breadboarding area (sev-
eral standard breadboards providing more than 2500 tie points) together with a power supply,
switches to provide inputs , and light-emitting diode (LED) to indicate the state of gate outputs.
 8

The lab demonstrator will provide an overview of the use of the prototyping station during the
first lab session. The student who is enrolled in the online version of the lab is referred to the
“Online Labs Input/Output Module User Guide”.

Power Switch:

An illuminated red rocker switch, located in the top left hand corner of the unit is used to power-
on and power-off the prototyping station. The switch will be illuminated with a red color when
turned on. A standard 15 A, 115 VAC , 60 Hz power line provides the required input power. [3]

Power Supplies:

The PB503 provides a fixed +5 V DC power supply together with two variable DC power sup-
plies. Binding posts provide access to each power supply with the red binding post providing +5
V DC, and the yellow and blue binding posts for each variable power supply. The black binding
post provides the circuit ground connection. ONLY the +5 V DC power supply is to be used for
the experiments in these labs. The inadvertent use of the variable power supplies applied to TTL
integrated circuits may result in permanent damage to the chip. [3] Each binding post is internally
connected to one of the 4 bus strips as indicated in Figure 1.3.

+5 V
+V −V

ground

Figure 1.3: Connection of power supply binding post connectors to bus strips.

Logic Indicators:

Sixteen LEDs (8 red LEDs and 8 green LEDs) are provided as logic indicators. A logic ‘1’ will
cause connected to an indicator will illuminate the red LED, a logic ‘0’ will cause the green LED
to light. When there is no input connected to a particular logic indicators, neither the red nor the
green LED will be lit. A set of 8 double tie-points solderless connector provide a means of connet-
ing a wire to a particular logic indicator. [3]

Two slide switches control the operation of the logic indicators. The upper switch selects the
power supply and must be set to the +5 position. The lower switch selects between TTL and
CMOS logic levels and must be set to the TTL position. Refer to Figure 1.4.
 9

+5

+V

1
2
3
4
5
6
7
8

TTL

CMOS

Figure 1.4: Logic Indicators.

Switches:

A set of eight switches are used to provide logic outputs. When a switch is placed in the upper (1)
position, a logic ‘1’ output is produced. Placing the switch in the lower (0) position will produce a
logic level of zero volts. [3] The voltage setting switch must be in the +5 position. Refer to
Figure 1.5.

CAUTION: The TTL integrated circuits may be damaged if supplied with an input voltage
greater than their operating voltage. ALWAYS ENSURE THAT THE SWITCH VOLTAGE
SETTING IS IN THE +5 POSITION.

+5

+V

S1 S2 S3 S4 S5 S6 S7 S8

Figure 1.5: Switches.

Logic Probe

Each lab station is equipped with a hand-held logic probe which is used to indicate the state of a
particular node in a circuit. It is useful when debugging a circuit. The +5 V red alligator clip is
 10

attached to the +5 V binding post and the black ground clip is connected to the black ground bind-
ing post. The logic probe has a threshold switch which is used to select either TTL or CMOS logic
levels - it is to be set to the TTL position. During use, the tip of the logic probe is placed against a
leg of an integrated circuit to determine the logic value present on the pin. The red LED indictor
will light if the logic value is ‘1’. The green indicator LED will be illuminated when there is a
logic ‘0’ present at the probe tip. [4] The use of the logic probe shall be presented by the lab TA.
Figure 1.6 is a pictorial representation of the logic probe.

Probe tip

HI Logic "HI" LED

Logic "LO" LED

LO

TTL
Threshold
Switch
CMOS

+5 V alligator
clip

Ground clip

Figure 1.6: Logic probe.

Circuit Debugging

Your circuit may not work properly. Common mistakes include:

• Not turning on the power switch to the prototyping station.

• Forgetting to apply +5 V and ground to each integrated circuit chip used.
• Incorrectly applying +5 V and ground to an integrated circuit. Although most TTL integrated
circuits use pin 14 and pin 7 for power and ground, there are some exceptions. Always consult the
component data sheet when in doubt (see the Appendix for the data sheets).
• A broken wire can be the cause of a hard to troubleshoot problem. Use the logic probe to trace
signals from a switch input to a gate output by appying the tip of the probe directly to the pin of an
integrated circuit. In such a manner, a defective wire (or bent pin) can be readily determined to be
the source of the problem.
• Using an incorrect integrated circuit. Keep your chips neatly organized on the workbench.
 11

• Use of an integrated circuit which has been internally damaged. Ensure that all the gates within
a chip are functioning properly by applying known inputs and observing the gate outputs (either
with a logic probe, or connecting the gate output to the logic indicators). The lab is also equipped
with a logic tester. The lab TA shall demonstrate its use. Any chips which have been identified as
defective are to be placed in the trash bin - do not return known defective integrated circuits to the
parts cabinet.
• An error during the wiring of the circuit. A well-drawn schematic diagram (done as part of the
pre-lab) can help o prevent wiring errors and will assist you in completing the lab within the allot-
ted time period. Indicating which connections have been made (with a pen or pencil and a ‘tick’
mark) is a good habit to adopt.
•Any unusual odor is usually indicative of a short-circuit, immediately turn off the power. Care-
fully touch each integrated circuit with a finger tip. If this chip is unusually hot to the touch,
remove it and determine whether it is still functional.

WARNINGS

1) NEVER connect TTL gate outputs to each other. This will result in permanent damage to
the gates (and possibly to the entire integrated circuit).

2) NEVER connect a TTL gate output to ground. Double check all power and ground connec-
tions.

3) Unused gate inputs should be connected to either +5 V or ground. This will help to mitigate
deleterious effects due to electrical noise.

4) Follow the practice of establishing the power and ground connections to each integrated circuit
as the first step when breadboarding a circuit. Omitting the power supply connections is one of
the most common mistakes.

5) NEVER apply a voltage greater than +5 V to any TTL gate input. ALWAYS ensure the voltage
setting switch on the prototyping station is set to the +5 V position prior to turning the unit on.

Prelab

1) Read the entirety (including the Questions) of Experiment 1 prior to attending your lab ses-
sion.

2) Prepare the complete schematic diagrams for the logic circuits given in Figures 1.7 and 1.8.
Refer to the Appendix for the chip pinout diagrams.

3) Determine the truth tables for the logic circuits given in Figures 1.7 and 1.8

4) Tabulate the type and required number of integrated circuit chips required to complete the lab.

Procedure
 12

Part 1:
Construct the circuit shown in Figure 1.7 using the solderless breadboard and the required inte-
grated circuit chips. Test each circuit by using three input switches to provide the inputs A,B, and
C. Connect the output labelled OUT to an indicator LED. Record in a truth the values of the out-
put , for all possible input combinations.

DEMONSTRATE THE OPERATION OF YOUR CIRCUITS TO THE LAB INSTRUC-

TOR PRIOR TO DISCONNECTING THE CIRCUITS.

B
C

A
B OUT
C
A
B
C

Figure 1.7: A combinational logic circuit.

Part 2:

Construct the circuit shown in Figure 1.8 using the solderless breadboard and the required inte-
grated circuit chips. Test each circuit by using three input switches to provide the inputs A,B, and
C. Connect the output labelled OUT to an indicator LED. Record in a truth the values of the out-
put , for all possible input combinations.

A
C

OUT
B
C

Figure 1.8: Another combinational logic circuit.

 13

Questions

1) Determine the Boolean functions produced by the two circuits in Figures 1.7 and 1.8.

2) Do your experimental results agree with the analysis of the two circuits performed in the Pre-
lab? Comment on any differences.

3) Comment on the functionality of the two circuits given in Figures 1.7 and 1.8.

4) Give the Boolean function implemented by the circuit in Figure 1.9.

mick
keith

stones
ron

Figure 1.9: A hint for the implementation of the circuit in Part 1.

 14

EXPERIMENT 2: Combinational Logic Circuit Design

Objectives

• To gain experience in combinational logic minimization using the K-map method.

• To design and construct and verify a 2-bit combinational multiplier.
• To gain further experience in connecting digital logic circuits using a breadboard.

Introduction

The fastest possible implementation of combinational logic is always given by a two-level stan-
dard form (sum-of-products or product of sums). In this experiment, a 2-bit combinational logic
multiplier circuit will be designed an tested. The multiplier has two 2-bit binary input (A1A0 and
B1B0) and a 4-bit output (P3P2P1P0). Note the use of the subscript notation to differentiate the
bits of the inputs and output with the most significant bit labelled with subscript 1 and 3 respec-
tivey. For example, 3 multiplied by 2 in binary would performed using the ‘grade school’ shift and
add method as:

11
x 10
00 (0 multiplied by 11 = 00)
+ 110 (shift a 0, 1 multiplied by 11 = 11)
0110

The truth table for the binary multiplier with inputs A1A0 and B1B0 and output P3P2P1P0 with the
subscript 1 and 3 used for the most significant bit of the input and output respectively is given in
Table 1:

Table 1: Truth table for binary multiplier (inputs A1A0, B1B0, and outputs P3P2P1P0)

Output
A1 A0 B1 B0 P3 P2 P1 P0 value in
decimal

0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0
0 0 1 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0
0 1 0 0 0 0 0 0 0
0 1 0 1 0 0 0 1 1
0 1 1 0 0 0 1 0 2
 15

Table 1: Truth table for binary multiplier (inputs A1A0, B1B0, and outputs P3P2P1P0)

Output
A1 A0 B1 B0 P3 P2 P1 P0 value in
decimal
0 1 1 1 0 0 1 1 3
1 0 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0 2
1 0 1 0 0 1 0 0 4
1 0 1 1 0 1 1 0 6
1 1 0 0 0 0 0 0 0
1 1 0 1 0 0 1 1 3
1 1 1 0 0 1 1 0 6
1 1 1 1 1 0 0 1 9

Prelab

1) Read Experiment 2 in its entirety in order to become acquainted with the procedure to complete
this experiment.st

2) Design the 2-bit multiplier using the truth table and four 4-variable K-maps. Obtain the stan-
dard sum-of-products expression for each output.

3) Draw the schematic diagram of the multiplier circuit taking care to label each gate with its part
number, instance number, and pin numbers.

Procedure

1) Connect the 2-bit multiplier circuit which was designed in step 2 of the Prelab. Verify its func-
tionality by testing all 16 input combinations and recording the outputs obtained in a truth table.

Questions

1) How many rows would the truth table of a combinational 3-bit multiplier have? How many out-
puts would be required? What kind of a K-map would be required to minimize this truth table?

2) Obtain the minimal sum-of-product Boolean expression for the truth table of the circuit in Fig-
ure 1.7 of Experiment 1. Comment on the circuit provided in Figure 1.8 of Experiment 1 and it’s
relationship with the obtained minimal sum-of-products expression.
 16

EXPERIMENT 3: Design of (Medium Scale Integration) MSI Components

Objectives

• To design a 2-1 multiplexer and to become familiar with word-sized versus single bit operands.
• To design a combinational adder circuit.

Introduction

Multiplexers:

A multiplexer (commonly referred to as a mux) is a digital logic component which selects one of
many inputs to a single output. A select input determines which of the inputs is routed to the sin-
gle output. A multiplexer with m select lines will have up to 2m inputs. The operation of a 4-to-1
mux can be best explained with the analogy of a mechanical switch, the position of which is deter-
mined by the value of the two select inputs S1S0 as shown in Figure 3.1.

IN0

IN1
OUT
IN2

IN3

S1 S0

Figure 3.1: Operation of a 4-to-1 mux by means of a switch analogy.

The position of the rotating switch is controlled by the values on the two select lines. When S1S0
= 00, the switch is connected to the input labelled IN0, when the select l inputs S1S0 are equal to
01, the switch is connected to input IN1, etc. The operation of this mux can also be succinctly
expressed using the syntax of a C++ switch statement:

switch (S1S0)
{
case 00: OUT = IN0 ;
break;
 17

case 01: OUT = IN1 ;

break;
case 10: OUT = IN2 ;
break;
case 11: OUT = IN3;
}

Figure 3.2 gives the logic diagram of a 4-to-1 and 2-to-1 mux. The chosen symbol is meant to rep-
resent the “concentration” of many inputs into a single output. The inputs to the mux are labelled
with binary numbers (or sometimes with their decimal equivalents) to emphasize the selection of
the input based upon the value of the select input(s).

IN0 00
IN0 0
IN1 01
OUT OUT
IN2 10
IN1 1
IN3 11

S1 S0 S0

(a) (b)

Figure 3.2: A 4-to-1 mux (a) and a 2-to-1 mux (b).

Word sized operands:

In digital design, the inputs and outputs of a gate or component often consist of multiple bits
(commonly called a bus). A specific notation when drawing logic diagrams is used to refer to a
bus. A diagonal slash (/) together with a number representing the width of the bus (in terms of
number of bits) is used to indicate that the wire is a bus (rather than a single bit). For example,
consider the logical AND of two inputs, M and K, with each input consisting of a bus of three bits.
Figure 3.3 gives the logic diagram of such an AND gate.

3
M 3
OUT
K
3
Figure 3.3: A word-sized two input AND gate.
 18

A total of three 2-input AND gates connected as shown in Figure 3.4 would be required to imple-
ment this word-sized AND gate.

M0
OUT0
K0

M1
OUT1
K1

M2
OUT2
K2

Figure 3.4: Implementation of the word-sized AND gate.

A word-sized 2-to-1 mux, where each input consists of a bus of 2 bits, would require a total of two
2-to-1 muxes with the select line of each mux commonly connected. A 2-to-1 mux is required for
every bit contained in the buses. The logic diagram of this word-sized multiplexer together with
it’s implementation is shown in Figure 3.5. Note that the individual bits of each word in Figure 3.5
(a) have been explicitly shown (for pedagogical reasons), in practice this is normally not done.
Note also how the bus widths have been emphasized using an exaggerated line thickness. This too
is usually not done. The 2-to-1 mux which is responsible for handling bit 1 of each two bit word is
shown in blue (again for reasons of clarity).

IN0_0 2
IN0_0
0 OUT_0 0
IN0_1 IN0 OUT_0
2

IN1_0 2 OUT
1 OUT_1 IN1_0 1
IN1_1 IN1

S0 S0

IN0_1 0
OUT_1

IN1_1 1

S0

(a)
(b)

Figure 3.5: A word-sized 2-to-1 mux (a) and its implementation (b).
 19

Binary addition:

The addition of two binary bits (call them M and K), yields a two bit answer: a carry (C) bit and a
sum (S) bit. The four possible cases are:

0 0 1 1
+ 0 + 1 + 0 + 1
00 01 01 10
CS CS CS CS

The first three cases represent the ‘easy’ cases in which there is no carry bit. The carry bit for
these three cases is 0 and has been indicated in red. The last cases represents the addition of 1 + 1
= 2 (in decimal). The carry is 1 and sum bit is zero for the last case. If the value of 10 is expanded
as an unsigned binary number representing powers of 2 we obtain:

10 = ( 1 x 21) + (0 x 20)
= 2 + 0
= 2

The rules of binary addition may also be define in tabular form as given in Table 2.

Table 2: Binary addition (half-adder)

M K C S

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

Addition of multi-bit numbers:

Consider the addition of two binary numbers, in which each operand consists of three bits. When
adding a pair of bits, it is possible that a carry may be generated. This carry is to be added with the
next (higher-order) pair of bits. For example:

1 0 (carries)
0 1 1 3
+ 0 1 0 + 2
1 0 1 5
 20

The addition of the least significant pair of bits ( 1 and 0), yields a sum bit of 1 and a carry out of
0. This carry of 0 is then added with the middle pair of bits ( 1 and 1) to yield a sum bit of 0 and a
carry of 1. This carry bit is then added with the two high order bits to yield a sum bit of 1 and a
final carry out of 0. It is readily apparent that in order to add two multi-bit numbers, the rules of
binary addition must be expanded to include the possibility of adding a carry bit which has been
generated from the addition of a previous pair of bits. These rules define what is called full-addi-
tion and are given in Table 3.

Table 3: Rule of Full-Addition

M K Cin Cout S

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

The four entries in Table 3 in which the Cin has value of 0, reduce to the half-adder table. The four
rows in which Cin is equal to 1 (indicated in red) can easily be deduced. The last row represents
the addition of 1 + 1 + 1 = 11 ( = 3 in decimal).

A full-adder has three inputs (the pairs of bits to be added and a carry-in bit which is to be added
together with the input bits) and produces a carry out bit together with a sum bit. Figure 3.6 shows
the block diagram of a full-adder.

M K

Cout Full−Adder Cin

Figure 3.6: Block diagram of a full-adder component.

 21

A series of full-adders, connected in a chain-like manner, may be used to perform the addition of
two multi-bit operands. Such an adder is called a ripple-carry adder. Each full adder receives the
pair of input bits, together with the carry-out of a previous full-adder to produce a sum and a
carry-out bit. Figure 3.7 illustrates a 3-bit ripple-carry adder performing the addition of 3 + 2 .

0 0 1 1 1 0

M K M K M K
0 0
1 0
Full−Adder Full−Adder Full−Adder
Cout Cin Cout Cin Cout Cin
S S S

1 0 1

Figure 3.7: A 3-bit ripple-carry adder.

It should be noted that the ripple-carry adder is one of many different possible implementations of
a combinational adder. Entire textbooks have been written devoted to the topic of binary addition.
The reason being that addition is the basis of higher mathematical operations such as multiplica-
tion and division. In fact, even subtraction may be performed using only addition. The interested
reader is directed to the topic of two’s complement arithmetic.

Prelab

1) Read the entirety of Experiment 3.

2) Design a 2-to-1 multiplexer in which the inputs and outputs consist of single bits. Provide the
truth table for this multiplexer using IN0 and IN1 for the two inputs, S for the select line and OUT
for the output. Obtain the minimal standard sum-of-products expression for the output.

3) Obtain the schematic diagram for the mux designed in 2). Use proper conventions as to the
labelling of part numbers, instance numbers and pin numbers.

4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are
all 2-bits wide. Use IN0_1, IN0_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for
the outputs. Obtain the schematic diagram for a possible implementation of such a mux following
the example given in Figure 3.4.

5) Obtain a implementation of a half-adder circuit using standard gates such as AND, OR, NOT,
XOR, etc. Obtain the minimal standard sum-of-products expressions for the Carry and Sum out-
puts of a half-adder. Compare these expressions with your implementation.
 22

6) Draw the schematic diagram of your implementation of the half adder from step 5).

7) Design a full-adder by minimizing the full-adder truth table to obtain the minimal standard
sum-of-products expressions for the Carry out and Sum outputs.

8) Obtain the schematic diagram of the full adder obtained in step 7. Identify all part numbers,
instance numbers and pin numbers.

Procedure

1) Construct the 2-to-1 mux designed in step 2) of the Prelab. Apply all possible inputs and
record your results in a truth table.

2) Construct the word-sized 2-to-1 mux designed in Prelab step 4). Employ the following testing
methodology:

(a) with the select input equal to 0, change the IN0 input to all 4 possible values (00,01,10,11)
while keeping the IN1 input to some constant value.

(b) with the select input equal to 0, keep the IN0 input to some constant value and change the IN1
input to all possible 4 values (00,01,10,11).

(c) Repeat steps (a) and (b) with the select input equal to 1.

3) Connect the half-adder designed in step 6) of the Prelab. Test your half-adder by applying all
possible input combinations and record your results in a truth table.

4) Connect the full-adder designed in step 8) of the Prelab. Test your full-adder by applying all
possible input combinations and record your results in a truth table.

Questions

1) How many rows would the truth table of a combinational 32-bit parallel adder contain?
Express your answer as a power of two. State any assumptions you may have made in order to
deduce your answer.

2) Would it be practical to design a 32-bit parallel adder using the techniques of Boolean minimi-
zation to obtain the SOP expressions for each of the outputs?

3) How many full-adders would be required to construct a 32-bit ripple carry adder?
 23

EXPERIMENT 4: Latches

Objectives

• To become familiar with the operation of a basic SR latch (NOR and NAND implementations).

• To become familiar with level-sensitive clocked latches.

Introduction

All the circuits thus far encountered have been examples of combinational logic - the outputs can
be determined from only knowledge of the inputs. In a sequential circuit, knowledge of both the
inputs and the present output is required in order to determine the value of the (next) output.

A latch is a sequential circuit which is capable of storing one bit of information. A latch has two
outputs, traditionally designated by Q and Q The outputs are logical complements of each other.

The SR (Set Reset) latch has two inputs ( S(et) and R(eset) ) and two outputs ( Q and Q . ) The
latch may be set to store a logic ‘1’ by applying S = 1 and R = 0. The latch is reset to store a logic
‘0’ by applying S= 0 and R = 1. When the inputs are both equal to logic ‘0’, the latch holds its
output (either logic ‘1’ or logic ‘0’). As we shall soon see, the S = 1 and R = 1 is the so called
forbidden input combination and is to be avoided in normal latch operation. Figure 4.1 gives the
logic diagram of a basic SR NOR gate latch.

R
1 Q

2 Q
S

Figure 4.1: Basic SR NOR gate latch.

Table 4 summarizes the operation of the SR NOR latch.

Table 4: SR NOR Latch Operation

Comments S R Q Q

set the latch 1 0 1 0

 24

Table 4: SR NOR Latch Operation

Comments S R Q Q

hold the 1 (after 0 0 1 0

having set it)
reset the latch to 0 1 0 1
0
hold the 0 after 0 0 0 1
having reset it
the forbidden 1 1 0 0
input state

As Table 4 indicates, there are two rows corresponding to the input combination of S = 0 and R =
0. This is due to the fact that the latch may have been previously been either set to store a ‘1’, or
have been reset to store a ‘0’. It is assumed that the operations described by Table 4 have been
successively applied, one after another, commencing with the setting of the latch as described by
the first row of the table.

SR NOR Latch Operation:

As drawn in Figure 4.1, it would appears that there are two feedback paths in the SR latch. How-
ever, the circuit may be redrawn as in Figure 4.2 to reveal that, in reality, there is only one feed-
back path.

R Q
1
2 Q
S

Figure 4.2: SR NOR latch redrawn.

The operation of the SR latch is best understood by noting the behaviour of a NOR gate when one
of it’s inputs is held either at a constant logic ‘0’ or constant logic ‘1’ value. A NOR gate with one
of its inputs held at ‘0’ will invert the other input. A NOR gate with one of its inputs held at ‘1’,
will produce an output of ‘0’ irrespective of the value of its other input. These observations may
be deduced by application of the Boolean equations which describe a NOR gate as provided in
Figure 4.3.
 25

0
1 M+0 =M ( acts as an inverter)
M

1
2 K+1 =1 =0 (provides a constant 0)
K

Figure 4.3: Operation of a NOR gate where one input is fixed to a constant value.

We shall consider five different cases of S and R.

Case 1: S = 1 and R = 0 which will cause the latch to store a logic 1 ( Q = 1 and Q = 0). This
input combination causes NOR gate 2 to produce a constant 0, which is fed back as an input to
NOR gate 1 (which is acting as an inverter). The fed back 0 will be inverted to produce the Q = 1
output at NOR gate 1. Figure 4.4 illustrates this input combination. Note that in the subsequent
figures, an inverter has been drawn within the NOR gate symbol to emphasize that the NOR gate
is acting as an inverter.

R=0 Q=1
1 0
2 Q
0 S=1

Figure 4.4: Setting the latch.

Case 2: We keep R = 0 and change S from 1 to 0. Recall that this is the hold state. NOR gate 1
continues to invert its fed back input of 0 to produce Q = 1. NOR gate 2 now acts as an inverter
and will still produce Q = 0. Thus the latch retains its output value and will retain this output as
long as power is supplied (and S = 0 and R = 0). Figure 4.5 illustrated the latch holding the logic 1
output value.
 26

R=0 Q=1
1 0 Q
0 S=0 2

Figure 4.5: Hold state with Q = 1.

Case 3: To reset the latch, we apply S = 0 and R = 1. This will cause NOR gate 1 to produce a
constant output of 0. This output will then be inverted by NOR gate 2 to produce Q = 1. The latch
is now in the reset state (retaining the Q = 0 output value) as illustrated in Figure 4.6.

R=1 Q=0
1 1 Q
1 S=0 2

Figure 4.6: Resetting the latch.

Case 4: After having reset the latch, we keep S = 0 and make R = 0. NOR gate 1 will now act as
an inverter and will invert the fed back value of 1 to keep Q at 0. This Q = 0 output of NOR gate 1
will be inverted by NOR gate 2, keeping Q at 1. Thus, there is no change in the Q and Q output,
and the latch is holding the 0 output. Figure 4.7 shows how the Q = 0 output is retained with S= 0
and R = 0.

R=0 Q=0
1 1 Q=1
1 S=0 2

Figure 4.7 Hold state with Q = 0.

 27

Case 5: To illustrate the forbidden input combination of both S and R equal to 1, Figure 4.8 shows
how both of the NOR gates are producing a constant ‘0’ and each of their outputs. Thus, we have
the contradictory state of Q = 0 and Q = 0. Again, it must be stressed that under normal latch
operation, the input state S = 1 and R = 1 is to be avoided.

R=1 Q=0
1 0 Q=0
0 S=1 2

Figure 4.8: Forbidden input state.

SR NOR Latch State Transition Table:

Since the output of a latch depends upon the present value stored in the latch (for the hold case),
we may consider the present value of the Q output as in input to the latch (along with the S and R
inputs). In doing so, the state transition table of a SR NOR latch can be given as in Table 5.

Table 5: State Transition Table for SR-NOR latch

S R Q(present) Q(next) Comments

0 0 0 0 Hold
0 0 1 1 Hold
0 1 0 0 Reset
0 1 1 0 Reset
1 0 0 1 Set
1 0 1 1 Set
1 1 0 - Forbidden
1 1 1 - Forbidden

Note that there are two possible values for the Q output in the two hold cases - the latch may hold
either a 0 or a 1.

Level Sensitive SR NOR latch with Enable:

 28

It is useful in certain digital systems to be able to control at which points in time, a latch (or a flip-
flop) is to respond to changes in its input signal. This is usually achieved with the addition and a
supplementary input signal (usually designed as the enable input). It is only during the times that
the enable signal has value of logic 1, that a latch is to respond to activity on its inputs (i.e S and
R), when the enable signal is logic 0, the latch is to hold its current state. Figure 4.9 provides a
timing diagram which illustrates the behaviour of a level-sensitive SR NOR latch with an enable
input.

enable

latch holds latch resets hold set latch holds the current Q = 1
current Q = 1 and does not respond to
since enable = changes on S and R since
0 enable = 0

Figure 4.9 : Level-sensitive SR NOR latch timing diagram.

The addition of two AND gates to a basic SR NOR latch allows for the selective level-sensitive
control of a latch as shown in Figure 4.10 (the SR latch has been indicated by the rectangle).

Soutside S Q

enable

R Q
Routside

Figure 4.10: SR latch with level-sensitive enable circuitry.

 29

When the enable signal is equal to 0, the output of both AND gates comprising the enabling cir-
cuitry are equal to 0, thus the latch is in the hold state (irrespective of any changes in the Soutside
and Routside inputs). When the enable signal is equal to 1, the S and R inputs of the latch are
respectively equal to the Soutside and Routside inputs, allowing the latch to respond to the activ-
ity on the external Soutside and Routside inputs. Table 6 summarizes the operation of a level-sen-
sitive latch with enable (sometimes referred to as a gated latch).
Table 6: Gated SR latch operation

enable S R Comments

0 0 0 latch will hold

present Q.
1 Soutside Routside latch will respond to
activity on the exter-
nal S and R inputs

SR NAND Latch:

NAND gates may be used to implement a SR latch as indicated in Figure 4.11.

S 1 Q

2 Q
R

Figure 4.11: SR NAND latch implementation.

It should be noted that for a NAND gate implementation of a SR latch, the input which is equal to
logic 0 is the input which takes effect. For example, if S = 0 and R = 1, this will set a SR NAND
latch. Consequently, the S = 0 and R = 0 input combination is the forbidden input. Table 7 sum-
marizes the operation of a SR NAND latch.
 30

Table 7: SR NAND latch operation

S R Q Q Comments

0 1 1 0 set
1 1 1 0 hold
1 0 0 1 reset
1 1 0 1 hold
0 0 1 1 forbidden

The addition of two NAND gates to allow for the selective enabling of a SR NAND latch to the
basic SR NAND latch (refer to Figure 4.12) results in a latch with the same functionality of the
circuit given in Figure 4.10.

Soutside
S
1 Q

enable

2 Q
R
Routside

Figure 4.12: A level sensitive latch using NAND gates.

Prelab

1) Read the entirety of Experiment 4 to become familiar with the operation of the SR latch and the
procedures required to complete this experiment.

2) Draw the schematic diagrams of:

• a SR NOR latch.
 31

•a level sensitive SR NOR latch with enable.

• a SR NAND latch.

• a level sensitive SR NAND latch with enable.

3) Derive the state transition table for a SR NAND latch.

4) Using a procedure similar to that presented earlier, explain the operation of a SR NAND latch.
HINTS: Under which case does a 2-input NAND gate behave as an inverter? When does a 2-input
NAND gate produce an constant 1 output?

Procedure

Part 1

Connect the SR NOR latch. Verify its functionality by applying all possible input values. Record
your results in a state transition table.

Part 2

Connect the level sensitive SR NOR latch with enable. Verify its functionality by applying all pos-
sible input values. Record your results in a state transition table.

Part 3

Connect the SR NAND latch. Verify its functionality by applying all possible input values.
Record your results in a state transition table.

Part 4

Connect the level sensitive SR NAND latch with enable. Verify its functionality by applying all
possible input values. Record your results in a state transition table.

Questions

1) Suggest a use for a collection of latches.

Hint:

“Memory is a stranger
History is for fools” - R. Waters, Perfect Sense Part 2,.
 32

REFERENCES

1. https://en.wikipedia.org/wiki/Dual_in-line_package.

2. https://en.wikipedia.org/wiki/7400-series_integrated_circuits.

3. PB503 Analog & Digital Design Workstation Instruction Manual, Global Specialties.

4. Logic Probe Instruction Manual, B&K Precision.

 33

APPENDIX: Pinout Diagrams, Safety Procedures, Data Sheets and Equip-

ment Manuals

Figures 5.1(a) and 5.1(b) give the pinout diagrams for the integrated circuits commonly used in
the lab experiments. The ECE Safety Procedures, selected data sheets and equipment manuals fol-
low the pinout diagrams.

14 13 12 11 10 9 8 14 13 12 11 10 9 8

+5 V +5 V

7400 7402

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7

14 13 12 11 10 9 8 14 13 12 11 10 9 8

+5 V +5 V

7404 7408

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7

14 13 12 11 10 9 8 14 13 12 11 10 9 8

+5 V +5 V

7410 7411

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7

Figure 5.1(a): Chip pinout diagrams.

 34

14 13 12 11 10 9 8 14 13 12 11 10 9 8

+5 V +5 V

7420 7421

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7

14 13 12 11 10 9 8 14 13 12 11 10 9 8

+5 V +5 V
7430

7432

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7

14 13 12 11 10 9 8

+5 V

7486

GND
1 2 3 4 5 6 7

Figure 5.1(b): Chip input diagrams.