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Static Timing Analysis (STA)

Lecture #09: Flip-Flop Timing Constraints – Setup & Hold
Video Lecture Link
13-01-2023 VLSI Excellence - Gyan Chand Dhaka 1
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Static Timing Analysis (STA) – Flip-Flop Timing Constraints

There are two main problems which can arise in synchronous logic designs -
1) Max Delay: The data does not have enough time to pass from one register to the next register before the
next clock edge
- Max delay violations are the result of slow data path, including the register's Tsetup time, therefore it is
often called Setup Path/Setup Constraint
- A setup constraint specifies how much time is necessary for data to be available at the input if a
sequential device before the clock edge that captures the data in the device.
2) Min Delay: The data path is so short that it passes through several registers during the same
clock cycle
- Min delay violations are the result of sort data path, causing the data to change before the
register's Thold time has passed, therefore it is often called the Hold Path/Hold Constraint
- A hold constraint specifies how much time is necessary for data to be stable at the input of a
sequential device after the clock edge that captures the data in the device


REG1 REG2
Comb
D Q D Q
X Logic Y
Clock
Launch Flop Capture Flop
Setup & Hold Launch Edge
Hold Check Setup Check
Hold Capture Edge Setup Capture Edge

Static Timing Analysis (STA) – Flip-Flop Timing Constraints – Max Delay/Setup
REG1 REG2
Comb
D Q D Q
X Logic Y
Tsetup/Thold
Clock
Tcq Tsetup
T
Static Timing Analysis (STA)-Flip-Flop Timing Constraints – Max Delay/Setup
1) After the clock rises, it takes Tcq for the data to propagate
to point X.
2) Then the data goes through the delay of the logic to get to
point Y
3) The data has to arrive at point Y, Tsetup before the next

clock edge
In general, out timing path is a race –
1) Between the data arrival, starting with the launching

clock edge and
2) The data capture, one clock period later

Static Timing Analysis (STA) – Flip-Flop Timing Constraints – Min Delay/Hold

REG1 REG2
Comb
D Q D Q
X Logic Y
Tsetup/Thold
Clock
Tcq Tcomb_delay
Thold
Static Timing Analysis (STA) – Flip-Flop Timing Constraints – Min Delay/Hold

1) Hold problems occur due to the logic changing before
Thold has passed
2) This is not a function of a cycle time – it is relative to

a single clock edge
In general,
1) The clock rises and the data at X changes after Tcq
2) The data at Y changes after comb logic delay later
3) Since the data at Y has to stay stable for Thold after the clock edge (for the
second register).
The change at Y has to be at least Thold after the clock edge
- Hold time is the amount of time that REG1’s old data must persist at the D input
of REG2 after the clock edge
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3. Static Timing Analysis (STA) – Practice/Interview Questions – Link
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Lecture #10: Derivation of Setup & Hold Timing Equations,

Maximum Operating Frequency
Video Lecture Link
Static Timing Analysis (STA) – Setup & Hold Equations
Something about Clock with respect to Timing Path – They (Timing Paths) are relative/synchronous
to a clock
Note:
• Data arrives at a start point relative to a clock
• Data gets captured at a end point relative to a clock
• Starting a new cycle, the clock signal resets the time at the register
• STA tool breaks all the timing paths at registers, so that each timing path has one clock cycle or
one clock period as the timing goal (Required Time)
Slack :
Slack = Required Time – Arrival Time (For Setup)

Slack = Arrival Time – Required Time (For Hold)
Required Time : Defined by the timing constraints like Clock Period

Arrival Time : When the signal actually arrives at a end point
Note:
Positive Slack indicates that path Met timing constraint requirement, Negative Slack indicates that
path did not Met timing requirements.

Setup Requirement for Register-to-Register Path: REG1 REG2
D Comb D Q
Q
Clk_to_Q [REG1] + Comb Delay <= Clock Period Logic
CLK -> Q Tsetup
– Tsetup[REG2]
CLK
Here, Required Time = Clock Period – Tsetup[REG2]
Clock
Arrival Time = Clk_to_Q [REG1] + Comb Delay
Data is LAUNCHED ! Data is CAPTURED !
Hence, Setup Slack = Required Time – Arrival Time Setup Check
Clock Period

Hold Requirement for Register-to-Register Path: REG1 REG2
D Comb D Q
Q
Clk_to_Q [REG1] + Comb Delay >= Hold_Check[0] Logic
CLK -> Q Thold
+ Thold [REG2]
CLK
Here, Required Time = Hold_Check[0] + Thold [REG2]
Clock
Arrival Time = Clk_to_Q [REG1] + Comb Delay
Data is LAUNCHED !
Hence, Hold Slack = Arrival Time – Required Time Hold Check
Note: Default Hold Check is at 0

Clock Period

Input-to-Register Path:
REG2
Comb
D Q
Logic 2
Clock


Setup Requirement for Input-to-Register Path:
Outside Word Module being Constrained
REG2
REG1
Comb Comb
D Q D Q
Logic 1 Logic 2
Input Pin
CLK -> Q Tsetup/Thold
CLK
Input Delay
Clock
Required Time = Clock Period – Tsetup [REG2]
Arrival Time = {Clk_to_Q[REG1] + Comb Logic 1 Delay} + Comb Logic 2 Delay
Arrival Time = Input Delay + Comb Logic 2 Delay
Setup Slack = Required Time – Arrival Time

Hold Requirement for Input-to-Register Path:
Required Time = Hold_Check[0] + Thold [REG2]
Arrival Time = {Clk_to_Q[REG1] + Comb Logic 1 Delay} + Comb Logic 2 Delay
Arrival Time = Input Delay + Comb Logic 2 Delay
Hold Slack = Arrival Time – Required Time


Setup Requirement for Register-to-Output Path:
Module being Constrained Outside Word
REG2
REG1
Q Comb Comb
D D Q
Logic 1 Logic 2
Output
CLK -> Q Tsetup/Thold
Pin
Output Delay
CLK
Clock

Setup Requirement for Register-to-Output Path:
Required Time = Clock Period – Tsetup [REG2]
Arrival Time = Clk_to_Q [REG1] + Comb Logic 1 Delay + Comb Logic 2 Delay
Arrival Time = Clk_to_Q [REG1] + Comb Logic 1 Delay + Output Delay
Setup Slack = Required Time – Arrival Time


Hold Requirement for Register-to-Output Path:
Required Time = Hold_Check[0] + Thold [REG2]
Arrival Time = Clk_to_Q [REG1] + Comb Logic 1 Delay + Comb Logic 2 Delay
Arrival Time = Clk_to_Q [REG1] + Comb Logic 1 Delay + Output Delay
Setup Slack = Arrival Time – Required Time


Input – to – Output Path Timing Requirements:
Comb
Logic
There is no clock defined for combinational paths. So, we need to use either a virtual clock or set path delays to
Constrain input to output paths
Using Virtual Clock or Dummy Clock –
Slack = Clock Period – Input Delay – Output Delay – Comb Logic Delay
Note: Input Delay and Output Delay are set with respect to a Clock
Static Timing Analysis (STA) – Setup & Hold (Summary)

1) For setup constraints, the data has to be propagate fast enough to be captured by the next clock edge.
- This sets our maximum frequency
- If we have setup failures, we can always just slow down the clock
2) For Hold constraints the data path delay has to be long enough so it is not accidently captured by the
same clock edge
- This is independent of the clock period
- If there is hold failure, you can throw your chip away!!!
Static Timing Analysis (STA) – Maximum Operating Frequency
Maximum Operating Frequency:
Clk_to_Q [REG1] + Comb Delay <= Clock Period – Tsetup[REG2] {Setup Equation}
Clock Period (T) >= Clk_to_Q[REG1] + Comb Delay + Tsetup(REG2)
So, Minimum Clock Period (T) = Clk_to_Q[REG1] + Comb Delay + Tsetup(REG2)
Hence, Maximum Clock Frequency = 1/T
13-01-2023 VLSI Excellence - Gyan Chand Dhaka


Thanks !!
Lecture #11: Setup & Hold Timing Equations Summary &

Maximum Operating Frequency
Video Lecture Link


1) For setup constraints, the data has to be propagate fast enough to be captured by the next clock edge.
- This sets our maximum frequency
- If we have setup failures, we can always just slow down the clock
2) For Hold constraints the data path delay has to be long enough so it is not accidently captured by the
same clock edge
- This is independent of the clock period
- If there is hold failure, you can throw your chip away!!!

Thanks !!

Lecture #11: Maximum Operating Frequency & Minimum

Clock Period of a Digital Design
Video Lecture Link


Thanks !!

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youtube.

Static Timing Analysis (STA)

Video Lecture Link

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 1

Static Timing Analysis (STA) – Flip-Flop Timing Constraints

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 2

Static Timing Analysis (STA) – Flip-Flop Timing Constraints

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 3

Static Timing Analysis (STA) – Flip-Flop Timing Constraints

Hold Check Setup Check

Hold Capture Edge Setup Capture Edge

Static Timing Analysis (STA) – Flip-Flop Timing Constraints – Max Delay/Setup

Static Timing Analysis (STA)-Flip-Flop Timing Constraints – Max Delay/Setup

3) The data has to arrive at point Y, Tsetup before the next

In general, out timing path is a race –

1) Between the data arrival, starting with the launching

2) The data capture, one clock period later

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 6

Static Timing Analysis (STA) – Flip-Flop Timing Constraints – Min Delay/Hold

Static Timing Analysis (STA) – Flip-Flop Timing Constraints – Min Delay/Hold

2) This is not a function of a cycle time – it is relative to

2) The data at Y changes after comb logic delay later

Best Free VLSI Content

1. Verilog HDL Crash Course – Link

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 9

Static Timing Analysis (STA)

Lecture #10: Derivation of Setup & Hold Timing Equations,

Video Lecture Link

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 1

Static Timing Analysis (STA) – Setup & Hold Equations

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 2

Static Timing Analysis (STA) – Setup & Hold Equations

Slack = Required Time – Arrival Time (For Setup)

Required Time : Defined by the timing constraints like Clock Period

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 3

Static Timing Analysis (STA) – Setup & Hold Equations

Setup Requirement for Register-to-Register Path: REG1 REG2

Hence, Setup Slack = Required Time – Arrival Time Setup Check

Static Timing Analysis (STA) – Setup & Hold Equations

Hence, Hold Slack = Arrival Time – Required Time Hold Check

Note: Default Hold Check is at 0

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 5

Static Timing Analysis (STA) – Setup & Hold Equations

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 6

Static Timing Analysis (STA) – Setup & Hold Equations

Outside Word Module being Constrained

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 7

Static Timing Analysis (STA) – Setup & Hold Equations

Required Time = Clock Period – Tsetup [REG2]

Arrival Time = {Clk_to_Q[REG1] + Comb Logic 1 Delay} + Comb Logic 2 Delay

Arrival Time = Input Delay + Comb Logic 2 Delay

Setup Slack = Required Time – Arrival Time

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 8

Static Timing Analysis (STA) – Setup & Hold Equations

Required Time = Hold_Check[0] + Thold [REG2]

Arrival Time = {Clk_to_Q[REG1] + Comb Logic 1 Delay} + Comb Logic 2 Delay

Arrival Time = Input Delay + Comb Logic 2 Delay

Hold Slack = Arrival Time – Required Time

Static Timing Analysis (STA) – Setup & Hold Equations

Module being Constrained Outside Word

13-01-2023 VLSI Excellence - Gyan Chand Dhaka 10

Static Timing Analysis (STA) – Setup & Hold Equations

Required Time = Clock Period – Tsetup [REG2]