Outline

❑ Logical Effort
❑ Delay in a Logic Gate
❑ Multistage Logic Networks
❑ Choosing the Best Number of Stages
❑ Example

Lecture 6: ❑ Summary

Logical
Effort
6: Logical Effort CMOS VLSI Design 4th Ed. 2

Introduction Example
❑ Chip designers face a bewildering array of choices ❑ Ben Bitdiddle is the memory designer for the Motoroil 68W86,
– What is the best circuit topology for a function? an embedded automotive processor. Help Ben design the
– How many stages of logic give least delay?
??? decoder for a register file.
A[3:0] A[3:0]
32 bits

– How wide should the transistors be? ❑ Decoder specifications:

4:16 Decoder

16 words
16
Register File
– 16 word register file
❑ Logical effort is a method to make these decisions – Each word is 32 bits wide
– Uses a simple model of delay – Each bit presents load of 3 unit-sized transistors
– Allows back-of-the-envelope calculations – True and complementary address inputs A[3:0]
– Helps make rapid comparisons between alternatives – Each input may drive 10 unit-sized transistors
❑ Ben needs to decide:
– Emphasizes remarkable symmetries
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?
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Delay in a Logic Gate Delay Plots

❑ Express delays in process-independent unit d d =f+p
❑ Delay has two components: d = f + p d = abs 2-input

 = gh + p 6
NAND Inverter
❑ f: effort delay = gh (a.k.a. stage effort)  = 3RC g = 4/3
Normalized Delay: d

– Again has two components

5 p=2
 3 ps in 65 nm process ❑ What about d = (4/3)h + 2
❑ g: logical effort 60 ps in 0.6 m process 4 g=1
NOR2? p=1
– Measures relative ability of gate to deliver current 3 d=h+1
– g  1 for inverter
❑ h: electrical effort = Cout / Cin 2 Effort Delay: f

– Ratio of output to input capacitance 1

– Sometimes called fanout Parasitic Delay: p
0
❑ p: parasitic delay 0 1 2 3 4 5
– Represents delay of gate driving no load Electrical Effort:
– Set by internal parasitic capacitance h = Cout / Cin

6: Logical Effort CMOS VLSI Design 4th Ed. 5 6: Logical Effort CMOS VLSI Design 4th Ed. 6
Computing Logical Effort Catalog of Gates
❑ DEF: Logical effort is the ratio of the input ❑ Logical effort of common gates
capacitance of a gate to the input capacitance of an
inverter delivering the same output current. Gate type Number of inputs
❑ Measure from delay vs. fanout plots 1 2 3 4 n
❑ Or estimate by counting transistor widths
Inverter 1
2 2 A 4 NAND 4/3 5/3 6/3 (n+2)/3
Y
2 B 4
A 2 NOR 5/3 7/3 9/3 (2n+1)/3
A Y Y
1 B 2 1 1
Tristate / mux 2 2 2 2 2
Cin = 3 Cin = 4 Cin = 5 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
g = 3/3 g = 4/3 g = 5/3

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Catalog of Gates Example: Ring Oscillator

❑ Parasitic delay of common gates ❑ Estimate the frequency of an N-stage ring oscillator
– In multiples of pinv (1)
Gate type Number of inputs
1 2 3 4 n
Inverter 1
Logical Effort: g=1 31 stage ring oscillator in
NAND 2 3 4 n
0.6 m process has
NOR 2 3 4 n
Electrical Effort: h=1 frequency of ~ 200 MHz
Parasitic Delay: p=1
Tristate / mux 2 4 6 8 2n
Stage Delay: d=2
XOR, XNOR 4 6 8
Frequency: f osc = 1/(2*N*d) = 1/4N

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Transistor Sizing a Complex

Example: FO4 Inverter CMOS Gate
❑ Estimate the delay of a fanout-of-4 (FO4) inverter
d B 8 6
A 4 3
C 8 6

D 4 6
Logical Effort: g=1 OUT = D + A • (B + C)
Electrical Effort: h=4 The FO4 delay is about A 2
Parasitic Delay: p=1 300 ps in 0.6 m process D 1
Stage Delay: d=5 15 ps in a 65 nm process
B 2C 2

6: Logical Effort CMOS VLSI Design 4th Ed. 11 6: Logical Effort CMOS VLSI Design 4th Ed. 12
Multistage Logic Networks Multistage Logic Networks
❑ Logical effort generalizes to multistage networks ❑ Logical effort generalizes to multistage networks
❑ Path Logical Effort G= gi  ❑ Path Logical Effort G= gi 
Cout-path Cout − path
❑ Path Electrical Effort H= ❑ Path Electrical Effort H=
Cin-path Cin − path
❑ Path Effort F =  f i =  gi hi ❑ Path Effort F =  f i =  gi hi

10
x
❑ Can we write F = GH?
y z
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

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Paths that Branch Branching Effort

❑ No! Consider paths that branch: ❑ Introduce branching effort
15 – Accounts for branching between stages in path
90
G =1 Con path + Coff path
H = 90 / 5 = 18
5 b=
Con path
GH = 18 15
B =  bi
90 Note:

h
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6 i = BH
F = g1g2h1h2 = 36 = 2GH ❑ Now we compute the path effort
– F = GBH

6: Logical Effort CMOS VLSI Design 4th Ed. 15 6: Logical Effort CMOS VLSI Design 4th Ed. 16

Multistage Delays Designing Fast Circuits

❑ Path Effort Delay DF =  f i D =  d i = DF + P

❑ Path Parasitic Delay P =  pi ❑ Delay is smallest when each stage bears same effort

fˆ = gi hi = F N
1

❑ Path Delay D =  d i = DF + P
❑ Thus minimum delay of N stage path is
1
D = NF N + P
❑ This is a key result of logical effort
– Find fastest possible delay
– Doesn’t require calculating gate sizes
6: Logical Effort CMOS VLSI Design 4th Ed. 17 6: Logical Effort CMOS VLSI Design 4th Ed. 18
 Gate Sizes Example: 3-stage path
❑ How wide should the gates be for least delay? ❑ Select gate sizes x and y for least delay from A to B

fˆ = gh = g CCoutin x
gi Couti y
 Cini = x
fˆ 45
A 8
❑ Working backward, apply capacitance x
y B
transformation to find input capacitance of each gate 45
given load it drives.
❑ Check work by verifying input cap spec is met.

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Example: 3-stage path Example: 3-stage path

x
❑ Work backward for sizes
y
x
45 y = 45 * (5/3) / 5 = 15
A 8
x
y B x = (15*2) * (5/3) / 5 = 10
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

x
Electrical Effort H = 45/8
Branching Effort B=3*2=6 y
x
45
45
Path Effort F = GBH = 125
fˆ = 3 F = 5
A P:
84
Best Stage Effort N: 4
P:
x 4 P:
N: 6 y 12 B
B
Parasitic Delay P=2+3+2=7 N: 3 45
45
Delay D = 3*5 + 7 = 22 = 4.4 FO4

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Best Number of Stages Derivation

❑ How many stages should a path use? ❑ Consider adding inverters to end of path
– Minimizing number of stages is not always fastest – How many give least delay? N - n1 ExtraInverters
Logic Block:
❑ Example: drive 64-bit datapath with unit inverter n1 n1Stages

D = NF N +  pi + ( N − n1 ) pinv
1
Path Effort F
Initial Driver 1 1 1 1
i =1
8 4 2.8
D 1 1 1

D = NF1/N + P = − F N ln F N + F N + pinv = 0
16 8
N
= N(64)1/N + N
=F
23 1
❑ Define best stage effort N

Datapath Load 64 64 64 64

N:
f:
D:
1
64
65
2
8
18
3
4
15
4
2.8
15.3
pinv +  (1 − ln  ) = 0
Fastest

6: Logical Effort CMOS VLSI Design 4th Ed. 23 6: Logical Effort CMOS VLSI Design 4th Ed. 24
 Best Stage Effort Sensitivity Analysis
❑ pinv +  (1 − ln  ) = 0 has no closed-form solution ❑ How sensitive is delay to using exactly the best
number of stages? 1.6
1.51

D(N) /D(N)
1.4
1.26

❑ Neglecting parasitics (pinv = 0), we find  = 2.718 (e) 1.2 1.15

1.0

❑ For pinv = 1, solve numerically for  = 3.59 (=6) ( =2.4)

0.0
0.5 0.7 1.0 1.4 2.0

N/ N

❑ 2.4 <  < 6 gives delay within 15% of optimal

– We can be sloppy!
– I like  = 4

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Example, Revisited Number of Stages

❑ Ben Bitdiddle is the memory designer for the Motoroil 68W86, ❑ Decoder effort is mainly electrical and branching
an embedded automotive processor. Help Ben design the
decoder for a register file.
A[3:0] A[3:0]
32 bits Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8
❑ Decoder specifications:
4:16 Decoder

16 words

16
Register File
– 16 word register file
– Each word is 32 bits wide ❑ If we neglect logical effort (assume G = 1)
– Each bit presents load of 3 unit-sized transistors Path Effort: F = GBH = 76.8
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
❑ Ben needs to decide: Number of Stages: N = log4F = 3.1
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?
❑ Try a 3-stage design

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Gate Sizes & Delay Comparison

Logical Effort: G = 1 * 6/3 * 1 = 2 ❑ Compare many alternatives with a spreadsheet
Path Effort: F = GBH = 154 ❑ D = N(76.8 G)1/N + P
Stage Effort: fˆ = F 1/ 3 = 5.36 Design N G P D
Path Delay: D = 3 fˆ + 1 + 4 + 1 = 22.1 NOR4 1 3 4 234
NAND4-INV 2 2 5 29.8
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
NAND2-NOR2 2 20/9 4 30.1
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 10 INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
y z word[0]
NAND2-INV-NAND2-INV 4 16/9 6 19.7
96 units of wordline capacitance
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
y z word[15] NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

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 Review of Definitions Method of Logical Effort
Term Stage Path 1) Compute path effort F = GBH
number of stages 1 N 2) Estimate best number of stages N = log 4 F
logical effort g G =  gi 3) Sketch path with N stages
1

electrical effort h= Cout

H=
Cout-path 4) Estimate least delay D = NF N + P
Cin Cin-path

fˆ = F N
1
branching effort b=
Con-path +Coff-path
Con-path B =  bi 5) Determine best stage effort
effort f = gh F = GBH
gi Couti
effort delay DF =  f i 6) Find gate sizes Cini =
fˆ
f

parasitic delay p P =  pi
delay d= f +p D =  d i = DF + P

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Limits of Logical Effort Summary

❑ Chicken and egg problem ❑ Logical effort is useful for thinking of delay in circuits
– Need path to compute G – Numeric logical effort characterizes gates
– But don’t know number of stages without G – NANDs are faster than NORs in CMOS
❑ Simplistic delay model – Paths are fastest when effort delays are ~4
– Neglects input rise time effects – Path delay is weakly sensitive to stages, sizes
❑ Interconnect – But using fewer stages doesn’t mean faster paths
– Iteration required in designs with wire – Delay of path is about log4F FO4 inverter delays
❑ Maximum speed only – Inverters and NAND2 best for driving large caps
– Not minimum area/power for constrained delay ❑ Provides language for discussing fast circuits
– But requires practice to master

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