EC29008: Analog Electronic Circuits Laboratory

Experiment III: Common collector (CC) amplifier and Cascaded CE-CC amplifier

Objective:
(i) Design a common collector amplifier
(ii) Simulate and observe performance of the CC amplifier
(iii) Design of directly coupled CE-CC amplifier
(iv) Observe advantages of CE-CC amplifier w.r.t. a CE amplifier through simulation
(v) Observe limitation of power efficiency of a class A amplifier

Part A: Design and simulation of Common Collector amplifier

Experiment Steps:
(i) A simple common collector amplifier circuit is shown in Fig. 3.a. Find suitable values
of the bias resistors R1, R2 and R3 such that, with Vcc = 12V, IC1 is near about 2mA,
IR1 ≤ 0.1× IC1 and VOUT is near about 5.4V. Connect an output load capacitor of 1 nF
(ii) Construct the circuit in simulator environment and observe the operating point
(vi) Through transient analysis, observe the maximum output signal swing (without
significant distortion) for an input signal having frequency of 100kHz.
(vii) Observe gain of the amplifier through transient simulation for 10 frequencies
spreading over a wide range of frequency [say, 100Hz to 20MHz].
(viii) Observe gain and phase plot of the amplifier through a.c. analysis over a wide range
of frequency [say, 20Hz to 100MHz].

Calculation Steps:
(i) Analyze the observed frequency response and find the voltage gain and the upper
cutoff frequency
(ii) Calculate the theoretical values of the voltage gain and the upper cutoff frequency of
the amplifier.

Vcc

Ic

R1
Q1

R2

Vout
R3

Fig. 3.a
Notes:
(i) Instead of the bias resistor R3, an active device (transistor Q2) may be used to define
the emitter current of transistor Q1. This biasing arrangement helps to get Ic of Q1
“independent” of the input d.c. voltage.
Part B: Design and simulation of cascaded CE-CC (directly coupled) amplifier
Experiment Steps:
(i) Cascade a CE amplifier designed before (in previous experiment) with the CC
amplifier without using any d.c. decoupling capacitor and remove the base bias circuit
of the CC stage as shown in Fig. 3.b.
(ii) Construct the circuit in the simulation environment and observe the operating points
of the transistors.
(iii) Observe gain of the cascaded amplifier through transient simulation for 10
frequencies spreading over a wide range of frequency [say, 100Hz to 20MHz].
(iv) Observe gain and phase plot of the cascaded amplifier (CE-CC) through a.c. analysis
over a wide range of frequency [say, 20Hz to 100MHz].
(v) Observe gain and phase plot of the CE amplifier (loaded with 1nF capacitor) through
a.c. analysis over the same frequency range and compare

Calculation Steps:
(i) Analyze the observed frequency response of the two circuits (CE and cascaded CE-
CC) and find their voltage gain and their upper cutoff frequencies
(ii) Calculate the theoretical values of the voltage gains and the upper cutoff frequencies
of the circuits (CE and cascaded CE-CC).
Vcc
Rc
R11
Ic

Ib Ib
R12

Fig. 4.b
Notes:
(i) Since the base current of CC stage is very small compare to the collector current of
CE stage, in this direct coupling configuration the CC stage does not load the CE
stage.
Part C: CE-CC amplifier driving a resistive load
Experiment Steps:
(i) Connect a 1 kΩ load resistor at the output node of the CC stage to a d.c. voltage
source of 5.4V (same as the d.c. voltage of the circuit)
(ii) Observe the d.c. operating point of the transistors
(iii) Apply an input signal having frequency in the mid-frequency range (say 10kHz) and
measure the maximum output signal swing (without distortion)

Calculation Steps:
(i) Analyze the change in the operating point of the transistors in the CC stage
(ii) Analyze the circuit driving resistive load to find theoretical values of maximum
output swing and compare it with the observed value in simulation.
(iii) Using the simulated observation, calculate the output signal power (without
significant distortion) and the power dissipation in the CC stage to find the power
efficiency of the CC stage