Microprocessors &

Microcontrollers
Lecture 5
24/01/2022
 Classification of Instruction Set
• Data Transfer Instruction
• Arithmetic Instruction
• Logical Instruction
• Branching Instruction
• Control Instruction
 Arithmetic Instruction

• These group of instruction perform arithmetic

operation such as addition, subtraction,
increment and decrement.
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
 Arithmetic Instruction
ADD R

Operation A=A+R
Machine Cycle OP
No. of bytes 1 byte
Flags All the flags are modified
Addressing mode Register Addressing mode
T-states 4
 Arithmetic Instruction
Suppose before the execution of the instruction ADD E
A = 10101111
E = 10110101
CY = 0 , S = 1, Z = 0 and P = 1
then after the execution of the instruction ADD E we get the following
result:
A=10101111
E=10110101
_____________________________
A=101100100
CY
The flags will be affected as;
CY = 1, S = 0 , Z = 0 and P = 0
 Arithmetic Instruction
ADD M

Operation A=A+M
Machine Cycle OP +MR
No. of bytes 1 byte
Flags All the flags are modified
Addressing mode Indirect Addressing mode
T-states 4+3 =7
 Arithmetic Instruction
ADC R

Operation A=A+R+CY
Machine Cycle OP
No. of bytes 1 byte
Flags All the flags are modified
Addressing mode Register Addressing mode
T-states 4
 Arithmetic Instruction
Suppose before the execution of the instruction ADC D
A = 10101001
D = 10111101
CY = 1, S = 1, Z = 0 and P = 1
then after the execution of the instruction ADD D we get the following
result:
CY = 1
A=10101001
D=10111101
_____________________________
A=1 01100111
CY
All flags will be affected.
 Arithmetic Instruction
ADC M

Operation A=A+M+CY
Machine Cycle OP + MR
No. of bytes 1 byte
Flags All the flags are modified
Addressing mode Indirect Addressing mode
T-states 4 +3 =7
 Arithmetic Instruction
ADI Data

Operation A=A+Data
Machine Cycle OP + MR
No. of bytes 2 byte
Flags All the flags are modified
Addressing mode Immediate Addressing mode
T-states 4 +3 =7
 Arithmetic Instruction
ACI Data
(Adds immediately the data with Carry)
Operation A=A+Data +CY
Machine Cycle OP + MR
No. of bytes 2 byte
Flags All the flags are modified
Addressing mode Immediate Addressing mode
T-states 4 +3 =7
 Arithmetic Instruction
DAD Rp
(Double Add )
Operation HL -- HL + Rp
Machine Cycle OP + BI + BI
No. of bytes 1 byte
Flags Only the carry flag is affected, No
other flags are modified to reflect
the result of operation
Addressing mode Register Addressing mode
T-states 4 +3 + 3 =10

where Rp stands for register pair. It may be B, D or H.

Rp as B represents B-C register pair,
Rp as D represents D-E register pair,
Rp as H represents H-L register pair.
 Arithmetic Instruction
For example before the execution of the instruction DAD D, we
have the following data in different registers.
DE = 2AB6 H
HL = 0127 H
After the execution of this instruction we HL = 2BDD H
Only carry flag will be affected in this instruction
 Arithmetic Instruction
SUB R

Operation A=A-R
Machine Cycle OP
No. of bytes 1 byte
Flags All the flags are modified to reflect
the result of subtraction
Addressing mode Register Addressing mode
T-states 4
 Arithmetic Instruction
Suppose before the execution of the instruction SUBD
A = 10101111, D = 10110101, CY = 0 , S = 1, Z = 0 and P =
1
then after the execution of the instruction SUBD we get
the following result:
A=10101111
D=10110101
_____________________________
A=111111010
CY
 Arithmetic Instruction
SUB M

Operation A=A-M
Machine Cycle OP + MR
No. of bytes 1 byte
Flags All the flags are modified to reflect
the result of subtraction
Addressing mode Indirect Addressing mode
T-states 4 +3 =7
 Arithmetic Instruction
SBB R
(Subtract register and borrow flag from accumulator)

Operation A=A-R-CY
Machine Cycle OP
No. of bytes 1 byte
Flags All the flags are modified to reflect
the result of subtraction
Addressing mode Register Addressing mode
T-states 4
 Arithmetic Instruction
Suppose before the execution of the instruction SBB H
A = 10101111, H = 10110101, CY = 0 , S = 1, Z = 0 and P =
1
then after the execution of the instruction SBB H we get
the following result:
A=10101111
H=10110101
CY = 1
____________________________
A=111111001
CY
 Arithmetic Instruction
SUI Data

Operation A=A- 8 bit data

Machine Cycle OP + MR
No. of bytes 2 byte
Flags All the flags are modified to reflect
the result of subtraction
Addressing mode Immediate Addressing mode
T-states 4 +3 =7
 Arithmetic Instruction
SBB M

Operation A=A-M-CY
Machine Cycle OP + MR
No. of bytes 1 byte
Flags All the flags are modified to reflect
the result of subtraction
Addressing mode Indirect Addressing mode
T-states 4 +3 =7
 Arithmetic Instruction
SBI Data
(Subtract immediate 8-bit data and borrow flag from accumulator)

Operation A=A-8 bit data -CY

Machine Cycle OP + MR
No. of bytes 2 byte
Flags All the flags are modified to reflect
the result of subtraction
Addressing mode Immediate Addressing mode
T-states 4 +3 =7
 Arithmetic Instruction
DAA
(Decimal Adjust Accumulator)
Operation A- sum in A is adjusted to
packed BCD format
Machine Cycle OP
No. of bytes 1 byte
Flags All the flags are modified to reflect
the result of subtraction
Addressing mode Implied Addressing mode
T-states 4

If the value of the low order 4 bits B3-B0 in the accumulator is greater
than 9 or if AC flag is set, then the instruction adds 6 to the low order 4
bits of the accumulator.
If the value of the high order 4 bits B7-B4 in accumulator is greater than 9
or if the carry flag is set, then the instruction add 6 to the high order 4 bits
of the accumulator.
 Arithmetic Instruction
• The DAA instruction is used with the add instructions eg. ADD, ADI etc. to
perform addition of a number in BCD. The add instruction add the two
BCD numbers in hexadecimal form and the DAA instruction converts this
hexadecimal result to BCD format.
• Eg. MVI A, 12H
ADI 39 H
DAA
A= 0001 0010
Data= 0011 1001
1st = 0100 1011
 Arithmetic Instruction
1st = 0100 1011
DAA(LSB) = + 0110
= 0101 0001 (51)

• The result in accumulator is 51 in BCD format

 Arithmetic Instruction
INR R
(Increment specified register content by 1)
Operation R=R +1
Machine Cycle OP
No. of bytes 1 byte
Flags Except carry all the flags are
modified to reflect the result
Addressing mode Register Addressing mode
T-states 4
 Arithmetic Instruction
• For example if Z = 0, S = 1, and CY = 0 and contents of register
is C = 1 1 1 1 1 1 1 1 , then after the execution of the
instruction INR C we have:
C=00000000
Z = 1, S = 0, and CY = 0
 Arithmetic Instruction
DCR R
(Decrement specified register content by one)
Operation R=R-1
Machine Cycle OP
No. of bytes 1 byte
Flags Except carry, all the flags are
modified to reflect the result
Addressing mode Register Addressing mode
T-states 4
 Arithmetic Instruction
INR M
(Increment content of memory location by 1)
Operation HL=HL +1
Machine Cycle OP +MR+MW
No. of bytes 1 byte
Flags Except carry all the flags are
modified to reflect the result
Addressing mode Indirect Addressing mode
T-states 4 +3+3
Arithmetic Instruction
 Arithmetic Instruction
DCR M
(Decrement specified memory content by 1)
Operation HL-HL - 1
Machine Cycle OP + MR + MW
No. of bytes 1 byte
Flags Except carry all the flags are
modified to reflect the result
Addressing mode Indirect Addressing mode
T-states 4 +3 +3
 Arithmetic Instruction
INX Rp
(Increment specified register pair by 1)
Operation Rp=Rp +1
Machine Cycle OP
No. of bytes 1 byte
Flags No flags are modified
Addressing mode Register Addressing mode
T-states 6

The register Rp is valid for BC, DE, HL or stack pointer

 Arithmetic Instruction
DCX Rp
(Decrement specified register pair by 1)
Operation Rp=Rp -1
Machine Cycle OP
No. of bytes 1 byte
Flags No flags are modified
Addressing mode Register Addressing mode
T-states 6

The register Rp is valid for BC, DE, HL or stack pointer

 Logical Instruction
• Logic group of instructions operate on registers, memory and
conditional flags.

• This group of instruction contains AND, OR, XOR,

complementing and comparing of data.
Logical Instruction
Logical Instruction
Logical Instruction
Logical Instruction
 Logical Instruction
ANA R
(AND register)
Operation A=A AND R
Machine Cycle OP
No. of bytes 1 byte
Flags S,Z and P reflect the result of
operation and CY flag is reset ad
AC flag is set
Addressing mode Register Addressing mode
T-states 4
 Logical Instruction
• ANA C
• A = 73 H C = C3 H CY = 1
A=01110011 CY = 1
C=11000011
__________________________
A=01000011 CY = 0
 Logical Instruction
ANA M
(AND Memory)

Operation A=A AND M

Machine Cycle OP + MR
No. of bytes 1 byte
Flags S,Z and P reflect the result of
operation and CY flag is reset ad
AC flag is set
Addressing mode Indirect Addressing mode
T-states 4+ 3
 Logical Instruction
A = 19 H H = 25 H L = 00 H
M2500 =37 H and CY = 1

A = 0 0 0 1 1 0 0 1 CY = 1
M2500 = 0 0 1 1 0 1 1 1
__________________________
A= 00010001 CY = 0
 Logical Instruction
ANI Data
Operation A=A AND data
Machine Cycle OP +MR
No. of bytes 2 byte
Flags S,Z and P reflect the result of
operation and CY flag is reset ad
AC flag is set
Addressing mode Immediate Addressing mode
T-states 4 +3 =7
 Logical Instruction
If A = AB H and CY = 1 before the execution of ANI 06 H,
Then after the execution of this instruction we have:
A = 1 0 1 0 1 0 1 1 CY = 1
data = 0 0 0 0 0 1 1 0
__________________________
A = 0 0 0 0 0 0 1 0 CY = 0
 Logical Instruction
ORA R
Operation A=A OR R
Machine Cycle OP
No. of bytes 1 byte
Flags S,Z and P reflect the result of
operation and CY and AC flag are
reset
Addressing mode Register Addressing mode
T-states 4
 Logical Instruction
Before the execution of the instruction ORA B
Let A = 73 H B = C3 H CY = 1
Then after the instruction is executed we get:
A = 0 1 1 1 0 0 1 1 CY = 1
B=11000011
__________________________
A = 1 1 1 1 0 0 1 1 CY = 0
 Logical Instruction
ORA M
Operation A=A OR M
Machine Cycle OP + MR
No. of bytes 1 byte
Flags S,Z and P reflect the result of
operation and CY and AC flag are
reset
Addressing mode Indirect Addressing mode
T-states 4 +3
 Logical Instruction
Let A = 19 H H = 21 H L = 00 H
M 2100 = 37 H and CY = 1 before the execution of the instruction
ORA M. Then after the instruction is executed we get:
A = 0 0 0 1 1 0 0 1 CY = 1
M 2100 = 0 0 1 1 0 1 1 1
__________________________
A = 0 0 1 1 1 1 1 1 CY = 0
 Logical Instruction
ORI Data
Operation A=A OR Data
Machine Cycle OP + MR
No. of bytes 2 byte
Flags S,Z and P reflect the result of
operation and CY and AC flag are
reset
Addressing mode Immediate Addressing mode
T-states 4 +3
 Logical Instruction
If A = AB H and CY = 1 before the execution of ORI 16 H, then
after the execution of this instruction we have:
A = 1 0 1 0 1 0 1 1 CY = 1
data = 0 0 0 1 0 1 1 0
__________________________
A=10111111 CY = 0
 Logical Instruction
XRA R
Operation A=A EX-OR R
Machine Cycle OP
No. of bytes 1 byte
Flags S,Z and P reflect the result of
operation and CY and AC flag are
reset
Addressing mode Register Addressing mode
T-states 4
 Logical Instruction
Let A = 73 H D = C3 H, CY = 1 before the execution of the
instruction XRA D. Then after the instruction is executed we get:
A=01110011 CY = 1
D=11000011
__________________________
A=10110000 CY = 0
 Logical Instruction
XRA M
Operation A=A EX-OR M
Machine Cycle OP +MR
No. of bytes 1 byte
Flags S,Z and P reflect the result of
operation and CY and AC flag are
reset i.e =0
Addressing mode Indirect Addressing mode
T-states 4 +3 =7
 Logical Instruction
XRI Data
Operation A=A EX-OR M
Machine Cycle OP +MR
No. of bytes 2 byte
Flags S,Z and P reflect the result of
operation and CY and AC flag are
reset i.e =0
Addressing mode Immediate Addressing mode
T-states 4 +3 =7
 Logical Instruction
CMA
Operation A= complement (A)
Machine Cycle OP
No. of bytes 1 byte
Flags No flags are modified
Addressing mode Implied Addressing mode
T-states 4

if A = 0B H before the execution of CMA instruction, then after the

execution of this instruction we have:
A=00001011
Complement (A) = 1 1 1 1 0 1 0 0
__________________________
A=11110100
 Logical Instruction
CMC
Operation CY= complement (CY)
Machine Cycle OP
No. of bytes 1 byte
Flags Only CY flag is complemented. No
other flags are affected.
Addressing mode Implied Addressing mode
T-states 4
 Logical Instruction
STC
Operation CY=1
Machine Cycle OP
No. of bytes 1 byte
Flags Only CY flag is set and no other
flags are modified.
Addressing mode Implied Addressing mode
T-states 4
 Logical Instruction
CMP R
Operation A=A Compare R
Machine Cycle OP
No. of bytes 1 byte
Flags S, AC and P reflect the result of
subtraction and CY and Z flag are
used to indicate the result of
comparison.
Addressing mode Register Addressing mode
T-states 4

The result of comparison is indicated by setting the flags as follow:

If A > R : CY = 0 and Z =0
If A = R : Z = 1 and CY = 0
If A < R ; CY =1, Z = 0
 Logical Instruction
Label Mnemonics Operand
MVI B, 00 H
MVI A, 09 H
LOOP INR B
CMP B
JNZ LOOP
Thank You