electronics
Article
A Reconfigurable Hybrid RF Front-End Rectifier for Dynamic
PCE Enhancement of Ambient RF Energy Harvesting Systems
Wen Xun Lian 1 , Jack Kee Yong 1 , Gabriel Chong 2 , Kishore Kumar Pakkirisami Churchill 1 ,
Harikrishnan Ramiah 3, *, Yong Chen 4 , Pui-In Mak 4 and Rui P. Martins 5
Citation: Lian, W.X.; Yong, J.K.;
Chong, G.; Churchill, K.K.P.; Ramiah,
H.; Chen, Y.; Mak, P.-I.; Martins, R.P.
A Reconfigurable Hybrid RF
Front-End Rectifier for Dynamic PCE
Enhancement of Ambient RF Energy
Harvesting Systems. Electronics 2023,
12, 175. https://doi.org/10.3390/
electronics12010175
Academic Editors: Andrea Ballo,
Gaetano Palumbo and Orazio Aiello
Received: 30 November 2022
Revised: 23 December 2022
Accepted: 26 December 2022
Published: 30 December 2022
Copyright: © 2022 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Electronics 2023, 12, 175. https://doi.org/10.3390/electronics12010175
1 Department of Electrical Engineering, Faculty of Engineering, University of Malaya,
Kuala Lumpur 50603, Malaysia
2 Nexperia R&D Penang, Bayan Lepas 11900, Malaysia
3 Centre of Research Industry 4.0 (CRI 4.0), Faculty of Engineering, University of Malaya,
Kuala Lumpur 50603, Malaysia
4 State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau,
Macau 999078, China
5 Insitituto Superior Técnico, Universidade de Lisboa, 1649-004 Lisboa, Portugal
* Correspondence: hrkhari@um.edu.my
Abstract: This paper presents a reconfigurable hybrid Radio Frequency (RF) rectifier designed to
efficiently convert AC RF power to DC voltages for an energy harvesting system. The proposed
reconfigurable rectifier adopts the advantage of low conduction loss in the switch-connected rectifier
and low reverse current loss in the diode-connection rectifier topology to enhance its power con-
version efficiency (PCE). Capable of reconfiguring into different rectifier topologies, the proposed
circuit can reconfigure into a switch-based cross-coupling differential drive (CCDD) at low input
power and a diode-based hybrid rectifier at higher input power for a wide dynamic range operation.
Designed and implemented on a CMOS 65 nm technology, the post-layout result records a peak PCE
of 88.7% and a wide PCE dynamic range (PDR) of 16 dBm for PCE >40%. The proposed circuit also
demonstrates a −21 dBm sensitivity output across a 1 MΩ output load.
Keywords: RF energy harvesting (RFEH); CMOS; RF-DC; reconfigurable rectifier; CCDD; wide
dynamic range
1. Introduction
With the increasing demand for self-powered autonomous sensors for the Internet of
Things (IoT), energy harvesting will become a key enabling technology with widespread
deployment. The uprising of radiofrequency (RF) has enabled widespread wireless com-
munication in many environments, such as in urban cities, offices, and homes. Due to this,
the opportunity to harvest the available RF energy in the environment presents a new form
of energy source in the upcoming IoT growth.
Integrating miniaturized sensors through complementary integrated circuits to harvest
ambient RF energy adds to challenges. The varying nature of ambient RF, nonuniform de-
ployment of the RF services, and the high frequency spreading loss impede the performance
of RFEH [1]. A reasonable tradeoff of power-conversion-efficiency (PCE) and sensitivity of
the harvester is essential to attain a practical level of power harvesting. Second, the dynamic
characteristic of RF energy adds to the design challenge in PCE performance regardless of
the harvested power level. Hence, there is a need to improve the PCE dynamic range of the
RF energy harvesting (RFEH) system.
There have been many prior-art design schemes and techniques to improve the peak
PCE of the CMOS rectifier, generally by reducing the forward conduction loss and the
reverse current loss effected by the transistors. The forward conduction loss is the power
loss caused by turning on the transistors with on resistance [2]. There is a high internal
https://www.mdpi.com/journal/electronics
Electronics 2023, 12, 175 2 of 15

resistance from the threshold voltage of transistors. Techniques, such as threshold com-
pensation [3] and cancellation [4], for the Dickson topology rectifier, and self-body biasing
with an additional coupling capacitor technique in the cross-coupled differential drive
(CCDD) rectifier [5], focus on reducing the conduction loss to enhance PCE. Reverse current
loss is in effect due to non-proper turn-off in the transistors [6], which causes the driving
current to flow back into the previous rectifier stage. A dynamic gate biasing technique can
concurrently reduce the forward and reversion loss, but it requires an additional pumping
stage in the implementation [7]. An alternate solution for restricting reverse current is
replacing the transistor with a diode, forcing the current flow in a single direction. However,
the large threshold voltage from a diode will result in a higher conduction loss which is
undesirable, especially in a low input power range.
Due to the nature of switch and diode rectifier connections, CCDD has a large inherent
reverse current, and the threshold voltage of CMOS limits the PCE performance of Dickson
rectifier topologies. Therefore, the CCDD rectifier typically offers superior PCE at low RF
input power, whereas the Dickson topology offers high PCE during high input RF power.
Both topologies exhibit tradeoffs of a narrow high PCE dynamic range.
Various reported state-of-the-art studies have proposed techniques to enhance the peak
PCE of the RFEH system, yet only a handful of these focus on improving the rectifier’s PCE
dynamic range (PDR) [5,8–14]. In [5,15], diode-connected MOSFETs were added to stem
the reverse leakage current. However, current leakage in the diodes at low input RF power
degrades the PCE [15]. Although the dynamic range is extended, the PCE curve shifted
towards the right, where peak PCE occurs during high input RF power. To extend the PDR
of a CCDD rectifier, an adaptive self-biasing method is applied to control the conduction
of the PMOS at high input RF power [8,9]. It extends the high PCE range by reducing the
reverse current leakage, yet with a penalty of suppressing the forward conduction at low
input RF power, concurrently reducing the rectifier’s peak PCE. A dual-path CCDD rectifier
was proposed in [10] to enhance the PDR. It switches between high and low power paths
using a control circuit and a reference path. However, integrating multiple path rectifiers
and the control circuit consumes the rectifier’s input power and impairs the achievable
PCE. The solution also adopts an off-chip impedance matching network (IMN) at 900 MHz
using an off-chip, which inhibits the System-on-Chip (SoC) applications. Alternatively, [11]
adopted a reconfigurable Dickson topology by adaptively configuring the number of stages
between 6 and 12 stages for low and high input power, respectively. It increases the PDR
compared to the conventional Dickson topology. Nevertheless, due to the diode-connected
configuration, it achieves low peak PCE and sensitivity compared to the aforementioned
CCDD rectifier configuration. Another configuration is improvised on a CCDD topology
to switch between 1 and 2 stages for low and high power, respectively [12]. However, the
peak PCE is low because of high reverse leakage. The reconfigurable rectifier in [13] shows
the PCE of different rectifier configurations, known as conventional CCDD (all switches),
differential Dickson (all diodes), and hybrid switches and diodes (NMOS diodes, PMOS
switches, and vice versa). The work illustrated a high PCE performance across a wide
RF harvesting range by switching between rectifier configurations across low and high
input RF power. However, the control circuit was absent in the work, as manual switches
were used as a proof of concept. Such configuration switching between rectifier topologies
prevents concurrent suppression of forward conduction at low input RF harvesting and
upholds a wide PDR.
To overcome the limitations of related prior-art works, an enhanced PDR RFEH system
is proposed. The system consists of a reconfigurable rectifier, an auxiliary path rectifier, a
comparator, and an on-chip impedance matching network (IMN). Section II provides the
architectural overview of the RFEH system. Section III describes each individual circuit that
is integrated in constructing the entire RFEH system. Post-layout and simulation results
are presented in Section IV, and the summary in Section V concludes the article.
Electronics 2023, 12, x FOR PEER REVIEW 3 of 16

circuit that is integrated in constructing the entire RFEH system. Post-layout and simula-
Electronics 2023, 12, 175 tion results are presented in Section IV, and the summary in Section V concludes the arti-
3 of 15
cle.

2. 2.
RFEH System
RFEH Architecture
System Architecture
2.1. Rectifier
2.1. Topologies
Rectifier Topologies
Each
Eachrectifier
rectifierdesign scheme
design scheme shown
shown inin
Figure
Figure 1 has anan
1 has optimal
optimalworking
working range, where
range, where
it it
achieves
achieves thethe
peak
peakPCE
PCE at at
a specific
a specificpower
power level. The
level. Thedynamic
dynamic change
change of of
power
powerin in
thethe
ambient
ambient affects thethe
affects PCE
PCEof of
thethe
rectifier. Selected
rectifier. Selecteddesign
design schemes
schemesfunction
functionefficiently when
efficiently when
rectifying
rectifying lowlowRFRF power,
power,whereas
whereas others
others achieve
achieve better
betterperformance
performance at at
high
highharvesting
harvesting
power.
power. Therefore,
Therefore, several conventional
several conventionalrectifiers are examined
rectifiers to efficiently
are examined designdesign
to efficiently a rec- a
rectifier
tifier that achieves
that achieves high high
PCE PCE at a wide
at a wide inputinput
power power fluctuation.
fluctuation.

RF+ RF+ RF+ RF+

MNa,n MPa,n MNa,n MPa,n MNa,n MPa,n MNa,n MPa,n

IN OUT IN OUT IN OUT IN OUT
MNb,n MPb,n MNb,n MPb,n MNb,n MPb,n MNb,n MPb,n

RF- RF- RF- RF-

(a) (b) (c) (d)

Figure 1. 1.
Figure TheThedifferent
differentconfigurations
configurations of
of a rectifier:
rectifier: (a)
(a)conventional
conventionalCCDD,
CCDD, (b)(b) diode-connected
diode-connected dual
dual path
path rectifier,
rectifier, (c) hybrid
(c) hybrid topology
topology (NDPS),
(NDPS), (d) (d) hybrid
hybrid topology
topology (NSPD).
(NSPD).

Figure
Figure 1a1a shows
shows thethe
CCDD CCDD rectifier.
rectifier. The The rectifier
rectifier receives
receives differential
differential signals
signals and
and ac-
accumulates a common-mode gate voltage to bias the MOSFETs.
cumulates a common-mode gate voltage to bias the MOSFETs. It reduces the threshold It reduces the threshold
voltage
voltage ofof
thetheMOSFETs.
MOSFETs.The The CCDD
CCDD rectifier
rectifier operates
operates better
better in in subthreshold
subthreshold [16]
[16] and
and
threshold regions than other rectifier topologies. Therefore, the
threshold regions than other rectifier topologies. Therefore, the CCDD rectifier achieves CCDD rectifier achieves
peak
peak PCE
PCE at at a low
a low input
input power
power level.
level. OnOn thethe contrary,
contrary, at at high
high input
input power,
power, thethe CCDD
CCDD
rectifier
rectifier suffers
suffers from
from reverse
reverse leakage
leakage duedueto to
thethe bidirectionality
bidirectionality of of
thethe CMOS
CMOS devices
devices [14].
[14].
The subsequent rectifier topology is a diode-based configuration.
The subsequent rectifier topology is a diode-based configuration. Figure 1b shows the four Figure 1b shows the
four diode-connected MOSFETs to rectify the differential signals.
diode-connected MOSFETs to rectify the differential signals. Due to the threshold voltage Due to the threshold
ofvoltage
the two of the two diode-connected
diode-connected transistors in transistors
each signal in path,
each signal path, this
this topology hastopology
a high drop-has a
high dropout voltage. In contrast with CCDD topology, the diode-based
out voltage. In contrast with CCDD topology, the diode-based configuration achieves low configuration
achieves low PCE at a low input power due to the forward voltage drop at the diodes.
PCE at a low input power due to the forward voltage drop at the diodes. However, this
However, this connection significantly prevents the reverse current flow, achieving high
connection significantly prevents the reverse current flow, achieving high PCE at a high
PCE at a high input power level. The other configuration is a hybrid switch-diode-based
input power level. The other configuration is a hybrid switch-diode-based rectifier, as il-
rectifier, as illustrated in Figure 1c,d. It consists of two MOSFETs in diode configuration
lustrated in Figure 1c,d. It consists of two MOSFETs in diode configuration and the other
and the other two in switch configuration. In one signal path, there is a diode and a switch.
two in switch configuration. In one signal path, there is a diode and a switch. Therefore,
Therefore, the dropout voltage and reverse leakage are reduced compared to the diode
the dropout voltage and reverse leakage are reduced compared to the diode and CCDD
and CCDD configurations, respectively. The hybrid configuration merges the pros of the
configurations, respectively. The hybrid configuration merges the pros of the diode con-
diode connected and CCDD topology. Figure 2 depicts the performance of various rectifier
nected and CCDD topology. Figure 2 depicts the performance of various rectifier topolo-
topologies extracted from [13]. The figure shows that the CCDD rectifier achieves high PCE
gies extracted from [13]. The figure shows that the CCDD rectifier achieves high PCE at a
at a low input power and degrades drastically at a high input power. It is demonstrated
low input
that the power
hybridand degrades drastically
configuration at a high
obtained higher PCEinput
thanpower. It is demonstrated
the diode-based rectifierthat
at all
theinput
hybrid configuration
power levels. At aobtained
low input higher
power PCE thanthe
level, theCCDD
diode-based
performs rectifier
better,atwhereas
all inputthe
power
hybridlevels. At a low
surpasses CCDD input
at power
a high level,
input the
powerCCDD performs better, whereas the hybrid
level.
surpasses CCDD at a high input power level.
2.2. Proposed Circuit Architecture
The aim of the proposed front-end RFEH is to obtain high PCE at a wide input power
range to improve the practicality of an RFEH system. By employing standard CMOS,
different configurations can be achieved by altering the transistors’ gate connection. Based
on the analysis in Section 2.1, a combination of CCDD and a hybrid topology would provide
a wide PDR, as illustrated in Figure 3. The proposed front-end RFEH system consists of an
IMN to achieve maximum power transfer and reduce power reflection, the main rectifier for
scavenging the RF to DC, an auxiliary rectifier for a constant comparison of output voltage,
and a control logic circuit as the adaptive switching control. Figure 4a,b illustrate the
rectifier configuration during low input RF power and high RF input power, respectively,
where the top architecture block diagram of the front-end is described in Figure 5.
 PC
40
30
CCDD
20 Hybrid(NDPS)
Hybrid(NSPD)
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2023, 12,
12, 175
x FOR PEER REVIEW
10 Diode-Based
Electronics 44 of
of 15
16
0
0 2 4 6 8 10 12 14
PIN (dBm)
90
Figure 2. Simulated PCE of the four rectifier configurations [13].
80
70
2.2. Proposed Circuit Architecture
60 aim of the proposed front-end RFEH is to obtain high PCE at a wide input power
The

PCE (%)
range to50 improve the practicality of an RFEH system. By employing standard CMOS, dif-
ferent configurations
40 can be achieved by altering the transistors’ gate connection. Based
on the analysis in Section 2.1, a combination of CCDD and a hybrid topology would pro-
30
vide a wide PDR, as illustrated CCDDin Figure 3. The proposed front-end RFEH system consists
20 Hybrid(NDPS)
of an IMN to achieve maximum power transfer and reduce power reflection, the main
Hybrid(NSPD)
rectifier10for scavenging the RF Diode-Based
to DC, an auxiliary rectifier for a constant comparison of
output voltage,
0 and a control logic circuit as the adaptive switching control. Figure 4a,b
illustrate0the rectifier
2 4 6 8
configuration 10
during 12 14
low input RF power and high RF input power,
respectively, where the top PIN (dBm)
architecture block diagram of the front-end is described in
Figure 5. 2. Simulated PCE of the four rectifier configurations
Figure configurations [13].
[13].

2.2. Proposed Circuit Architecture Extended

PCE PCE PDR PCE
The aim of the proposed front-end RFEH is to obtain high PCE at a wide input power
range to improve the practicality of an RFEH system. By employing standard CMOS, dif-
ferent configurations can be achieved by altering the transistors’ gate connection. Based
on the analysis in Section 2.1, a combination of CCDD and a hybrid topology would pro-
vide a wide PDR, as illustrated in Figure 3. The proposed front-end RFEH system consists
of an IMN to achieve maximum power transfer and reduce power reflection, the main
Electronics 2023, 12, x FOR PEER REVIEW
rectifier for PINscavenging the RF to DC,PINan auxiliary rectifier forPaIN constant comparison 5 of 16
of
Figure output
Figure 3.voltage, and aofcontrol
Conceptualization
3. Conceptualization the thelogic
ofPCE PCE circuit
curve
curve onas
on the the
the adaptive
proposed
proposed switching
reconfigurable
reconfigurable control.
rectifier. Figure 4a,b
rectifier.
illustrate the rectifier configuration during low input RF power and high RF input power,
Main Rectifier Main Rectifier
respectively, where the top architecture block diagram of the front-end is described in
Figure RF+ 5. RF+

IMN IMN
TG1,n TG1,n Extended
L
MNa,n
TG2,n PCE MPa,n
PCE L PCETG
MNa,n
2,n
M
PDROUT
Pa,n

VOUT VOUT
IN MNb,n VX OUT IN MNb,n VX
C C
TG3,n TG3,n
MPb,n MPb,n
TG4,n CL RL TG4,n CL RL

VY VY

RF- RF-

Auxiliary Rectifier
PIN PIN Auxiliary Rectifier
PIN
Figure 3. Conceptualization of the PCE curve on the proposed reconfigurable rectifier.
VY

VY
VX

VX

VAUX VAUX

VREF VREF
Comparator Comparator

(a) (b)

Figure4.4.Top
Figure Toparchitecture
architectureofofthe
theproposed
proposedfront-end
front-end RFEH:
RFEH: (a)
(a) at
at low
low input
input power,
power, (b)
(b) at
at aa high
high
input power.
input power.

3.3.Circuit
CircuitDescription
Description
3.1.
3.1.Main
MainRectifier
Rectifier
Figure
Figure5a5adepicts
depictsthethemain
mainrectifier circuit.
rectifier It It
circuit. has three
has threecascade stages
cascade ofof
stages reconfigurable
reconfigura-
CCDD topology rectifiers. In each stage, there are four transmission gates (TG1-TG4).
ble CCDD topology rectifiers. In each stage, there are four transmission gates (TG1-TG4). The
transmission gates are controlled by the control logic circuit. To increase the sensitivity
The transmission gates are controlled by the control logic circuit. To increase the sensitiv- of
the
ityrectifier, a low-threshold-voltage
of the rectifier, transistor
a low-threshold-voltage is used.
transistor is The
used.two
Therectifying NMOS
two rectifying NMOShave
W/L
haveofW/L
30 while
of 30 the PMOS
while has W/L
the PMOS hasofW/L
60, of
because the hole
60, because themobility of PMOS
hole mobility is twoistimes
of PMOS two
times smaller than the electron mobility of NMOS. For State 1, where the input power is
low, TG1 and TG2 are switched on, while TG3 and TG4 are off. It forms a conventional
CCDD. For State 2, where the input power is high, TG3 and TG4 are on, and TG1 and TG2
are off. With this configuration, the PMOS is in a diode-connected state, and NMOS is in
Electronics 2023, 12, 175 5 of 15

smaller than the electron mobility of NMOS. For State 1, where the input power is low,
TG1 and TG2 are switched on, while TG3 and TG4 are off. It forms a conventional CCDD.
For State 2, where the input power is high, TG3 and TG4 are on, and TG1 and TG2 are off.
With this configuration, the PMOS is in a diode-connected state, and NMOS is in a switch
configuration. It forms a hybrid rectifier topology similar to Figure 1d. PMOS is connected
directly to the output, so the reverse current is higher. Therefore, the diode connections are
Electronics 2023, 12, x FOR PEER REVIEW
designed at PMOS. The two switches in the hybrid topology contribute to high forward 6 of 16

conduction at high input power, and the two diodes are in a reverse-bias state to control
the high current flow from the output.

(c) IMN (a) Main Rectifier

L1 CP CP CP

MPa,1 MPa,2 MPa,3

TG1,1 TG1,2 TG1,3
TG2,1 TG2,2 TG2,3
MNa,1 MNa,2 MNa,3 VOUT
MNb,1 VX MNb,2 VX MNb,3 VX
C TG3,1 TG3,2 TG3,3
TG4,1 TG4,2 TG4,3 CL RL
MPb,1 MPb,2 MPb,3
VY VY VY

CP CP CP
L2
VAUX
VREF
CP CP
Cfilter

MC3 MC4 MC7 MC9 MC11 MC13

M1,1 M1,2

M3,1 M2,1 M3,2 M2,2 MC1

VX
VY
M4,1 M4,2
CP CP MC2 MC5 MC6 MC8 MC10 MC12 MC14

(b) Auxiliary Rectifier (d) Comparator

Figure 5. The schematic of the proposed reconfigurable hybrid rectifier with (a) main rectifier,
(b) auxiliary rectifier, (c) impedance matching network (IMN), and (d) comparator.
Figure 5. The schematic of the proposed reconfigurable hybrid rectifier with (a) main rectifier, (b)
auxiliary rectifier,
Unlike (c)diode
a full impedance matching
topology network
in [11], (IMN),
where and (d) comparator.
the forward conduction is suppressed by
the diodes, the proposed scheme balances forward conduction and controls reverse leakage.
Unlike awith
In contrast full diode topology
[8,9], the in [11],
proposed wherewill
rectifier the not
forward conduction
reduce forward is suppressedatby
conduction low
the diodes, the proposed scheme balances forward conduction and controls
input power as it is a conventional CCDD rectifier. At the same time, the peak reverse
PCEleak-
occurs
age. In input
at low contrast with which
power, [8,9], the proposedfor
is favorable rectifier will
far-field not reduce
ambient forward
energy conduction at
harvesting.
low input power as it is a conventional CCDD rectifier. At the same time, the peak PCE
3.2. Auxiliary
occurs Rectifier
at low input power, which is favorable for far-field ambient energy harvesting.
As the proposed hybrid rectifier will be reconfigured into different topologies at
3.2. Auxiliary
different Rectifier
input power, it is necessary to detect the input power level to determine the
As thepoint
switching proposed
for the hybrid rectifier
rectifier’s will bereconfiguration.
topology reconfigured into different
The idea is topologies
to compareata dif-
target
ferent
voltageinput power,
signal which it is necessarythe
represents to detect
input the input
power power
level withlevel to determine
the switching thevoltage.
point switch- If
ing
thepoint
targetfor the rectifier’s
voltage is lowertopology reconfiguration.
than the switching The ideathe
point voltage, is to compare
input power a target volt-
is considered
age
low,signal
and which represents
the circuit will bethereconfigured
input powerinto levelCCDD
with the switchingSimilarly,
topology. point voltage.
if theIf target
the
target
voltagevoltage is lower
is greater thanthan the switching
the switching pointpoint voltage,
voltage, the the input
circuit willpower is considered
be reconfigured into
low, and the circuit will
switch-diode-based topology. be reconfigured into CCDD topology. Similarly, if the target volt-
age isThe
greater
inputthan the switching
voltage RF−voltage,
(RF+ andpoint the circuit
) is not suitable to will be reconfigured
be used as the targetinto switch-
signal, which
diode-based
represents the topology.
input power level, due to the large fluctuation in the AC voltage. The main
The input voltage (RF+ and RF−) is not suitable to be used as the target signal, which
represents the input power level, due to the large fluctuation in the AC voltage. The main
rectifier’s DC output is also unsuitable as the target signal because its output voltage var-
ies in different topologies.
An auxiliary rectifier is used in this work to furnish a stable voltage to determine the
Electronics 2023, 12, 175 6 of 15

rectifier’s DC output is also unsuitable as the target signal because its output voltage varies
in different topologies.
An auxiliary rectifier is used in this work to furnish a stable voltage to determine the
Electronics 2023, 12, x FOR PEER REVIEW 7 of 16
rectifier’s switching point. The auxiliary rectifier offers an independent output voltage
from the main rectifier. In other words, the output voltage of the auxiliary rectifier (V AUX )
will not be affected by the change in the main rectifier’s topology; hence, it is ideally used
in triggering
triggeringthethetopology
topologyswitching.
switching.AAconventional
conventionalthree-stage
three-stageCCDD
CCDD is implemented
is implemented as
the auxiliary
as the rectifier
auxiliary in this
rectifier work,
in this offering
work, an independent
offering DC DC
an independent voltage representing
voltage the
representing
input power
the input level.
power As shown
level. As shownin Figure 6, the6,Vthe
in Figure AUX portrays
VAUX a linear
portrays relationship
a linear withwith
relationship the
increment in theinPthe
the increment IN . The
PIN. performance
The performance of theofCCDD topology
the CCDD is better
topology betterVwhen
is when AUX isVlower
AUX is
than
lower800 mV,800
than while
mV,the performance
while of the diode-based
the performance topology istopology
of the diode-based better when V AUXwhen
is better rises
beyond 800 mV. Based on this relationship, we can
VAUX rises beyond 800 mV. Based on this relationship, we can assign V AUX = 800 mV as the rectifier’s
assign VAUX = 800 mV as the
topology
rectifier’sreconfiguration switching switching
topology reconfiguration point. point.

1.4 40
Switching point
= 0.8V
1.2
30
1.0
VAUX

PCE (%)
CCDD
VAUX (V)

0.8 Switch-Diode 20
0.6

0.4 10

0.2
0
−25 −20 −15 −10 −5 0 5
PIN (dBm)

Figure 6.
Figure 6. Relationship
Relationshipbetween
betweeninput
input power,
power, auxiliary
auxiliary charge
charge pump
pump voltage,
voltage, andswitching
and the the switching
point
point of the rectifier’s topology.
of the rectifier’s topology.

3.3. Impedance Matching Network

In front-end RFEH, the signal scavenged directly from the antenna to the rectifier
results in high
high reflection
reflection and
and power
powerloss.
loss.Thus,
Thus, anan IMN
IMN is essential
is essential to reduce
to reduce power
power re-
reflection
flection and andprovide
providepassive
passiveamplification.
amplification.InInaa perfect
perfect match
match condition,
condition, the the antenna’s
antenna’s
resistance
resistance equals
equalstotorectifier’s
rectifier’sequivalent
equivalent resistance,
resistance, while thethe
while reactance
reactance of the
of antenna and
the antenna
rectifier is in the conjugate. The matched impedance condition only
and rectifier is in the conjugate. The matched impedance condition only occurs at the res-occurs at the resonance
frequency, as the reactance
onance frequency, is a frequency-dependent
as the reactance parameter.parameter.
is a frequency-dependent At the resonance frequency,
At the resonance
maximum power transfer occurs. As the frequency deviates further
frequency, maximum power transfer occurs. As the frequency deviates further from the from the resonance
frequency, the matching
resonance frequency, theismatching
progressively poor, along poor,
is progressively with increased
along withpower reflection.
increased powerThere-
performance of the matching
flection. The performance is evaluated
of the matching is byevaluated
the reflection
by the coefficient,
reflection Scoefficient,
11, of the circuit.
S11, of
The lower the
the circuit. TheS11 , the the
lower better
S11,the
thematching. To realize the
better the matching. matching,
To realize the impedance
the matching, of the
the imped-
rectifier is first simulated. The rectifier can be modeled as a series or
ance of the rectifier is first simulated. The rectifier can be modeled as a series or parallelparallel resistor and
capacitor set [17].
resistor and capacitor set [17].
In
In most
mostcases,
cases,the
thesimulated
simulated impedance
impedance is in
is series form,
in series but but
form, it is it
transformable
is transformableas longas
as the circuit maintains the same quality factor, Q. Figure 7 demonstrates the conversion of
long as the circuit maintains the same quality factor, Q. Figure 7 demonstrates the conver-
the rectifier model from series or parallel or vice versa. The conversion can be performed
sion of the rectifier model from series or parallel or vice versa. The conversion can be per-
by referring to Equations (1)–(5), where QS and QP are the Q of the rectifier model in series
formed by referring to Equations (1)–(5), where QS and QP are the Q of the rectifier model
and parallel, respectively.
in series and parallel, respectively.
QS = Q P = Q (1)
𝑄 = 𝑄1 = 𝑄 (1)
QS = (2)
ωCS1RS
𝑄 = (2)
Q P = ωC 𝜔𝐶 𝑅
P RP (3)

R P =𝑄RS=1𝜔𝐶 + Q𝑅2 (3)

 
(4)
𝑅 = 𝑅 (1 + 𝑄 ) (4)
𝐶
𝐶 =
1 (5)
1+
𝑄
Electronics 2023, 12, 175 7 of 15

Electronics
Electronics2023,
2023,12,
12,xxFOR
FORPEER
PEERREVIEW
REVIEW 88ofof1616
CS
CP = (5)
1 + Q12

RRPP
RRSS CCSS CCPP
Series
Seriesmodel
model Parallel
Parallelmodel
model
Figure
Figure7.7.
Figure 7.Rectifier’s
Rectifier’sequivalent
equivalentimpedance
impedancemodel
modelinterchangeable
model interchangeablefrom
interchangeable fromseries
from seriesto
series toparallel.
to parallel.
parallel.

There
There
Thereare are four
arefour configurationsofofaaconventional
fourconfigurations conventionalL-network
conventional L-network[18],
L-network [18],as
[18], asshown
as shown
shown ininin
Figure
Figure
Figure 8.
It is categorized
8.8.ItItisiscategorized into
categorizedinto two
intotwo categories,
twocategories, with
categories,with either
witheitherthe
eitherthereal impedance
thereal
realimpedance of the
impedanceofofthe source,
thesource,R
source,
S being
RRS S
larger
being
beinglargeror smaller
larger or than the
orsmaller
smaller than
thanrectifier’s
the equivalent
therectifier’s
rectifier’s seriesseries
equivalent
equivalent real impedance,
series real
realimpedance,
impedance,RL . Each category
RRL.L.Each
Each cat-
cat-
has
egory
egory a high
hasaor
has lowor
ahigh
high pass
orlow
lowtopass
block
pass totoor passor
block
block the DC the
orpass
pass signal.
theDC DCA shuntAA
signal.
signal. capacitor
shunt and series
shuntcapacitor
capacitor and
andinductor
series
series
pass
inductor DC. On the contrary, a series capacitor and shunt inductor
inductor pass DC. On the contrary, a series capacitor and shunt inductor pass DC. Inmost
pass DC. On the contrary, a series capacitor and shunt pass
inductor DC. In
pass most
DC. cases,
In most a
series
cases, acapacitor
series is used
capacitor to
is prevent
used to the
preventbackflow
the of
backflowsignal of from
signal
cases, a series capacitor is used to prevent the backflow of signal from the rectifier to thethe rectifier
from the to the
rectifier source.
to the
However,
source.
source.However, since the
However, proposed
since
since the system has
theproposed
proposed a diode
system
system hasconfiguration,
has aadiode it is sufficient
diodeconfiguration,
configuration, to block the
ititisissufficient
sufficient toto
high
block
blockthe reverse
thehigh current.
highreverse Therefore,
reversecurrent. the
current.Therefore, IMN
Therefore,the design
theIMN is
IMNdesignfocused on
designisisfocusedmatching
focusedon the
onmatching rectifier
matchingthe and
therec-
rec-
antenna
tifier impedances only.
tifierand andantenna
antennaimpedances
impedancesonly. only.

LL RRSS>>RRLL LL RRSS<<RRLL
CC CC
RRSS RRSS RRSS RRSS
CC RRLL LL RRLL CC RRLL LL RRLL

(a)
(a) (b)
(b) (c)
(c) (d)
(d)
Figure
Figure8.8.Four
Fourconfigurations
Four configurations ofofof
L-network:
L-network:(a) Low
(a)(a)
Low pass
pass CL
CLfor forRfor
RS S>>R
RRL,L>,(b)
RLHigh
(b) pass
passLC for RRS S>for
Figure configurations L-network: Low pass CL S (b) ,High High LC forLC
pass >
RRL,L,(c)
(c)Low
Lowpass
passLC
LCfor
forRRS S<<RRL,L,(d)
(d)High
Highpass
pass CL
CL for RRS S<<RRL.L.
for
RS > RL , (c) Low pass LC for RS < RL , (d) High pass CL for RS < RL .

The
Thesimulation
The simulationof
simulation ofthe
of therectifier’s
the rectifier’simpedance
rectifier’s impedanceshows
impedance showsthat thatthe
thereal
realimpedance
real impedanceisis
impedance ismuch
much
much
larger
largerthan
larger thanthe
than theantenna’s
the antenna’s(standard
antenna’s (standard50
(standard 50 Ω).
50Ω).Ω).Consequently,
Consequently,the theL-network
the L-networkthat
L-network thatmatches
that matchesthe
matches the
the
condition
condition
condition will
will be
be Figure
Figure 8c
8c or
orFigure
Figure
Figure 8c or Figure 8d. 8d.
8d. For
For aafair
fair comparison,
comparison, the
therectifier
rectifiersizing,
sizing, load,
load,
capacitance,
capacitance,inductor
capacitance, inductorsizing,
sizing,and andQQare arefixed.
fixed.Figure
fixed. Figure99shows showsthetheresult
resultofofPCE
PCEfor
PCE forthe
for the
the
RFEH
RFEH front-end
RFEH front-end when
front-end when when CL CLCL andand LC
and LC networks
LC networks
networks are are employed with the proposed
are employed with the proposed rectifier. rectifier.
rectifier.AtAt
At
the
thematching
the matching frequency,
matchingfrequency,
frequency,900 900
900 MHz,
MHz,
MHz, the
the L-C
the L-C
L-C network
network
network hashas aahigher
a higher
has peak
peak
higher andand
peak andoverall
overall PCEPCE
overall than
PCE
than
the
thanC-Lthe C-L
C-Lnetwork.
thenetwork. Therefore,
Therefore,
network. Therefore,the IMNthe
theIMN
in
IMN ininFigure
Figure 8c is 8c
Figure 8cisisselected
selected for
for the
selected the
thematching.
matching.
for matching.
In this work, an on-chip L network was used by cascading four inductors in series
to40 40
increase the inductance while maintaining
37.87%
a high-quality factor. It was tuned to match
37.87%Peak
PeakPCE
PCE
900 MHz, between a 50 Ω antenna and the proposed reconfigurable rectifier with the
at 35
35 33.65%
auxiliary rectifier. Considering 33.65%Peak
Peak
thatPCE
PCE
the Q of the inductor affects the matching parameter,
3030
the following equations were deduced to obtain matching. A resistor was placed in
2525 with the inductor to represent the parasitic of the inductor. From (8) and (10), the
series
PCE(%)
PCE(%)

parameter of matching components can be calculated based on the desired harvesting

2020
frequency. The matching capacitor is assumed to be ideal. Figure 10 exemplifies the
LC-network
LC-network
1515 for the
model PDRmatching
= condition, CL-network
CL-network
where RL and CL are the equivalent impedance of the
PDR =
proposed −9−9dBm
rectifier
dBm and auxiliary rectifier, RA is the antenna resistance, L and C are the
1010
matching network’s passive components, and RP represents the parasitic of the matching
55
inductor. ThePDR PDR==
auxiliary rectifier, integrated in parallel with the main rectifier, reduced the
−10
−10dBm
dBm
equivalent
00 impedance of the rectifiers (RL and CL) to be matched, hence reducing the
−25 −20
−25 matching
−20 −15
−15 −10
−10 −5−5 0 55
required transformation
PPININ(dBm)
(dBm) [19].0 To match, Re(Z1 ) = Re(Z2 ), and Img(Z1 ) = *Img(Z2 ).
Figure
Figure9.9.Comparison
ComparisonofofLC LCand andCL CLnetworks
networksatat100
 KΩ when rectifier  parameters and the passive
1001KΩ when rectifier1 parameters and the passive
components
componentssizing sizingare arefixed.
fixed. 2
Z = jωL + R P + || R L || (6)
jωC jωCL
In
Inthis
thiswork,
work,an
anon-chip
on-chipLLnetwork
networkwas
wasused
usedby
bycascading
cascadingfour
fourinductors
inductorsininseries
seriestoto
increase
increase the inductance while maintaining a high-quality factor. It was tuned to matchatat
the inductance while maintaining a high-quality factor. It was tuned to match
 egory has a high or low pass to block or pass the DC signal. A shunt capacitor and series
inductor pass DC. On the contrary, a series capacitor and shunt inductor pass DC. In most
cases, a series capacitor is used to prevent the backflow of signal from the rectifier to the
source. However, since the proposed system has a diode configuration, it is sufficient to
block the high reverse current. Therefore, the IMN design is focused on matching the rec-
Electronics 2023, 12, 175 tifier and antenna impedances only. 8 of 15
Electronics 2023, 12, x FOR PEER REVIEW 9 of 16

L RS > RL L R1 − RS < RL
C jω (C + CL )C
RS 900 MHz,Rbetween
S a 50 Ω antenna Rand
Z2 = jωL S + the
RP +proposed
1 2
L
RS
reconfigurable
2
rectifier with the aux-(7)
iliary rectifier. Considering that the Q of the inductor
( R L ) + [affects
ω (C + the
CL )]matching parameter, the
RL equations
C following RL to obtain matching.
L were deduced C RLA resistor wasLplaced RL in series with
RL
the inductor to represent the Re[ Z parasitic
2 ] = R Aof =the
R P inductor.
+ From (8) and2 (10), the parameter of(8)
matching components can be calculated based 1on+the ω (C + Charvesting
[ R Ldesired L )] frequency. The
(a)matching capacitor(b) is assumed to be ideal. Figure 10(c) exemplifies
2
ωR L (C + CL )
(d)
the model for the match-
ing condition, where R Img[ Z2 ] =
L and CL are the = ωL − impedance
0 equivalent of the proposed rectifier (9)
Figure 8. Four configurations of L-network: (a) Low 1+ pass[ R LCL
ω (for
C+ RSC>LR 2
)]L, (b) High pass LC forand
RS >
auxiliary rectifier,
RL, (c) Low pass LC is the
RAfor RS <antenna
RL, (d) Highresistance,
pass CLLfor and
RS C < Rare
L. the matching network’s passive
2 (C + C )
components, and RP represents the parasitic
ωL =
ωR of Lthe matching L inductor. The auxiliary recti- (10)
2
fier, integrated in parallel
The simulation with
of the the main
rectifier’s 1+rectifier,
[ R L ω (Creduced
impedance + CL )]that
shows thethe equivalent impedance
real impedance of
is much
thelarger
rectifiers
than(RL
the and CL) to(standard
antenna’s be matched, hence
50 Ω). reducing thethe
Consequently, required
L-network matching transfor-the
that matches
RL
mation [19]. To match, Re(Z ) = k
Re(Z = ), and
condition will be Figure 8c or Figure 8d. For a fair
1 2 Img(Z 1 ) = *Img(Z ).
R L comparison, the rectifier sizing, load,
2 (11)
RP + 2
capacitance, inductor sizing, and Q are fixed. 1+[ R1LFigure
ω (C +CL )]9 shows
1 the result of PCE for the
RFEH front-end when CL and 𝑍 =LC 𝑗𝜔𝐿 +𝑅s
networks |𝑅 |
+ (are employed ) the proposed rectifier.
with (6)At
1 R𝑗𝜔𝐶 L 1 √ 𝑗𝜔𝐶
the matching frequency, 900 MHz,Athe = L-C network
= has
k a higher peak and overall PCE
(12)
2 R 1 2
than the C-L network. Therefore, the IMN in Figure A − 𝑗𝜔(𝐶 + selected
8c is 𝐶) for the matching.
𝑅
𝑍 = 𝑗𝜔𝐿 + 𝑅 + (7)
1
40 ( ) + [𝜔(𝐶 + 𝐶 )]
37.87% Peak PCE 𝑅
35 𝑅
33.65% Peak PCE
𝑅𝑒[𝑍 ] = 𝑅 = 𝑅 + (8)
30 1 + [𝑅 𝜔(𝐶 + 𝐶 )]
25 𝜔𝑅 (𝐶 + 𝐶 )
PCE(%)

𝐼𝑚𝑔[𝑍 ] = 0 = 𝜔𝐿 − (9)
20 1 + [𝑅 𝜔(𝐶 + 𝐶 )]
LC-network
15 PDR =
𝜔𝑅
CL-network(𝐶 + 𝐶 )
𝜔𝐿 = (10)
−9 dBm 1 + [𝑅 𝜔(𝐶 + 𝐶 )]
10
𝑅
5 PDR = 𝑘=
−10 dBm 𝑅 (11)
𝑅 +
0 1 + [𝑅 𝜔(𝐶 + 𝐶 )]
−25 −20 −15 −10 −5 0 5
PIN (dBm)
1 𝑅 1
Figure 9. Comparison of LC and CL networks =KΩ√𝑘
𝐴 = at 100 (12)
when rectifier parameters and the passive
2 𝑅 2
components sizing are fixed.
components sizing are fixed.

In this work, an on-chip L network was used by cascading four inductors in series to
Z2 while maintaining a high-quality factor. It was tuned to match at
Z1inductance
increase the
RA L RP VOUT

VRF C RL CL

Figure 10.10.
Figure Model of of
Model thethe
matching condition
matching forfor
condition thethe
RFEH front-end.
RFEH front-end.

Based
Basedononthe equations
the equationsabove,
above,the
thetransformation
transformationratio,
ratio,known
knownas askk==RRL/R
L /RA [20] can
A [20] can
bebefound
found inin
(11).
(11).The equation
The equation shows
showsthat
thatRPRplays anan
P plays important
important role
rolein in
thethe
transformation
transformation
ωL
performance.
performance. TheTheQ ofQ the
of the inductor
inductor whenwhen parasitic
parasitic assumed
assumed in series
in series is .isWhen R P . When
the rec-the
rectifier parameters are fixed, the increase
tifier parameters are fixed, the increase in RP will in R will decrease k. It shows that
P decrease k. It shows that the parasiticthe parasitic
resistance will directly affect the transformation
resistance will directly affect the transformation ratio. ratio. Furthermore,
Furthermore, thethe matching
matching network
network
contributes
contributes toto
thethe passive
passive amplification
amplification toto provide
provide higher
higher sensitivity
sensitivity ofof
thethe system.
system. In In [21],
[21],
the passive amplification is defined as (12). The higher the k, the larger the amplifica-
the passive amplification is defined as (12). The higher the k, the larger the amplification.
tion. Therefore, it is concluded that the parasitic of the inductor plays a big part in the
Therefore, it is concluded that the parasitic of the inductor plays a big part in the imped-
impedance matching. The higher the Q, the lower the R , the better the performance of the
ance matching. The higher the Q, the lower the RP, theP better the performance of the
matching network.
matching network.
Electronics 2023,
Electronics 2023, 12,
12, 175
x FOR PEER REVIEW 10 of 15
9 of 16

To maintain
To maintain aa high-quality
high-quality factor
factor at
at high
high total
total inductance,
inductance, fourfour similar
similar inductors are
cascaded to
cascaded toincrease
increasethe
the total
total inductance
inductance while
while maintaining
maintaining highhigh quality
quality factorfactor
at 900atMHz.
900
MHz.
The The parameters
parameters of the inductor
of the inductor are in
are shown shown in11.
Figure Figure
The 11. The parasitics
parasitics are included
are included and the
and the parameters
parameters are simulated
are simulated using
using Sonnet EMSonnet EM Simulator.
Simulator. At 900 MHz, At 900 MHz,
it has it has
a Q of aQ
11.07, of
and
11.07, and inductance
inductance of 15.53 nH.ofUpon
15.53stacking
nH. Upon stacking
four similarfour similarininductors
inductors series, theintotal
series, the total
inductance
inductance
is 62.12 nH. is 62.12 nH.

20 45
900MHz Quality Factor
Inductance 40
15
35

Inductance, L (nH)
Quality factor, Q

30
Q=11.07
10
25

20
5
15
L=15.53nH
0 10
0 2 4 6 8
Frequency (GHz)

11. Quality factor and inductance of

Figure 11. of the
the matching
matching inductor,
inductor, L,
L, over
over frequency.
frequency.

3.4.
3.4. Control
Control Logic
Logic Circuit
Circuit
The
The proposed work
proposed work adopted
adopted aa CMOS
CMOS Op-Amp
Op-Amp comparator
comparator fromfrom [22][22] toto determine
determine
the
the rectifier’s topology configuration. As depicted in Figure 5d, the comparator consists
rectifier’s topology configuration. As depicted in Figure 5d, the comparator consists
of
of aa source
source input
input stage
stage for
for voltage
voltage comparison,
comparison, an an output
output stage
stage that
that provides
provides the the output
output
signal, and a biasing stage responsible for supplying a bias voltage
signal, and a biasing stage responsible for supplying a bias voltage to the source input to the source input
and
and the output stage. At the source-input stage, the comparator accounts
the output stage. At the source-input stage, the comparator accounts for an external refer- for an external
reference
ence voltage voltage
(VREF)(V ofREF
800) of
mV 800tomV to be compared
be compared with the with the auxiliary
auxiliary rectifier’srectifier’s output
output voltage
voltage (V AUX ). The external V REF serves as a reference for the switching
(VAUX). The external VREF serves as a reference for the switching point to validate the input point to validate
the
powerinput power
level to be level to behigh
either eitheror high
low.orInlow.
the In the scenario
scenario VAUX V
wherewhere isAUX
lower is lower
than than
the Vthe
REF
V REF (V AUX < 800 mV), the input power is considered low, whereas when V AUX is higher
(VAUX < 800 mV), the input power is considered low, whereas when VAUX is higher than
than the V REF (V AUX > 800 mV), the PIN is considered high. A stable reference source is
the VREF (VAUX > 800 mV), the PIN is considered high. A stable reference source is required;
required; therefore, an independent external voltage source is supplied. The output stage
therefore, an independent external voltage source is supplied. The output stage compro-
compromises two CMOS-connected inverters in generating the control signals V X and V Y
mises two CMOS-connected inverters in generating the control signals VX and VY to con-
to configure the rectifier into a different topology.
figure the rectifier into a different topology.
Figure 6 portrays the V AUX at different input powers. At a low input power, as V REF is
Figure 6 portrays the VAUX at different input powers. At a low input power, as VREF
higher than V AUX (V AUX < 800 mV), the comparator will yield an output with a logic low.
is higher than VAUX (VAUX < 800 mV), the comparator will yield an output with a logic low.
This will activate State 1, where TG1 and TG2 are switched on while TG3 and TG4 are off,
This will activate State 1, where TG1 and TG2 are switched on while TG3 and TG4 are off,
configuring the rectifier into conventional CCDD topology. At a high input power, V AUX
configuring the rectifier into conventional CCDD topology. At a high input power, VAUX
rises above 800 mV. The comparator will yield a logic-high output as V REF is now lower
rises above
than the V AUX800. AtmV. The
this comparator
state, willwill
the rectifier yield
beaconfigured
logic-high into
output as VREF is now
a diode-based lower
topology
than TG
with the ,VTGAUX. At this state, the rectifier will be configured into a diode-based topology
1 2 deactivated and TG3 and TG4 activated.
with TG1, TG2 deactivated and TG3 and TG4 activated.
4. Postlayout and Simulation Results
4. Postlayout and Simulation Results
The proposed rectifier and an on-chip LC network are implemented in a 65 nm
CMOS The proposed
process, rectifierinand
as shown an 12.
Figure on-chip
FourLC networkareare
inductors implemented
connected in series in ato65form
nm
CMOS process, as shown in Figure 12. Four inductors are connected
high inductance while maintaining high Q for matching. The other blocks, such as the in series to form high
inductance
rectifier, while maintaining
auxiliary rectifier, andhigh Q for
control matching.
logic, The other in
are highlighted blocks, such asLow-voltage-
the figure. the rectifier,
auxiliary rectifier,
threshold and control
(LVT) transistors logic,for
are used arethe
highlighted
main and in the figure.
auxiliary Low-voltage-threshold
rectifiers to reduce forward
(LVT) transistors
conduction loss and arenormal
used fortransistors
the main and auxiliary
are used for therectifiers
controltologic
reduce
unit. forward conduc-
MIM capacitor
tion
is lossthroughout
used and normal transistors
the are used
entire design. for1 the
Table control
records thelogic unit.components
design’s MIM capacitor is used
value. The
throughout
total the design,
size of the entire design.
excluding Table
the 1bond
records
pads,the 620 µm ×components
is design’s 480 µm. value. The total
size of the design, excluding the bond pads, is 620 µm × 480 µm.
Electronics 2023,12,
Electronics2023, 12,175
x FOR PEER REVIEW 10
11 of
of 15
16

IMN
140um
Rect.

207um

480um
Aux.
Rect.

Ctrl. Logic

620um

Figure 12.
Figure 12. Chip
Chip layout
layout of
of the
the proposed
proposed RFEH
RFEH front
frontend.
end.

Table1.1.The
Table Theproposed
proposedcircuit’s
circuit’scomponents
componentssizing.
sizing.

Components
Components
Circuit Blocks
Circuit Blocks Circuit
Circuit Components
Components TypeType Size
Size
NameName
NMOS
NMOS (LVT)
(LVT) MM
MNa & &
MNb
NaNb 18 µm
18 µm
Rectifier
Rectifier PMOS
PMOS (LVT)
(LVT) PNa &PPNa Nb& PNb 36 µm
36 µm
Main Rectifier
Main Rectifier MIM Capacitor
MIM Capacitor CP CP 1 pF1 pF
Transmission NMOS
NMOS (LVT) TG (NMOS)
(LVT) TG (NMOS) 2 µm2 µm
Transmission Gate
Gate PMOS
PMOS (LVT)(LVT) TG (PMOS)
TG (PMOS) 4 µm
4 µm
NMOS
NMOS (LVT)
(LVT) M1 &M M13 & M3 600600
nm nm
PMOS
PMOS (LVT)(LVT) M2 & M24 & M4
M 36 µm µm
36
Auxiliary Rectifier
Auxiliary Rectifier Rectifier
Rectifier
MIM
MIM Capacitor
Capacitor CP CP 1 pF1 pF
MIM Capacitor
MIM Capacitor CFilter CFilter 1 pF1 pF
NMOS (Standard)MC1,2,5,6,8,10,12,14
MC1,2,5,6,8,10,12,14 21.6
µm µm
Control Logic
Control Logic Comparator NMOS (Standard)
Unit Comparator
Unit
21.6
PMOS (Standard)
PMOS (Standard) MC3,4,7,9,11,13
MC3,4,7,9,11,13 7.2 7.2
u u

The performance of the rectifier block was investigated independently. Figure 13 de-
The performance of the rectifier block was investigated independently. Figure 13
picts the output voltage across a wide range of input power for the CCDD topology, di-
depicts the output voltage across a wide range of input power for the CCDD topology,
ode-based topology, and the proposed hybrid topology with switch controls. The CCDD
diode-based topology, and the proposed hybrid topology with switch controls. The CCDD
topology obtains higher output voltage at low input power, whereas the diode-based to-
topology obtains higher output voltage at low input power, whereas the diode-based
pology has a higher output at high input harvesting power. The proposed rectifier’s per-
topology has a higher output at high input harvesting power. The proposed rectifier’s
formance is exhibited in a combination of both, with a slight voltage drop at high input.
performance is exhibited in a combination of both, with a slight voltage drop at high input.
This is due to the transmission gates, as there is some reverse leakage through the TG1 and
This is due to the transmission gates, as there is some reverse leakage through the TG1
TG during
and2 TG the diode-based configuration, where the switches are not fully turned off.
2 during the diode-based configuration, where the switches are not fully turned
Although
off. Althoughthe leakage is present,
the leakage the proposed
is present, rectifier
the proposed scheme
rectifier provides
scheme a wider
provides PDRPDR
a wider due
to its hybrid configuration. Contrary to the PCE significantly degrading at
due to its hybrid configuration. Contrary to the PCE significantly degrading at high input high input
power, the
power, the PCE
PCE increase
increase at
at the
the all-load
all-load condition
condition at
at high
high input
input power
power compared
compared to to the
the
conventional CCDD rectifier. It shows that the control logic circuit functions to
conventional CCDD rectifier. It shows that the control logic circuit functions to switch at switch at
the exact condition.
the exact condition.
ronics 2023,Electronics
12, x FOR2023,
PEER12,REVIEW
175 12 of 16 11 of 15
cs 2023, 12, x FOR PEER REVIEW 12 of 16

2.5 100
2.5 100 16dBm
Enhance VOUT 16dBm 88.7% Peak PCE
Enhance VOUT
Hybrid (NSPD) 7dBm 88.7% Peak PCE
2.0 Hybrid (NSPD) 80 7dBm
2.0 CCDD 80
CCDD 15dBm Hybrid (NSPD)
Diode-based 15dBm Hybrid (NSPD)
CCDD
Diode-based CCDD
1.5 60 Diode-based
Diode-based
VOUT (V)

1.5 60

PCE (%)
VOUT (V)

PCE (%)
21.5% Peak PCE
21.5% Peak PCE
1.0 40
1.0 40 100kΩ
−16.5 dBm Sensitivity 100kΩ
−16.5 dBm Sensitivity 200kΩ
0.5 20 200kΩ
0.5 20 500kΩ
−19 dBm Sensitivity 500kΩ
−19 dBm Sensitivity 1MΩ
0.0 0 1MΩ
0.0 −30 −25 −20 −15 −10 −5 0 0 −30 −25 −20 −15 −10 −5 0
−30 −25 −20 −15 −10 −5 0 −30 −25 −20 −15 −10 −5 0
PIN (dBm) PIN (dBm)
PIN (dBm)
(a) PIN (dBm)
(b)
(a) (b)
Figure 13. Postlayout 13.simulation
Postlayoutof (a) rectifier
of output voltage across different input power at 100
Figuresimulation
Figure 13. Postlayout of (a)simulation (a) rectifier
rectifier output voltage output
across voltage
differentacross
inputdifferent
power at input
100 power at 100 kΩ
kΩ without matching, (b) the power conversion efficiency of rectifiers across different input powers
without
kΩ without matching, (b)matching,
the power(b) the power
conversion conversion
efficiency efficiency
of rectifiers of rectifiers
across across
different inputdifferent
powers input powers at
at various load conditions.
at various load conditions.
various load conditions.

The on-chipTheLC-network
on-chip IMN is implemented
LC-network IMN isalongalong with the
implemented proposed
along rectifier.
withrectifier.
the proposed The
The on-chip LC-network IMN is implemented with the proposed The rectifier. The
output voltage and PCE of the front-end RFEH system are presented in Figure 14a,b, re-
output voltage output
and PCE voltage
of the and PCE of
front-end the front-end
RFEH system areRFEH system
presented are presented
in Figure 14a,b, re-in Figure 14a,b,
spectively. The switching point occurs at approximately −12 dBm. The PCE
−12 graph graph shows
spectively. Therespectively.
switching pointThe switching point occurs at −12
occurs at approximately approximately
dBm. The PCE dBm. Theshows PCE graph shows
a drop in thea PCE
drop at
in the
the switching
PCE at the point. Subsequently,
switching point. it is increased
Subsequently, it is after the configura-
increased after the configuration
a drop in the PCE at the switching point. Subsequently, it is increased after the configura-
tion is changed
is to a hybrid
changed to a switch-diode-based
hybrid configuration.
switch-diode-based Due to the
configuration. Due switching
to the losses losses and
switching
tion is changed to a hybrid switch-diode-based configuration. Due to the switching losses
and transition, there istherea dip in thein
PCE graph. However, once the switches are fully
and transition,transition,
there is a dip inis thea dipPCE the PCEHowever,
graph. graph. However,
once theonce the switches
switches are fullyare fully turned
turned on, the proposed
on, the proposed hybrid configuration follows the PCE of the diode-based config-
turned on, the proposed hybrid hybrid configuration
configuration followsfollows
the PCE the
ofPCE of the diode-based
the diode-based config-configuration at
uration at high input power.
uration at highhigh
inputinput
power.power.

2.5 40 9
2.5 Enhance VOUT 40 9 dBm 37.87% Peak PCE
Enhance VOUT 37.87%
36.18% Peak PCEPeak PCE
Hybrid (NSPD) 35 dBm 36.18% Peak PCE
Hybrid (NSPD) 35
2.0 CCDD 11dBm
2.0 CCDD 30 11dBm
Diode-based 30
Diode-based
25.16% Peak PCE
1.5 25 25.16% Peak PCE
25
VOUT (V)

PCE (%)

1.5 Hybrid (NSPD)

VOUT (V)

PCE (%)

20 Hybrid (NSPD)
CCDD
5
20 5 dBmCCDDDiode-based
1.0 15 dBm Diode-based
1.0 15 100kΩ
100kΩ
200kΩ
10 200kΩ
0.5 −12.5 dBm sensitivity 10
0.5 −12.5 dBm sensitivity 500kΩ
5 500kΩ
−15 dBm sensitivity 5 1MΩ
−15 dBm sensitivity 1MΩ
0.0 0
0.0 −25 −20 −15 −10 −5 0 50 −25 −20 −15 −10 −5 0 5
−25 −20 −15 −10 −5 0 5 −25 −20 −15 −10 −5 0 5
PIN (dBm) PIN (dBm)
PIN (dBm) PIN (dBm)
(a) (b)
(a) (b)

Figure 14. Postlayout simulation of (a) RFEH front-end output voltage across different input powers
Figure 14. Postlayout simulation of (a) RFEH front-end output voltage across different input powers
Figure 14. Postlayout simulation of (a) RFEH front-end output
(b) thevoltage across different input powers
at 100 kΩ withatimpedance
100 kΩ with impedance
matching, matching,
(b) the power conversion power conversion
efficiency efficiency
across different across
input pow-different input
at 100 kΩ with impedance matching, (b) the power conversion efficiency across different input pow-
ers at variouspowers at variouswith
load conditions loadimpedance
conditionsmatching.
with impedance matching.
ers at various load conditions with impedance matching.
The PCE of the rectifier is calculated by incorporating the power reflection, denoted
by (12), while the front-end RFEH is calculated by (13). The power reflection is not included
in (13) as a matching network is adopted; hence, it achieves maximum power transfer at the
desired frequency. Figure 15 illustrates the post-layout result on the reflection coefficient,
S11, of the proposed front-end RFEH. It is matched at 900 MHz with an S11 of −14 dB.
POUT refers to the output power of the rectifier, with VOUT 2 /RL , PSIG is the input signal
excluding the power reflection, and |S11 |is the power reflection. The rectifier achieves a
 900 MHz
−2.5

Refelction Coefficienct (S11)

−5.0
S11
Electronics 2023, 12, 175 12 of 15
−7.5

−10.0
peak PCE of 88.7% at −22 dBm, while the fully integrated RFEH front-end obtains a peak
−12.5 of 36%.
PCE
P
PCEREC (%) =  OUT  × 100% (13)
−15.0 P 1 −| S | 2
0.50 0.75 1.00 1.25 SIG 1.50 11
Frequency (GHz)
Electronics 2023, 12, x FOR PEER REVIEW POUT 13 of 16
Figure 15. Postlayout simulationPCE
of SRFEH
11. (%) = × 100% (14)
PSIG

The PCE of the rectifier is calculated by incorporating the power reflection, denoted
0.0
by (12), while the front-end
900 MHz RFEH is calculated by (13). The power reflection is not in-
−2.5 in (13) as a matching network is adopted; hence, it achieves maximum power
cluded
Refelction Coefficienct (S11)

transfer at the desired frequency. Figure 15 illustrates the post-layout result on the reflec-
tion−5.0
coefficient, S11, of the proposed front-end
S11 RFEH. It is matched at 900 MHz with an S11
of −14 dB. POUT refers to the output power of the rectifier, with VOUT2/RL, PSIG is the input
−7.5
signal excluding the power reflection, and |S11|is the power reflection. The rectifier
achieves
−10.0 a peak PCE of 88.7% at −22 dBm, while the fully integrated RFEH front-end ob-
tains a peak PCE of 36%.
−12.5
𝑃
𝑃𝐶𝐸 (%) = × 100% (13)
−15.0 𝑃 (1 − |𝑆 | )
0.50 0.75 1.00 1.25 1.50
Frequency (GHz) 𝑃
𝑃𝐶𝐸 (%) = × 100% (14)
Figure 15.
Figure 15. Postlayout
Postlayout simulation
simulation of
of SS11
11.. 𝑃
Figure 16a depicted the relationship of PIN, VAUX, and the power consumption of the
The PCE
Figure 16aofdepicted
the rectifier is calculatedofby
the relationship PINincorporating
, V AUX , and the thepower
powerconsumption
reflection, denoted of the
control logic unit.
unit. VV
by (12), while the front-end
control logic AUX increases linearly with the increment in PIN due to the boosting
RFEH is calculated by (13). The power
increases linearly with the increment in P
AUX IN reflection is not in-
due to the boosting
effect
effect
cludedofofthe
in two-stage
the(13)
two-stage auxiliary rectifier.is
auxiliarynetwork
as a matching rectifier. The
The powerconsumption
power
adopted; consumption
hence, ofof
it achieves the the control
control
maximum logic
logic unit
power unit
increases
increases
transfer at exponentially
exponentially with the increment
with the increment
the desired frequency. Figure 15 in P IN.
inillustratesThis
PIN . This isthe is because
because
post-layout V AUX
V AUX ,result, which
whichon is
is the the source
thesource
reflec-
ofofthe
tion control
thecoefficient, logic
control logic unit,
S11,unit, isisproposed
of the increased,
increased, causing
causing
front-end more more
RFEH. Itpower
power isto to into
flow
matched flow
at theinto
900 the with
control
MHz control
logican Slogic
unit. 11
unit.
The The
power
of −14 power
dB. POUT consumption
consumption
refers to of thethe of thepower
control
output control oflogic
logic unit the unit is negligible
is negligible
rectifier, as PIN
with VOUTis as
lower
2/R PLIN
, Pis
SIGlower
than is − 10than
the dBm−10
input
dBm
and and
signal its power
its excluding
power consumption
consumption
the powerincreases increases
reflection, andwith
with the |SP11the P
|isand
IN and
IN reaches
the power reaches a peak
areflection.
peak consumption
consumption
The of
rectifier
0.278
ofachievesmW
0.278 mW at 5 dBm.
at 5 dBm.
a peak PCE ofFigure
Figure 16b
88.7%16b shows
shows
at −22 the
dBm, power
the power
while consumption
theconsumption of
fully integrated the auxiliary
of RFEH
the auxiliary rectifier.
front-end It
rectifier.
ob-
shows
It tains
shows a similar
a similar
a peak behavior
PCE behavior where the power consumption is negligible
of 36%. where the power consumption is negligible whenINPIN is below when P is below
−10
−10 dBmdBm and andititincreases
increasesexponentially
exponentially until until aa peak
peakconsumption
consumptionofof0.037 0.037 mW mW at at
5 dBm.
5 dBm.
𝑃
𝑃𝐶𝐸 (%) = × 100% (13)
0.30 1.4 0.04
𝑃 (1 − |𝑆 | )
Power Consumption of Power 𝑃 Consumption of
0.25
Control Logic Unit
1.2 𝑃𝐶𝐸 (%)Auxiliary
= Rectifier× 100% (14)
VAUX 𝑃
0.03
Power Consumption (mW)

Power Consumption (mW)

0.20 Figure 16a depicted the1.0relationship of PIN, VAUX, and the power consumption of the
control logic unit. VAUX increases linearly with the increment in PIN due to the boosting
VAUX (V)

0.15 0.8
effect of the two-stage auxiliary 0.02
rectifier. The power consumption of the control logic unit
increases exponentially with the increment in PIN. This is because VAUX, which is the source
0.10
of the control logic unit, is 0.6
increased, causing more power to flow into the control logic
0.01
unit. The power consumption of the control logic unit is negligible as PIN is lower than −10
0.05 0.4
dBm and its power consumption increases with the PIN and reaches a peak consumption
0.00 of 0.278 mW at 5 dBm. Figure 0.2 16b shows
0.00 the power consumption of the auxiliary rectifier.
−25 −20 −15 −10 −5 0
−25 −20 −15
It shows −10
PIN (dBm)
−5 0 5
a similar behavior where the power consumption is negligible
PIN (dBm)
when5 PIN is below
−10 dBm and it increases exponentially until a peak consumption of 0.037 mW at 5 dBm.
(a) (b)

0.30 1.4 0.04

Figure 16.
Power Consumption of (a) The relationship between the input Power
power, auxiliary rectifier’s output voltage, and the
Consumption of
Controlpower
Logic Unit consumption of the control logic unit. (b) The power
Auxiliary Rectifier consumption of the auxiliary rectifier.
0.25 1.2
VAUX
0.03
Power Consumption (mW)

Power Consumption (mW)

0.20 1.0
VAUX (V)

0.15 0.8 0.02

0.10 0.6
0.01
0.05 0.4
 Figure 16. (a) The relationship between the input power, auxiliary rectifier’s output voltage, and
power consumption of the control logic unit. (b) The power consumption of the auxiliary rectifi

The scope of this proposed work was to extend the PDR of the rectifier. The PDR
Electronics 2023, 12, 175 13 of 15
defined as the input power range where the rectifier’s PCE upholds above 20% [9]. At 1
KΩ, the CCDD and diode-based rectifier has a PDR of only 20 dB and 16 dB, respective
In implementing
The scopethe proposed
of this proposedhybrid
work wasconfiguration
to extend the PDRby switching the The
of the rectifier. PMOS PDRconnectio
is
the rectifier
defined as achieves
the inputapower
PDR range
of 23where
dB. To thetest the robustness
rectifier’s PCE upholdsofabove the proposed
20% [9]. At front-e
RFEH,100simulation
KΩ, the CCDD ofand
thediode-based
proposedrectifier
rectifier
haswith
a PDRrespect
of only 20todBprocess
and 16 dB,corner and temper
respectively.
In implementing the proposed hybrid configuration by switching
were performed. The switching point, sensitivity, and peak PCE of the proposed fro the PMOS connections,
the rectifier achieves a PDR of 23 dB. To test the robustness of the proposed front-end RFEH,
end RFEH at typical-typical, slow-slow, and fast-fast processes at different temperatu
simulation of the proposed rectifier with respect to process corner and temperate were
conditions
performed.are The
shown in Figure
switching point, 17. Generally,
sensitivity, thePCE
and peak peak PCE
of the is higher
proposed at −40RFEH
front-end °C and it is
lowest for the fast-fast
at typical-typical, process.
slow-slow, andHowever, the peak
fast-fast processes PCE after
at different processconditions
temperature and temperatu
are shown
variation in Figure
remains 17. Generally,
a minimum the peak
of 23% withPCEmatching at −40 ◦ C included.
is highernetwork and it is at lowest
It is reasona
for the fast-fast process. However, the peak PCE after process and temperature variation
for fully integrated applications. Figure 17a proves the practicality of the proposed circ
remains a minimum of 23% with matching network included. It is reasonable for fully
as the switching
integrated point forFigure
applications. the hybrid configuration
17a proves the practicalityonly
of thevaries
proposedfor circuit
less than
as the200 mV
different processes
switching point forand
the temperatures.
hybrid configurationFor only
sensitivity
varies forwith IMN
less than 200included, it remains
mV at different
sameprocesses
for all the
andprocesses
temperatures. at −40 °C and reduces
For sensitivity with IMN gradually
included, with the increase
it remains the same for in tempe
all the processes at − 40 ◦ C and reduces gradually with the increase in temperature. There
ture. There is only a difference of 4 dBm between the worst and highest sensitivity. T
is only a difference of 4 dBm between the worst and highest sensitivity. The process and
process and temperature variation have shown the robustness of the proposed front-e
temperature variation have shown the robustness of the proposed front-end RFEH at
RFEH at different
different conditions.
conditions.

2.0 −10
Typical-typical Typical-typical Typical-typical
1.8 Slow-slow 45
−11 Slow-slow Slow-slow
1.6 Fast-fast Fast-fast Fast-fast
−12
40
Switching Point at VAUX (V)

Peak PCE (%)

1.4
Sensitivity (dBm)

1.2 −13
35
1.0 −14
0.8
−15 30
0.6
−16
0.4
25
0.2 −17

0.0 −18 20
−40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100
Temperature (°C) Temperature (°C) Temperature (°C)
(a) (b) (c)

Figure 17. Process

Figure corners
17. Process cornerssimulation
simulation ofof proposed
proposed front-end
front-end RFEH RFEH
for RL =for
100RL = (a)
KΩ: 100auxiliary
KΩ: (a) auxili
rectifier switching
rectifier voltage
switching voltage(V),
(V), (b) sensitivity,
(b) sensitivity, (c) PCE.
(c) PCE.

Table 2 summarizes the performance comparison with state-of-the-art RFEH rectifiers.

Table 2 summarizes the performance comparison with state-of-the-art RFEH rect
The proposed reconfigurable rectifier with extended PDR incorporates the CCDD rectifier
ers. The proposed
at low input andreconfigurable rectifier with
switches to a hybrid-based extended
switch-diode PDR incorporates
configuration theACCDD r
at high input.
tifier at low input and switches to a hybrid-based switch-diode configuration at high
comparison is drawn by assessing the rectifier block and by incorporating the computation
put. Aof comparison
power reflection. Hence,by
is drawn the result for the
assessing the rectifier
RFEH front-end withby
block and IMN block is not the co
incorporating
included. This work has comparable sensitivity with other state-of-the-art architectures and
putation of power reflection. Hence, the result for the RFEH front-end with IMN block
achieves a sensitivity of −21 dBm. Based on Table 2, it is shown that the CCDD topology
not included. This work
achieves a higher hasthan
peak PCE comparable sensitivity
the diode-based with other
Dickson topology. state-of-the-art
The proposed rectifier archit
turessurpasses
and achieves a sensitivity
the performance of −21
of other dBm.inBased
research on evaluation.
peak PCE Table 2, it Despite
is shown that the CCD
reporting
better sensitivity, the results of [2,10] achieve unfavorable peak PCE
topology achieves a higher peak PCE than the diode-based Dickson topology. The p and PDR performance.
For [12], a similar concept of configuring between switch and switch-diode configurations
posed rectifier surpasses the performance of other research in peak PCE evaluation. D
was applied; however, only manual switching and conceptual results were shown. [12]
spitecompared
reportingthebetter sensitivity,
four rectifier the results
topologies shown in ofFigure
[2] and [10]
1 and achieve
have shownunfavorable
the results for peak P
and PDR performance.
the four topologies. ThereForwere
[12], a similar
no results with concept of configuring
hybrid rectifier configuration.between switch a
switch-diode configurations was applied; however, only manual switching and conc
tual results were shown. [12] compared the four rectifier topologies shown in Figure 1 a
have shown the results for the four topologies. There were no results with hybrid rectif
configuration.

Table 2. Performance benchmark with related State-of-the-art RFEH rectifiers.

eference This Work [3] [5] [8] [10] [11] [23] [13]
CMOS 65 130 130 180 65 130 130 350
Electronics 2023, 12, 175 14 of 15

Table 2. Performance benchmark with related State-of-the-art RFEH rectifiers.

Reference This Work [3] [5] [8] [10] [11] [23] [13]
CMOS
Tech. 65 130 130 180 65 130 130 350
(nm)
Frequency
900 896 900 900 900 900 953 1356
(MHz)
Rectifier
CCDD Dickson CCDD CCDD CCDD Dickson CCDD CCDD
Topology
Reconfigurable Reconfigurable Self-body- Manual
Proposed hybrid Voltage Self-body- Double-Sided No. of biasing/low- hybrid
Dual-Path
Technique switch-diode Compensation biasing Self-Biasing Stage/Series/ feeding switch-diode
configuration Parallel DC configuration
Sensitivity @1 −21 dBm @1 −22 dBm @1 −18.7 dBm −18.2 dBm −17.7 dBm −21.7 dBm @1 −6.5 dBm 3.22 dBm **
V MΩ MΩ @100 KΩ @100 KΩ @∞ MΩ @50 KΩ @500 KΩ
Rectifier’s 88.7% 51% 80.3% 66% 36.5% 34.93% 69.5% 82% **
Peak PCE @100 KΩ @300 KΩ @100 KΩ @100 KΩ @147 KΩ @1 MΩ @2 KΩ @500 KΩ
PDR (Rectifier
23 dB 10.5 dB 17.5 dB * 20 dB * 11 dB 14 dB 13 dB * N.A.
PCE > 20%)
PDR (Rectifier
16 dB 4 dB 14.5 dB 10.5 dB N.A. N.A. 10 dB N.A.
PCE > 40%)
PDR (Rectifier
10 dB N.A. 9 dB 3 dB N.A. N.A. 5 dB N.A.
PCE > 60%)
Rectifier’s
Effective Chip 0.028 0.053 0.062 0.0088 0.048 0.039 0.029 0.019
Area (mm2 )
* Estimated from a graph. ** work does not include reconfiguration, estimated from combination of two different
topologies

5. Conclusions
A novel wide-dynamic-range hybrid reconfigurable rectifier for an RF energy harvest-
ing system is proposed in this work, which can be reconfigured into different topologies
based on the input voltage to enhance the rectifier’s PCE and sensitivity. At low input
power, the hybrid rectifier is configured into a CCDD topology that benefits from the
low conduction loss advantage due to the cross-coupled transistor pairs. At higher input
power, the rectifier is reconfigured into a hybrid diode-based (NSPD) topology to reduce
the reverse current leakage. Designed in 65 nm CMOS technology, the proposed rectifier
achieves a peak PCE of 88.7% at 100 KΩ, surpassing the performance of all existing research.
In addition, the reconfigurable hybrid design offers a wide PDR of 16 dB for PCE over 40%.
It attains superior sensitivity of −21 dBm to achieve 1 V with a 1 MΩ load condition.

Author Contributions: Conceptualization, W.X.L., J.K.Y., G.C. and K.K.P.C.; methodology, W.X.L.
and J.K.Y.; software, W.X.L. and J.K.Y.; data curation, W.X.L., J.K.Y. and G.C.; writing—original draft
preparation, W.X.L. and J.K.Y.; writing—review and editing, W.X.L., J.K.Y., G.C., H.R. and K.K.P.C.;
investigation, W.X.L., J.K.Y. and G.C.; supervision, H.R., Y.C., P.-I.M. and R.P.M.; validation, W.X.L.
and J.K.Y.; funding acquisition, H.R. All authors have read and agreed to the published version of the
manuscript.
Funding: This work was supported by the Collaborative Research in Engineering, Science and
Technology Center (CREST) Program under Grant T05C2-19(PV026-2020).
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: Data are contained within the article.
Conflicts of Interest: The authors declare no conflict of interest.
Electronics 2023, 12, 175 15 of 15

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