A HIGH SPEED PARALLEL TIMING SYNCHRONIZATION ALGORITHM
FOR 16QAM
HAO LI, ZHI-GANG WANG, HOU-JUN WANG
School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China
E-MAIL: haoli_uestc@163.com
Abstract:
The paper presents an efficient parallel timing
synchronization algorithm structure, which is suitable for high
speed communications demodulation system and easy to
implement on FPGA platform. First, a new parallel timing
synchronization structure is displayed. Wherein the proposed
parallel structure make up of a feedback loop based on the
farrow interpolation filter, Gardner algorithm and the
numerically controlled oscillator (NCO) controller. In addition,
the parallel implementation structure of these modules has been
studied. Especially, the principle based on the sign bit decision
is employed in parallel NCO algorithm. By this feedback loop,
we can get the best symbol points after timing synchronization.
The simulation results show that the entire parallel timing
synchronization algorithm not only can correct working, but
also the system performance loss does not exceed 1dB.
Keywords:
Parallel timing synchronization algorithm structure;
Farrow interpolation filter; Gardner algorithm
1. Introduction
With the development of wireless communication
technology, the demand for data transmission rate has been
up to several gigabits per second (Gbps) in the high speed
demodulation system. In order to achieve the transmission of
gigabits data rates in a limited bandwidth, the most effective
option is to use broadband modulation techniques, such as
16QAM.
Timing synchronization is a key technology of the high
speed demodulation system [1]. Universal timing
synchronization algorithm is designed based on O&M
algorithm [2] and Gardner algorithm [3]. O&M algorithm is
a process of timing error calibration in the frequency domain.
Its advantage is that we can obtain an accurate timing error
information, but it also needs to do square operation and the
DFT conversion for the signal, which will consume a lot of
resources. While the Gardner algorithm is an error detection
algorithm of no auxiliary data. Its characteristic is that we
can calculate the value of a timing error with only two
978-1-5090-6126-6/16/$31.00 2016 IEEE
symbol points in each symbol period. And it is independent
of the carrier synchronization, which has been demonstrated
in [3]. In [4], the authors have combined farrow interpolation
filter [5] to achieve the classic serial timing synchronization
algorithm on the basis of Gardner algorithm. Other similar
serial structures are presented in [6] and [7]. But these
traditional serial timing synchronization structure is not valid
for the high data stream, due to the impact of the current
digital hardware devices. Hence, we need to study a parallel
timing synchronization algorithm architecture based on
farrow interpolation filter and Gardner algorithm. A parallel
timing synchronization architecture based on Gardner
algorithm has been presented in [8], which contains a sample
dropping unit, parallel interpolation filter and a loop filter
control unit. But only the interpolation filter to be processed
in parallel, and other important module is still serial mode.
The author also gives a fully parallel timing synchronization
structure in [9]. However, it does not give a specific
theoretical derivation process.
This paper proposes a new fully high speed parallel
timing synchronization structure in digital domain. The
parallel structure is based on farrow interpolator and Gardner
algorithm. In the entire parallel loop architecture, the
improved parallel Gardner error detector and parallel NCO
control algorithm is analyzed in detail. This fully digital
parallel timing synchronization algorithm is very suitable for
16QAM and easy to implement on FPGA platform.
The rest of the paper is organized as follows. Section 2
describes the parallel timing synchronization algorithm and
its implemental structure. Section 3 shows the results of
simulation and FPGA implementation. Finally, conclusions
are drawn in Section 4.
2. Parallel timing synchronization
Since the sample clock of the receiver and the sender
clock is not synchronized, this results in the sample data is
not best sample point at the receiving. But according to the
input sample signal and interpolation position, the present
403
structure can obtain the best sample value by interpolation
algorithm. Here, the interpolation position is given by the
NCO controller. The serial farrow interpolation filter output
based on polynomial fitting can be written as [10]
y (k )
where v(l ) ¦ b (i) ˜ x(m
i
l k
interpolation position. The bl (i ) indicates the polynomial
coefficients.
According to equation (1), the serial farrow structure
has been described in [10], which is not specified here. The
designed four-parallel timing synchronization structure is
shown in Figure 1. The parallel structure consists of a
feedback loop. In Figure 1, the parallel farrow interpolation
filter structure can be seen as four groups parallel FIR filter
H(i), i = 0,1,2,3. And each group parallel FIR filter
coefficients are different, which can be obtained by
polynomial fitting. The parallel FIR filter structure can be
simply implemented with the register cache method. And the
timing adjust block is used to select the correct signal from
the data FIFO. The following sections will focus on the
parallel loop algorithm structure of the Gardner error
detector and the NCO controller.
x(4n  3)
x(4n  2)
x(4n  1)
x(4n)
H(3)
H(3) Ă H(0)
timing error detection algorithm for 16QAM can be
expressed as
e(r ) [ y(r 1 2)  a] ˜ [ y(r )  y(r 1)] (2)
where a [ y(r )  y(r  1)] 2 . The y (r ) denotes the r-th
N
¦P
l 0
l
k ˜ v(l ) (1) symbol sample point. The y(r  1 2) denotes sample point
between the r-th symbols and the (r-1)-th symbols.
 i) . And the P k denotes the From equation (2), we can found that it uses two
symbols sample points and their intermediate sample point.
This requires input data rate of the Gardner timing error
detector is twice the symbol rate. And it also can be seen that
the algorithm can estimate a timing error value in each
symbol period and easy to implement. However, the
traditional Gardner algorithm does not meet the demand of
the high data rate transmission. So we get a parallel Gardner
algorithm through its improvement.
We assume Gardner error detector has four route
parallel input data, the parallel Gardner algorithm is
expressed as follows
­e(2n) [ y(4n)  a(2n)] ˜ [ y(4n  1)  y(4n  1)]
®
¯e(2n  1) [ y(4n  2)  a(2n  1)] ˜ [ y(4n  3)  y(4n  1)]
(3)
where a(2n) [ y(4n  1)  y(4n 1)] 2 . The y(4n  i) ,
i 0,1, 2,3 is four route parallel input data of the current
clock cycle. The y(4n  1) is the fourth input data of the
before clock cycle. In every clock cycle, the fourth input data
needs to be delayed by one clock cycle through the register.
H(0) e(2n)
y (4n)

y (4n) 

yout 31 1/2
1/2
2
P1 y (4n  1)
H ( n)
detector
error detector

yout 01 y (4n  1)
D  1/2
1/2
adjust
d ust

yout 32
y (4n  1)
Timing adj

P2
Gardner error
Timing
NCO
Parallel NCO

yout 02 y (4n  2)
Gardner

w
yout 33 e(2n  1)
Parallel

P3 y (4n  2)
yout 03 
y (4n  3)
yout 34 1/2
1/2
2

P4
yout 04 y (4n  3)
Loop

Fig.2 Four-parallel Gardner error detector structure

ffilter
Loop

en1
lter

en2
fi

en3
en4 In addition, the y(4n  1) and the y(4n  i), i 1,3 is
the symbol sample point. The y(4n) and the y(4n  2) is
Fig.1 Four-parallel timing synchronization structure
the intermediate sample point. We can find that the parallel
Gardner algorithm can calculate the two route parallel timing
2.1. Gardner error detector
error values for four route parallel input data in one clock
cycle. The Figure 2 shows the four-parallel Gardner error
Gardner error detector is used to detect the loop timing
detector implementation structure. In Figure 2, in order to
error. Gardner algorithm is deduced based on QPSK
simplify the subsequent processing of the loop filter, the
modulated signal. But it is also suitable for 16QAM
modulated signal, which has been verified in [11]. The average of timing error H (n) is calculated.

404
2.2. Loop filter
The role of the loop filter is filtering the timing error. It
can reduce the influence of high frequency noise, so as to
reduce the jitter of the timing error signal. This makes timing
error value more smoothly and make the entire loop of the
timing synchronization is more stable. Here we just give a
common loop filter structure, as shown in Figure 3.
k1
e( n ) Z Then equation (7) is also written as
D
k2
Fig.3 Loop filter structure
In Figure 3, the k1 and the k 2 are loop filter
coefficients, which determines the performance of the timing
loop convergence rate. Its calculation method has been
specifically given in [12].
2.3. Parallel NCO
Parallel NCO control unit provides parallel fractional
interval for farrow interpolation filter, which will determine
the interpolation position. It also provides overflow parallel
enable signal for the timing adjust unit.
It has been pointed out the essence of NCO control unit
is a differential equation in [4]. It is expressed as follows
K (m) [K (m 1)  w(m)]mod 1 (4)
where mod is defined as a modulo function that just take the
remainder portion. Specific given by (5).
­K (m  1)  w(m)  1 K (m  1)  w(m)  0
K (m) ® (5)
¯K (m  1)  w(m) otherwise
Next, the K (m) represents the value of NCO register in
the m-th working clock. The w(m) is input control word of
the NCO control unit.
The working clock of the NCO is 1 Ts , and the 1 Ti is
output data rate after interpolator. Input control word w(m)
is adjusted through the loop filter. When the loop reaches
balance, the w(m) is approximately a fixed constant, that is
w(m) Ts Ti . According to the analysis of the preceding
Gardner algorithm, we can know that 1 Ti 2Rs , where Rs
represents the symbol rate. Therefore, at the initial moment
of the loop, we set w(1) 2RsTs . With the sample clock 1 Ts
is quite large in high speed demodulation system, the
405
traditional NCO structure does not be implemented in FPGA.
So we propose an improved parallel NCO algorithm, which
uses the principle of the sign bit decision.
Suppose parallel NCO control unit has M route and
generate M sets of data K1 (n) , K2 (n) , , KM (n) . Each set
of data is given
Ki (n) K (nM  i) i 1, 2,3, M (6)
Combining equation (4) can be obtained the following
expression
K (nM  i) [K (nM  i 1)  w(n)]mod1, i 1, 2, M (7)
­ K (nM  1) [K (nM )  w(n)]mod 1
° K (nM  2) [K (nM  1)  w(n)]mod 1
°°
® K (nM  3) [K (nM  2)  w(n)]mod 1 (8)
°
°
°̄ K (nM  M ) [K (nM  M  1)  w(n)]mod 1
where register variable K (nM  i) , i 1, 2,3, M is
initialized to 0.
The above process is described as follows. Input control
word w(n) at the initial moment, then according to above
equation (8), all M groups K can be calculated in one clock
cycle. Meanwhile, analyzing the positive and negative of the
M groups K . Because we have to get M groups K in one
clock cycle, so we will not use the pipeline design ideas. And
equation (8) is simplified as follows
­ K (nM  1) [K (nM )  w(n)]
° K (nM  2) [K (nM )  2 w(n)]
°°
® K (nM  3) [K (nM )  3w(n)] (9)
°
°
°̄ K (nM  M ) [K (nM )  Mw(n)]
It can be seen that the current time needed M groups K
only relevant K (nM ) and w(n) . This allows to calculate
the value of M groups K independent of each other, so as
to achieve the purpose of parallel processing. In equation (9),
it does not need to judge the positive and negative of the M
groups K and also do not need to use modulo function,
since the binary subtraction is converted into an addition
operation by its complement. It means that we can do parallel
processing according to the per clock cycle.
The M-parallel NCO overflow enable signal expression
is given
 ­ en[1] sgn[K (nM )] † sgn[K (nM  1)] Scatter plot Scatter plot
° en[2] sgn[K ( nM  1)] † sgn[K ( nM  2)]
5 4

°° 2

Quadrature

Quadrature
® en[3] sgn[K (nM  2)] † sgn[K (nM  3)] (10)
°
0 0

° -2
°̄ en[ M ] sgn[K (nM  M  1)] † sgn[K (nM  M )]
-5 -4
where sgn[K ] means to take the sign bit of K and †
-5 0 5 -4 -2 0 2 4
In-Phase In-Phase
represents exclusive OR (XOR). (a) before timing synchronization (b) after timing synchronization

And the M-parallel fractional interval is calculated 1 0.02

based on M groups K and en , the expression is written as

Fractional interval

Loop filter output

0.01

­ P1 en[1]? [K (nM ) w(n)] : P0 0.5 0

°
°° P2 en[2] ? [K (nM  1) w(n)] : P1 -0.01

® P3 en[3]? [K (nM  2) w(n)] : P2 (11) 0 -0.02

0 1000 2000 3000 4000 0 1000 2000 3000 4000
° Number of Symbols Number of Symbols
° (c) (d)

¯° P M en[ M ]? [K (nM  M  1) w(n)] : P M 1

Fig.4 Simulation results
where P0 is the fourth input value of the before clock cycle.
The “ ? ” represents the logical condition judgment. The
0
10

detail calculation expression is as follows 10

-1

­K (nM ) w (n) en[1] 1

P1 ® (12) 10
-2

¯ P0 en[1] 0
BER

-3

So the timing adjust unit selects valid data parallel

10

output by overflow enable signal, and the interpolation filter 10

-4

calculates the correct interpolation point by fractional -5

interval.
10 Float simulation BER
fixed simulation BER
Theoretical BER
-6
10
0 2 4 6 8 10 12 14

3 Simulation and implementation results EbNo(dB)

Fig.5 BER of the parallel timing synchronization

Here, the performance of the proposed high speed Figure 5 compares the BER simulation results of the
parallel timing synchronization algorithm is simulated in parallel demodulator with the theoretical value. We can also
MATLAB. The simulation parameter has been set as follows : find out that the performance of the proposed parallel
16QAM modulated signal, M 4 , f s 1.44 GHz, symbol demodulation architecture has the smaller loss. And the loss
rate Rs 180 MHz, w(1) 2Rs f s 1 4 , timing phase is less than 1dB.
error H 0.4 f s , loop filter coefficients of timing A hardware system platform also has been built with
Xilinx XC7VX485T FPGA chip and Texas Instruments (TI)
synchronization k1 210 and k2 221 , signal to noise A/D converter ADC12D1600 device. And a trigger capture
ratio (SNR) 20dB. The quantized parameters are as follows: mechanism is used on this platform [13], it can complete the
12bits after sampling, 25bits for timing synchronization. accurate capture of the signal .The parameters of the
Figure 4 shows the simulation results of the parallel system. hardware implementation are the same as MATLAB
Figure 4 (a) shows the constellation before timing simulation.
synchronization. Figure 4 (b) is a constellation after timing
synchronization, which has been compensated for the timing Table 1 Hardware resource utilization
phase error. Figure 4 (c), (d) shows the fractional interval Logic Utilization Used Available Utilization
curve and loop filter output in timing synchronization Num. of Slice Registers 36844 607200 6%
process, respectively. It is concluded that the fractional Num. of Slice LUTs 17525 303600 6%
Num. of Block/FIFO 13 1030 1%
interval quickly converges to 1 4 , and the loop filter output Num. of DSP48E1s 320 2800 11%
converges to near zero. From Figure 4, we can know that the Table 1 shows the hardware resource utilization of the
proposed parallel demodulator can efficiently work.

406
parallel timing synchronization structure after FPGA
implementation. In this experiment, the running clock of the
entire system is 1440 8 180 MHz in FPGA. Thus, for high
speed data streams, the existing FPGA can meet the
implementation requirements through parallel processing
architecture. And the consumption of hardware resource is
also allowed to accept.
4 Conclusions
This paper presents a brand new high speed parallel
timing synchronization structure for 16QAM. This parallel
structure has been proved to be quite effective and very
suitable for FPGA implementation. The simulation indicates
that the system performance loss is very small, which is very
close to the theoretical value. Meanwhile, the hardware
implementation results show that the proposed parallel
architecture does not consume a lot of resources. This simple
and efficient parallel timing synchronization algorithm of
low complexity can be widely used in high speed
communication system.
Acknowledgements
This paper is supported by National Natural Science
Foundation of China (Grant No. 60934002).
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