Computer Architecture Unit 4

References:
 David Salomon, Computer Organisation, 2008, NCC Blackwell
 John L. Hennessy and David A. Patterson, Computer Architecture: A
Quantitative Approach, Fourth Edition, Morgan Kaufmann Publishers
 Joseph D. Dumas II; Computer Architecture; CRC Press
 Nicholas P. Carter; Schaum’s outline of computer Architecture; McGraw-
Hill Professional

E-references:
 http://www.lc3help.com/tutorials/Basic_LC-3_Instructions/ Retrieved on
03-04-2012
 http://www.scribd.com/doc/4596293/LC3-Instruction-Details Retrieved
on 02-04-2012
 http://xavier.perseguers.ch/programmation/mips-
assembler/references/5-stage-pipeline.html

Manipal University Jaipur B1648 Page No. 101

Computer Architecture Unit 5

Unit 5 Design Space of Pipelines

Structure:
5.1 Introduction
Objectives
5.2 Design Space of Pipelines
Basic layout of a pipeline
Dependency resolution
5.3 Pipeline Instruction Processing
5.4 Pipelined Execution of Integer and Boolean Instructions
The design space
Logical layout of FX pipelines
Implementation of FX pipelines
5.5 Pipelined Processing of Loads and Stores
Subtasks of load and store processing
The design space
Sequential consistency of instruction execution
Instruction issuing and parallel execution
5.6 Summary
5.7 Glossary
5.8 Terminal Questions
5.9 Answers

5.1 Introduction
In the previous unit, you studied pipelined processors in great detail with a
short review of pipelining and examples of some pipeline in modern
processors. You also studied various kinds of pipeline hazards and the
techniques available to handle them.
In this unit, we will introduce you to the design space of pipelines. Day-by-
day increasing complexity of the chips had lead to higher operating speeds.
These speeds are provided by overlapping instruction latencies or by
implementing pipelining. In the early models, discrete pipeline was used.
Discrete pipeline performs the task in stages like fetch, decode, execution,
memory, and write-back operations. Here every pipeline stage requires one
cycle of time, and as there are 5 stages so the instruction latency is of five
cycles. Longer pipelines over more cycles can hide instruction latencies.

Manipal University Jaipur B1648 Page No. 102

Computer Architecture Unit 5

This provides processors to attain higher clock speeds. Instruction pipelining

has significantly improved the performance of today’s processors. In this
unit, you will study the design space of pipelines which is further divided into
basic layout of a pipeline and dependency resolution. We focus primarily on
pipelined execution of Integer and Boolean instructions and pipelined
processing of loads and stores.
Objectives:
After studying this unit, you should be able to:
 explain design space of pipelines
 describe pipeline instruction processing
 identify pipelined execution of Integer and Boolean instructions
 discuss pipelined processing of loads and stores

5.2 Design Space of Pipelines

In this section, we will learn about the design space of pipelines. The design
space of pipelines can be sub divided into two aspects as shown in
figure 5.1.

Figure 5.1: Principle Aspects of Design Space of Pipelines

Let’s discuss each one of them in detail.

5.2.1 Basic Layout of a pipeline
To understand a pipeline in depth, it is necessary to know about those
decisions which are fundamental to the layout of a pipeline. Let’s discuss
them below:

Manipal University Jaipur B1648 Page No. 103

Computer Architecture Unit 5

The number of pipeline stages used to perform a given task are:,

1. Specification of the subtasks to be performed in each of the pipeline
stages,
2. Layout of the stage sequence, that is, whether the stages are used in a
strict sequential manner or some stages are recycled,
3. Use of bypassing, and
4. Timing of the pipeline operations, that is, whether pipeline operations
are controlled synchronously or asynchronously.

Figure 5.2 depicts these stages diagrammatically.

Figure 5.2: Overall Stage Layout of a pipeline

5.2.2 Dependency resolution

Pipeline design has another aspect called the dependency resolution.
Earlier, some pipelined computers used the Microprocessor without
Interlocked Pipeline Stages (MIPS approach) and used a static dependency
resolution which is also called static scheduling or software interlock
resolution.
Here the detection and proper resolution of dependencies is done by the
compiler. Examples of static dependency resolution are:
 Original MIPS designs (like the MIPS and the MIPS-X)
 Some less famous RISC processors (like RCA, Spectrum)
 Intel processor (i860) which has both VLIW and scalar operation modes.

Manipal University Jaipur B1648 Page No. 104

Computer Architecture Unit 5

A further advanced resolution scheme is the combined static/dynamic

dependency resolution. This has been employed by MIPS R processors like
R2000, R3000, R4000, R4200 and R6000. In the first MIPS processors
(R2000, R3000) hardware interlocks were used for the long latency
operations, such as multiplication, division and conversion, while the
resolution of short latency operations relied entirely on the compiler. Newer
R-series implementations have extended the range of hardware interlocks
further and further, first to the load/store hazards (R6000) and then to other
short latency operations as well (R4000). In the 84000, the only instructions
which rely on a static dependency resolution are the coprocessor control
instructions.
In recent processors dependencies are resolved dynamically, by extra
hardware. Nevertheless, compilers for these processors are assumed to
perform a parallel optimisation by code reordering, in order to increase
performance. Figure 5.3 shows the various possibilities of resolving the
pipeline hazards.

Figure 5.3: Possibilities for Resolving Pipeline Hazards

Self Assessment Questions

1. The full form of MIPS is ___________________.
2. In recent processors dependencies are resolved ______________, by
extra hardware.

Manipal University Jaipur B1648 Page No. 105