X: can be any fields or features
DFT (Design For Test)
FUSA
Consists of fuse controller (1 per die) and
fuse puller (1 per IP).
At reset fuse controller sense all fuse and
store in RAM or RF.
When IP's fuse puller request fuse via
IOSF-SB, fuse controller return fuse data
through LUT
If no fuse data returned, reset value is
default fuse value.
STF/SCAN
Goal: improve controllability and observability
of internal flip-flop/ detects defects in the
combinational logic
connect virtually all flip-flop in chains by
converting each flip-flop into mux-flop
structure
SCAN uses SCANUNIT architecture
Structural Test Fabric (STF)
Parallel SCC and Parallel SRC Controllers
STF (Structural Test Fabric)
Load/Unload
Capture
Scan test sequence
DFX (Design for X) DFB (Design For Debug)
one of the features in PCH to ensure high Debug is to root cause issues and
effective defect screening strategy for unexpected behaviors, so all products
the entire PCH. features must be verified at post-silicon.
save cost, time and efficient test Previously, debug was done on specially
methodology and power. DFT in PCH is build board and setup on the hardware
the way to ensure the quality of the equipment, but it is costly, time consuming
devices. and high risk to cause another hardware
issues.
DFD will reduce these risks and debug now
is done on the system without open the
Boundary Scan cover for debug.
Basically, DFX components consists of Full IO coverage except critical PM
structural and functional modes to cater pins
different mode of testing. HVM coverage for all IOs DCI (Direct Connect Interface)
DFT (Test): HVM testability, platform Interconnect test for board testing VISA
Closed Chassis Debug (using external
testability Usage - DC Tests for Digital Circuits Generally, debug involves the power up/
Functional boot requirement
adapter to debug). primary way to observe internal signal at
DFT (Validation) : SV, DV, EV, MV boot sequence, low power debug,
non-standardized way of power up Debug adapter connected in between host pin level
DTF (Survivability) : A0 Debug Strap,/ OS/drivers/Apps.
requirement for 14nm HIP and debug target. divided into 3 segments mux: Unit LM,
Debug & Override Registers Debug components: JTAG, VISA, DCI,
Multiple SOC plumbing needed to Once connected, target will send the Partition LM, Center LM
DFT (Modularity): Chassis, SIIP NPK, CrashLog
simplify PHY boot for bscan. interface, register, pins information to the output: pin Northpeak (Mem, pin, DCI)
debug host.
JTAG
TAM MBIST Standard interface for Boundary Scan
Support self-test flow and functional safety NPK (North Peak)
16 bits input data through GPIO with 1 (Bscan) Design consists of many partition blocks
IJTAG network set of silicon features, target system API
clock, 1 command. 5 pins: TCK, TDI, TMS, TDO, TRSTB and contains the signal that we want to
Memory BIST: on-die logic to test memory used for debug tools and software stack
Supports IOSF primary access to any IP to TAP Control (Test Access Port): predefined observe.
array for defects. Enable: System-level Debug, HW & SW
transport test vectors. Bscan instructions Each signal is connected to configurable
build in logic to generate pattern and co-debug, third party vendors to create
Sideband access through P2SB. Allow multiple TAP control on single JTAG muxs and the mux output connect to
compare at speed. Control via TAP debug tools, architectural product-to-
TAM can be accessed through IOSF or SM partition-level mux.
product consistency
(for preloaded test execution). The partition-mux then connected to central
TAP mux, which itself connected to observe
endpoint.
primary test and debug access mechanism Selectors controlled by registers, which
TAP Controller State Machine (IEEE writing the signal to reg allows selected
Enable IP test to be converted into HVM 1149.1):
observed signal to the end point.
test 16 stage with 4 major operations: Reset,
Run-Test, Scan-DR, Scan-IR
multiple root spcae
HSIO loopback Scan: Capture, Shift, Update
FW pre-load into SRAM
FUSA (fabric parity end to end check)