Journal of VLSI Design and its Advancement

Volume 3 Issue 2
DOI: [To be assigned]

A Review Report on Multi-Voltage Rule Check and Formal

Verification of ASIC design
Mythili M.1*, Sujata D Badiger2, Jayati Singh3, Venkata Rangam Totakura4
1
Student, Department of Electronics and Communication, RV College of Engineering,
Bengaluru, Karnataka, India
2
Assistant Professor, Department of Electronics and Communication, RV College of
Engineering, Bengaluru, Karnataka, India
3,4
Cypress – an Infineon technologies company, Bengaluru-93, Karnataka, India
*Corresponding Author
E-Mail Id: mythilim.ec16@rvce.edu.in

ABSTRACT
In order to decrease the power dissipation in ASIC design, Multi-voltage design techniques
such as Power gating, Clock gating, Power down mode, Multi-threshold, etc. are employed.
To help designers verify the correct implementation of these low power design techniques,
Multi-voltage Rule Check is used. The implementation of different Multi-voltage design
elements such as Isolation Cell, Level Shifter Cell, Retention Cell and power aware design is
explained using Unified power format (UPF). And in the design process from Register-
transfer level (RTL) to Graphic Database System (GDSII) various changes are made to the
netlist to make it easily testable, to satisfy the timing constraints, to optimally place and route
the design. These processes introduce variations in the netlist, which must be checked to
make sure that its functionality has not changed. So Formal Verification is performed to
confirm that Golden netlist (Reference) and revised netlist are equivalent at different phases,
example Synthesis, Design for Testability (DFT), Place and route. This paper discusses the
different mathematical algorithms underlying formal Verification such as Binary decision
diagram and Satisfiability solvers. It provides a detailed review of both formal verification
and multi-voltage rule check.

Keywords: Power gating, clock gating, unified power format, binary decision diagram,
satisfiability solvers

INTRODUCTION the process technology decreases below

With the increase in the development of
portable devices, the low power designing
of circuit is becoming one of the most
important domains in VLSI. Since the
battery usage must be as minimal as
possible, several techniques are being
implemented in the chip design to reduce
power consumption. The total power
dissipation in CMOS circuits can be
divided into static and dynamic power
dissipation. The static power dissipation is
due to subthreshold conduction, reverse
bias leakage and tunneling current. And
dynamic power consumption is mainly due
to switching and short-circuits power. As
90nm the sub threshold leakage increases
which lead to power dissipation even when
there is no switching activity in the gates
[19]. Hence the modern chip designs not
only focus on satisfying the functionality
of the intended specification but also put a
huge effort on power reduction. It employs
various techniques such as having multiple
power domains according to the power
requirement, unlike the traditional designs
where the entire chip had a single power
domain. Clock gating is used to turn-off
the clock switching when the device is not
in use, Multi-threshold voltage cells are
used to reduce static power, etc. But the

HBRP Publication Page 1-11 2020. All Rights Reserved Page 1


main thing to be noted is that all these are
additional methods should not affect the
original intended functionality of the
design. And in order to make sure this, the
Multi-Voltage rule check (MVRC) is used.
It checks for all the power related issues in
the design and reports them, so that the
designer can add suitable cells to
overcome this or the design will be
tweaked accordingly to ensure that the data
integrity is maintained. There are various
tools available in the market to perform
MVRC and FV as shown in Table-1, this
paper discusses about the Cadence
Conformal tool.
Table 1: Different EDA Tools for FV and
MVRC.
EDA Formal MVRC
TOOLS Verification
Cadence Conformal Conformal
LEC Low Power
Synopsys Formality Eclypse
Mentor Formal Pro
Graphics
Formal verification (FV) is another
process used to perform the equivalence
check between two netlists at different
stage in ASIC design flow. The RTL code
in Verilog or VHDL format is converted to
gate level net list after synthesis; in this
conversion, the actual human
understandable code is converted into
logic gates and optimizations are
performed on the netlist. In the DFT
(Design for Testability) stage, extra logic
is inserted into the netlist to make the
design testable; various operations
performed are scan chain insertion and
built in self-test etc. After fabrication there
could be some defect in silicon, the DFT
logic helps in identifying these defects at
the post-silicon test. In the next stage the
DFT netlist is placed and routed, the clock
network is built; buffer/inverters are added
to satisfy timing constrains [6]. As it can
be seen, the netlist at the end of each stage
has some modifications, a few components
HBRP Publication Page 1-11 2020. All Rights Reserved
Journal of VLSI Design and its Advancement
Volume 3 Issue 2
DOI: [To be assigned]
are added, and optimizations are
performed in order to reduce area, power
and delay. Formal verification plays an
important role in making sure the
functionality of the design is not changing
after each stage from RTL to GDSII. The
traditional way of performing this
verification was simulation, where a set of
input vectors are applied and the outputs
were checked against the expected results.
But as input size increases the number of
testcases to be verified will also increase
exponentially and after a point it becomes
practically impossible within a given time
to verify the entire design. And the
testcases applied may not completely
cover all the possibilities. There is a
famous case of Intel Pentium FDIV where
after the chip was released, a bug was
found in the floating-point unit, because of
which it was giving incorrect results after a
few decimal places for division. Since this
was a very rare case, it was missed during
the verification.
BACKGROUND
Power Dissipation in CMOS
The total power dissipation in CMOS
circuits can be divided into static and
dynamic power.
Static power
It is dissipated even when there is no clock
signal applied. It is due to the following
factors:
1. Subthreshold conduction: If the input
voltage of a transistor is less than the
threshold, ideally there should not be
any drain current, but due to
subthreshold conduction of transistors,
there will be some leakage current [9].
2. Reverse bias leakage: In CMOS
circuits, at the junction between the
diffusion and well, reverse biased
diodes are formed, and this constitutes
to reverse biased leakage current.
3. Tunneling Current: As the size of the
MOSFET is made smaller in order to
reduce area, the thickness of the oxide
Page 2

is also reduced and when this
dielectric layer is reduced beyond a
certain point it will increase the
probability of electrons tunneling from
gate to the channel due to Quantum
mechanical effects. This process is
called Gate tunneling.
Dynamic power
It is constituted by the following factors:
1. Switching Power: It is due to the net
capacitance at the load of a gate.
Hence higher the load or if the
switching activity is more, dynamic
power will be high; that is the
capacitor will get charged and
discharged quickly. Without switching
there is no dynamic power, but static
power still exists.
2. Short Circuit Power: During switching
an instantaneous short-circuits is
formed between the supply and the
ground, as both pMOS and nMOS are
ON, this gives rise to short circuit
power [8].
The total power dissipation is the amount
of leakage and dynamic power.
Total Power = Pleakage + Pswitching + Pshort-
circuit
Pleakage is a function of {VDD , Vth , W/L},
and Pshort-circuit = ISC * VDD * f, where Ceff
is the effective capacitance, VDD is the
supply voltage, is the switching activity,
f is switching frequency and ISC is the
short-circuit current.
As technology progresses, the linear
dimension of the design is scaled usually
by a factor of 0.7, since that factor will
reduce the chip area by approximately half
of its original size [12]. As the process
technology decreases below 100nm, the
contribution of leakage power also
increases along with switching power.
According to reports, around 40 percent of
the total power is constituted by leakage
power at 65nm technology node [1]. And
HBRP Publication Page 1-11 2020. All Rights Reserved
Journal of VLSI Design and its Advancement
Volume 3 Issue 2
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due to the quadratic dependency of leakage
power on total number of transistors, it
makes reducing the leakage current as an
important objective. With every 10°C rise
in temperature of high-power devices, the
silicon failure rate is doubling, which
prioritizes the power reduction of deep
submicron nodes and nanometer
technologies [8].
From the view of power management, the
low power circuit consists of three
components they are: the design which is
divided into various power domains, the
power control circuitry containing level
shifter cells, retention cells, isolation cells.
And the power control logic [13].
Low Power techniques
The various low power design techniques
implemented in the design for power
reduction are:
Clock gating
The distribution networks of clock
contribute to around 50 percent of dynamic
power consumed. The clock buffers have
high switching rate and require larger
driving strength in order to minimize the
clock delay [4]. This clock signal can be
disable when not required by clock gating;
Since ,
and if the switching frequency that is * f
is reduced, this will significantly reduce
the switching power.
Multi Vt
In this technique MOSFETs with higher
threshold voltages are be used, in order to
reduce the sub-threshold conduction
(Pstatic). But its drawback is that the
transistor will take more time to turn ON.
Hence in blocks where performance
matters the most, low Vt or normal Vt cells
are used.
Multi VDD
Since all the power domains does not
require the same supply voltage,
Page 3

depending on the power requirement the
supply voltage can be reduced, where
some blocks use low power, and some be
completely shut off depending on the
mode of operation. Using multiple voltage
domains will reduce dynamic voltage. And
if two different power domains must
communicate then level shifter cells are
used between them to preserve the data
integrity.
Dynamic voltage scaling
It is a technique by which, the chip can
change its power supply value depending
upon the required performance, such as
sleep mode, standby mode, full power or
overdrive mode. This will reduce the
dynamic power consumption.
Power gating
If the power is not required to a particular
block, then it is turned off using switching
cells and this reduces the static power [2].
Fig. 1: ASIC Design Flow Showing FV and MVRC.
HBRP Publication Page 1-11 2020. All Rights Reserved
Journal of VLSI Design and its Advancement
Volume 3 Issue 2
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But in this case an isolation cell must be
inserted if the block turned off is a driver
of some other block.
Some or all the above discussed techniques
are implemented in a design to minimize
the power consumption, but at the same
time it is crucial to verify the working of
the design and if it is performing in the
intended way and that the data is not
getting corrupted due to any of this low
power techniques. To verify this Multi-
voltage rule check is needed where
additional cells are added for proper
functionality.
METHODOLOGY
The flowchart in Figure 1 is the ASIC
design flow from RTL to GDSII; it shows
the different stages where MVRC and
Formal verification are performed on the
design.
Page 4

Concepts of Multi-Voltage Rule Check
Unified power format (UPF)
The power management techniques can be
implemented at various levels of
abstraction from system-level to register
level or transistor level. A greater power
saving can be attained at higher level as
the main choices regarding timing, area
and power are done at higher abstraction
[15]. The amount of power that can be
saved decreases from system-level design
to transistor level. Hence to achieve
maximum power saving the power intent
must be combined with the logic at the
system level. The power intent can be
introduced either through Common Power
Fig. 2: UPF Flow.
UPF includes consistent semantics across
the design flow without being tied to one
tool or vendor. It is written in tcl, and
provides a concise and universal format
for specifying a design’s power intent
easily in one place for many elements in
the design. UPF file combined along with
the RTL is used to describe the power
intent of the design at a relatively higher
level [10].
Multi-voltage design elements
The different Multi-Voltage design
elements are discussed in the following
section:
Isolation (Iso) Cell
Consider a power domain with several
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Journal of VLSI Design and its Advancement
Volume 3 Issue 2
DOI: [To be assigned]
Format (CPF) or Unified Power Format
(UPF), which describes the power
structure of the design; CPF is a standard
adopted by Silicon Integration Initiative
[5]. UPF is an IEEE standard from
Accellera; it provides a universal format
for specifying a design’s power intent
easily in one place for many elements in
the design [4].
The goals of UPF are to:
 Capture power intent early in the
design flow, during RTL development
 Implement power intent consistently
throughout the flow
 Isolate HDL from Power Intent
sub-components, each of which can be
independently ON/OFF depending on the
requirement. In figure since P2 is
transmitting data to P3, so when P2
becomes OFF, the input at P3 becomes
undetermined (X) and it is propagated
throughout the circuit. In order to prevent
this Isolation cells are inserted which
retains the value of the circuit before it
went OFF [7]. The CLP tool checks if the
Isolation cells are inserted between OFF to
ON paths; that is between driver and
receiver, if the driver is power gated and it
turns off when not in use, it should not
transmit the wrong data to the receiver. If
the isolation cell is not present in such a
path the tool will report an error.
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Fig. 3: Inserting Isolation Cell in OFF to ON Path.
The two types of Isolation cells are:
 Clamp 1 Isolation Cell (e.g. OR gate)
 Clamp 0 Isolation Cell. (e.g. AND
gate).
Level Shifter Cell
Level shifter cells are used if there are
components with different power domains.
If a component with a power domain of
0.7V must send data to a 1.0V power
domain, the data must be shifted by the
level shifter cell before transmitting in
order to maintain the data integrity. It
basically translates values between two
power domains with different operating
voltages; this makes sure the data integrity
of the signal is maintained. Possible level
Shifters are: Low to High, High to Low or
Both Low to high, High to low (Employed
in a Dynamic Voltage Scaling design).
Retention Cell
Retention cell is used to store the register
state before power down mode. These
values will be restored when power is up.
So, retention cell be always on to serve the
purpose. As these are always ON, it can
consume power even in power down mode
[3].
Concepts of Formal Verification
Binary decision diagram (BDD)
BDDs are data structures that provide an
efficient way of representing the Boolean
function. The traditional truth table method
is very space consuming; it requires 2n
(n+1) entries for n variable function. But
by using BDDs this space can be reduced
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to a greater extent by removing the
redundant entries and duplicate sub-trees.
The BDD representation depends on the
ordering of the variables, for some order
there could be more reduction in the size
of BDD compared to others. But for a
given order of variables, the BDD has a
unique representation. There are reduction
algorithms that can be used to reduce the
BDD. Hence a wonderful property
emerges that is, for a given Boolean
equation by restricting the global ordering
of variables that can be obtained is a
canonical representation of BDD which
will always be the same and the
redundancy from the truth table is
significantly removed. Such reduced
BDDs are called Reduced Ordered Binary
Decision Diagram (ROBDD). An example
of BDD and ROBDD representation is
shown in Figure 4 for the function
̅ ̅ . Also, every node in a
BDD represents some Boolean function,
so it can be shared between multiple
functions and are called multi-rooted BDD
[17]; this will also result in reduction in
size. They are implemented in a bottom-up
fashion by building a set of operators and
joining them using recursive methods.
This helps in comparing logic
implementations [14] that are if two
functions are equivalent then they will also
have the same BDD representation as
BDDs are canonical and they have a
unique representation for a given function.
And if the functions are not logically
equivalent their BDDs will differ hence it
has to be verified to check for any
problems.
Page 6

Fig. 4: (a) BDD and (b) ROBDD Representation for
Boolean satisfiability (SAT)
SAT is another technique that can be used
for formal verification. The SAT problem
is to assign true/false to the literals
(variables) such that the final output of the
Boolean function is true. If for a given
Boolean expression the output cannot be
made true for any combination of inputs to
the literals, then it is unsatisfiable. SAT
problems are usually represented in
Conjunctive Normal Form (CNF), that is
any Boolean function written as the
conjunction of clauses, where each of the
clauses is the disjunction of literals. For
example:
f = (x1 ∨ x2) ∧ (x2 ∨ x3) ∧ (x2 ∨ x3 ∨ x5) ∧
(x4 ∨ x6 ∨ x5 ) ∧ (x1 ∨ x3 ∨ x5 ∨ x2)
Where ∧ represents AND, ∨ represents OR
and represents NOT operation.
Here x1 , x2, x2 , x3, x3 , etc., are the literals.
And (x1 ∨ x2), (x2 ∨ x3), etc. are the
clauses.
If somehow, all the clauses can be made as
true then the function f will be true, hence
it is satisfiable. But if f cannot be made
true for any combination of true/false of
the literals, then the function is
unsatisfiable. The Boolean Satisfiability is
a very famous problem in computer
science and math; it falls under the NP-
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̅ ̅ .
complete problems [20]. That means it
takes polynomial time to verify if the
solution is correct or not. But finding a
correct solution itself will take much
longer time. But that is under worst-case
condition, for a reasonably small function,
satisfiability can be proven in much lesser
time. Hence divide and conquer methods
are used to reduce the logic into small
pieces and then solving them using SAT.
There are also algorithms such as the
Davis-Putnam-Logemann-Loveland
(DPLL) algorithm, which can reduce its
complexity [16].
Cadence conformal logic equivalence
checking (LEC)
The Formal verification tool by Cadence is
Conformal LEC. Along with equivalence
checking it can also perform Clock-
domain-crossing (CDC) checks and
verifies multi-cycle paths and false paths
[11]. It considers some components in the
design as key points and logic cones to
divide the entire design. It checks the
logical equivalence of the netlist after each
stage by comparing it with the previous
stage netlist which is called Golden
(Reference) netlist. And the netlist that is
being verified is the revised netlist as
shown in Figure 5.
Page 7

Fig. 5: Comparison between Golden and Revised Netlist.
The various steps involved in LEC are:
Defining of key points
The LEC tool loads the golden and revised
design and finds out the key points. The
key points which are targeted are: Primary
inputs, Primary outputs, D flip-flop, D
latches, Blackboxes, TIE-Z cells (The LEC
tool inserts the TIE-Z cells to drive a
floating net), TIE-E cells (All the X-
assignments in the netlist are given to the
TIE-E cells), CUT gates (inserted in
combinational feedback loops to break
them; A combinational feedback loop is an
unregistered feedback loop which leads to
slew degradation).
Then Logic cones are formed which is a
combinational block that is bounded by
key points. The sink points of logic cones
are called as compare points and these
points will be used by the tool to map and
compare the two netlists.
Mapping of key points
At this stage the corresponding golden and
revised key points are paired. Mapping can
be done based on Name or Function. It can
be applied in both Setup and LEC modes.
a. Name based: The instance name of key
points in golden and revised design are
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Journal of VLSI Design and its Advancement
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compared and mapped.
b. Function based: The function of
compare points are used in golden and
revised design to map them.
Comparison of key points
The compare points are Sink points of
logic cones − Primary outputs, cut gates,
DFFs, D-latches, and Inputs of
Blackboxes. The tool loads the reference/
original design netlist and stores it as the
golden design. The tool then loads the
new/ updated design and stores it as the
revised design. The compare points in both
the designs are marked. The marked
compared points in the revised design are
mapped with its corresponding compared
points in the reference design. This
mapping step uses an algorithm which is
based on name of the compare point or the
functionality of the compare point. The
mapped points are then checked for the
equivalency and the equivalent and non-
equivalent points are reported. It is
important to note that only mapped points
can be compared.
The Cadence Conformal LEC flow mainly
consists of two modes namely, Setup mode
and LEC mode as shown in Figure 6.
Page 8

Fig. 6: Conformal LEC Flow.
The comparison report includes the
following classification:
Categories of mapped points
1. Equivalent: The compared points are
logically equivalent.
2. Inverted Equivalent: The compared
points are logically inverted.
3. Non-Equivalent: The compared points
are not equivalent and have different
functions
4. Abort: The compared points are not
yet proved because of timeout or some
other system parameter.
Categories of unmapped points
1. Extra: Key point that exists in only the
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Journal of VLSI Design and its Advancement
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Golden design or in only the Revised
design but does not affect the circuit
functionality. Example: scan_in,
scan_out
2. Unreachable: Key point that is not
propagated to any observable point.
Example: spare flops not connected,
scan flops blocked after constraining
3. Not-mapped: Key point which cannot
be mapped because there is no
correspondence on the other side.
Such points may be resolved with
renaming rules.
RESULTS AND DISCUSSION
BDD and SAT techniques provide a better
way to perform formal verification
Page 9

compared to the traditional simulation
techniques. But the problem with BDD is
that since they vary as the order of variable
changes, they do not always give the
smallest representation. So, for a bad
ordering there will be exponential growth
in the BDD representation [18]. In order to
overcome this, there are some algorithms
that can select the order dynamically to
give a better reduction but choosing the
order in a most efficient way is not
possible. Hence BDD based FV can be
used in cases where complete coverage is
required like in floating point arithmetic
and SAT based FV can be used in cases
where the design is larger, quick results are
required.
CONCLUSION
This paper gives a detailed literature
review of Multi-voltage rule check and
Formal verification techniques. It explains
the power dissipation in CMOS circuits,
various low pow techniques, and multi-
voltage design elements such as Isolation
cell, level shifter cell and retention cells. It
discusses the need for FV, and briefs the
underlying mathematics of FV that is BDD
and SAT. It also describes steps involved
in FV with respect to the Cadence
Conformal tool.
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