Module 2

CST 202 : Computer
Organization and
Architecture Module: 2
P R E PARED BY: AS HA ROS E T HOMAS
A P, CS E(A I) , ASIET,K A LA DY
3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

Processor Logic Design
Processor Arithmetic ALU result Complete design of
organization logic unit Processing ALU design accumulator.
Design of
Status Processor
arithmetic
register unit
circuit
Design of Design of
logic circuit shifter
Design of
arithmetic &
logic unit

SYLLABUS

Part 1-REGISTER TRANSFER LOGIC
❑Introduction
❑Inter-register Transfer
❑Arithmetic, logic and shift micro-Operations
❑Conditional control statement

Introduction
Digital system is a collection of digital hardware modules
EG for modules: registers, counters, arithmetic unit, etc
A module (eg: Register) consists of data and operation
◦ data
◦ operation (micro-ops)
◦ micro-ops are operations on data stored in registers

Introduction Cont…
Collection of modules connected via
◦data paths
◦control paths

Register Transfer Logic
Register Transfer Logic
◦The information flow and the processing task
among the data stored in the registers can be
described using RTL.

Types of Micro-Operations in digital system
Inter-register transfer micro-operation:
◦ Transfer the content of one register to another.
◦ Do not change the information content when the (binary) information moves from one
register to another.
Arithmetic micro-operation:
◦ Perform arithmetic on numbers stored in registers.
Logic microoperation:
◦ Perform operations such as AND and OR on individual pairs of bits stored in registers.
Shift microoperation:
◦ Perform shift operations on information stored in shift registers.

INTER REGISTER TRANSFER
Computer registers are designated by capital letters (sometimes followed by numerals) to
denote the function of the register.
✓ R1 - Processor Register(general purpose register’s)

✓MAR - Memory Address Register (holds an address for a memory unit)
✓PC - Program Counter
✓IR - Instruction Register
✓SR: Status Register

Representation of Register

Declaration of Registers
•For example: Registers in the above figure can be defined with declaration statement such as
DECLARE REGISTER A(8), MBR(12), PC(16)
DECLARE SUBREGISTER PC(L) = PC(1-8), PC(H) = PC(9-16).

➢Information transfer from one register to another is described by the notation
A←B
➢This statement denotes a transfer of the content of register B into register A
and this transfer happens in one clock cycle.
➢After the operation, the content of the B (source) does not change.
➢The content of the A (destination) will be lost and replaced by the new data
transferred from B.

Conditional transfer occurs only under a control condition: Representation of a (conditional)
transfer x’T1: A ← B.
➢A binary condition (x’T1 equals to 0 or 1) determines when the transfer occurs.
➢In this the content of B is transferred into A only if x is 0 and T1 is 1.
Hardware implementation of a controlled transfer:
x’T1: A ← B is as follows :-

INTERREGISTER TRANSFER MICROOPERATIONS Contd.
Destination receives information from two sources-Example
T1 : CA
T5 : CB

Basic symbols of Register Transfer Logic

Read Reference Text :Digital Logic and
computer Design-by Morris Mano:
8.2 Inter Register Transfer 308

Bus transfer
➢Paths is needed to transfer information from one register to
another in a digital computer
➢An efficient scheme is common bus system.

Bus transfer-cont..

Memory Transfer
Read operation :
Read: MDR←M
2. Write operation:
Write: M ← MDR
Note:
M-> a memory word/a memory location

Fig: Memory unit that communicate with
multiple registers -EG

ARITHMETIC, LOGIC AND SHIFT MICRO
OPERATION
Arithmetic Micro-Operation
Basic arithmetic micro-operations are:

1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Arithmetic shift.

Arithmetic Micro-Operation
Arithmetic add microoperations are defined by the statement
F←A+B
Explanation:
Contents of register A are to be added to the contents of register B and the sum is transferred
to register F

Arithmetic Micro-Operation cont..

Example
T2 : A ← A + B
T5 : A ← A + 1

Logical(LOGIC) Micro-Operations
❑Binary operations of bits stored in registers
❑Eg: F ← A ⊕ B (exclusive-OR micro-operation )
❑Let A =1010 and B=1100
❑Therefore, F= 0110

Shift Micro-Operations
❑Shift the contents of a register either left or right
❑Used along with arithmetic, logic, and other data-processing operations.
shl - shift left
shr - shift right
Example: A ← shl A 1-bit shift to the left of register A
B ← shr B 1-bit shift to the right of register B

Conditional Control Statements
Conditional control statement is symbolized by if-then-else statement in following manner
P : If (condition) then [microoperation(s)] else [microoperation(s)]
Example
T2 : If (C = 0) then (F  1) else (F  0)
Assume C and F are one bit register.

Computer Design-by Morris Mano:
8.2 Inter Register Transfer page 308
8.3 Arithmetic, Logic, and Shift Microoperations page 316
8.4 Conditional Control Statements page 321

PROCESSOR
ORGANIZATION

Introduction
➢Processor part of a computer is also referred to as data path of CPU.
➢The data paths are formed by means of buses.
➢Control gate that formulate given path are mux, decoders.
➢Processing of data is done by different function(Arithmetic or Logic).

Bus Organization
➢The registers in the processing unit are connected via two methods,
➢Common buses
➢Arrange them as small memory
➢Registers communicate with each other for data transfers and for
microoperations.

Processor registers and ALU connected
through common buses.

Processor registers and ALU connected
through common buses.
EG: R1  R2 + R3
Operation Steps.
1. MUX A Selector : place R2 contents onto bus A

2. MUX B Selector : place R3 contents onto bus B
3. ALU function selector : for arithmetic operation R2 + R3
4. Shift Selector : direct transfer from ALU to output bus
S( no shift)
5. Decoder destination selector : to transfer contents of
bus S into R1

Scratchpad Memory
➢Registers in a processor unit can be enclosed within a small memory unit – scratchpad memory
➢Consider a processor unit with 8 registers of 16 bits,ie 8x16 RAM
➢Eight registers are numbered from R0 through R7

Processor unit with scratchpad memory
Assume memory has 8 registers, 3 bits for addressing
R1  R2 + R3
Control must provide binary selection variables to

perform following sequence of 3 microoperations
T1 : A  M[010]
T2 : B  M[011]
T3 : M[001]  A + B

Processor with 2-port memory
Overcomes delay
▪2-port memory has two address lines to select two
words of memory simultaneously
▪A and B are latches
▪CP =1 , WE=1 :- A and B are open and reads data from
memory.
▪CP=0 , WE =0:- A and B are closed, if ME is enabled
result of microoperation written into B address
▪R1R2+R3 can be done in one clock pulse.
▪B address is fixed as destination address.

9.1 Introduction 358
9.2 Processor Organization 359

Arithmetic Logic Unit

ALU Design Steps
ALU Design
Arithmetic section Design
Logical section Design

Arithmetic & Logic section –
Combined
Combined Design
Arithmetic section modified
to incorporate logical
section

Block Diagram of a 4-bit ALU
▪Performs set of basic arithmetic & logic
operations
▪ALU has a number of selection lines to select
a particular operation.

Design of Arithmetic Section
▪Basic component of an ALU – Parallel Adder
▪ Parallel Adder is constructed with a number of full adder circuits connected in cascade.

Parallel adder operations

True/Complement, One/Zero circuit
Yi = Bi s0 + Bi ‘ s1
i=1,2,…n

4 BIT ARITHMETIC CIRCUIT

Parallel adder operations

FUNCTION TABLE FOR ARITHMETIC
CIRCUIT

4-bit Arithmetic circuit-All points

Design of Logic Circuit

Arithmetic Logic Unit - Combined

HOME WORK
Qn)Design an adder/Substracter circuit with one selection variable “s” and two input A and B.

9.3 Arithmetic Logic Unit 367
9.4 Design of Arithmetic Circuit 368
9.5 Design of Logic Circuit 376

Design of Arithmetic Logic Unit – From
Arithmetic Unit
▪More efficient ALU design
▪Able to generate logic operations in an already available arithmetic
circuit
▪Steps involved
▪Design the arithmetic section
▪Determine the logic operations obtained from arithmetic circuit in
step 1, assuming the input carries to all stages are 0
▪Modify the arithmetic circuit to obtain required logic operations.

FUNCTION TABLE

ALU Boolean Functions
▪Inputs to each full adder circuit
▪When s2 =0

Generation of logic operations
▪When s2 =1
▪ For s2s1s0 = 101 or 111(XOR and NOT operation)
▪ For s2s1s0 = 100 - provide the OR operation
▪ For s2s1s0 = 110 -provide the AND operation

FUNCTION TABLE

ALU DESIGN

ALU DESIGN –II METHOD-All points

9.6 Design of Arithmetic Logic Unit 378

STATUS REGISTER
➢ALU is connected with a register named “status register” where status bits
conditions(condition-codes/flag bits) are stored .
➢Bits are set or cleared as a result of an operation performed in the ALU.

Four status bits
Four status bits

Carry →Bit C : is set if output carry of ALU is 1
(cleared otherwise)
Sign → Bit S : is set if higher order bit of ALU
result is 1 (cleared otherwise)
Zero → Bit Z : is set if ALU result has all 0’s (ie. If
Z=1 result is zero,if Z=0 result is nonzero)
Overflow → Bit V : is set if exclusive OR of carries
C8 and C9 is 1 (cleared otherwise)

EXAMPLE(PERFORM (A-B))
⚫ A= 1 1 1 1 0 0 0 0 A: 11110000
⚫B=00010100 +(−B): 1 1 1 0 1 1 0 0
11011100
C=1 Z=0
S= 1
V=0

PROCESSOR UNIT

PROCESSOR UNIT
❑Control word
❑Usually stored in a memory unit called control memory.
❑Sequence of control words is read from control memory one word at a time , to initiate the desired
sequence of microoperations.
❑Selection variables (Control Variable)

❑Control variable Control’s microoperations executed within the processor during a given clock pulse.
❑Control ALU, buses, shifter, destination/source registers.

Processor unit with control variables
EG:OPERATION R1  R1 – R2 (cin=1)
A – 001
B – 010
D – 001
F – 010
Cin – 1
H – 000
16 bit Control word for the above operation

0010100010101000

Functions of control variable for the
processor

Examples of microoperations for
processor

9.8 Design of Status register 385
9.9 Processor Unit 386

Accumulator Register
❑Some processor units separate one register from all others .
❑ We call it an accumulator register, abbreviated AC or A register.

Sum of two numbers
To find the sum of two numbers stored in processor
registers, it is necessary to add them in the A register using
the following sequence of microoperations:

MICROOPERATIONS IN ACCUMULATOR
➢Accumulator is a
➢Special register
➢bidirectional shift register with parallel load
➢Designed by sequential circuit techniques
➢Multifunction register that can perform
microoperations in a processor unit

ASSIGNMENT 2
DESIGN OF ACCUMULATOR
DATE OF SUBMISSION 19/3/24

9.7 Status Register 382
9.10 Design of Accumulator 391

Design of Shifter
❑The shift unit which is attached to a processor, transfers the output of the ALU onto the output bus.
❑Shifter may shift the information to the right or left.
❑EXAMPLE

Design of 4-bit Combinational Logic
Shifter

MODULE TEST
1)Design a status register.(4 mark)
2) An 8-bit register A has one input x. The register operation is represented symbolically as
P: A7 ← x, Ai ← Ai+1, i = 0,1,2,3 ... 6. What is the function of the register?(3 mark)
3) Design a 4-bit combinational logic shifter with 2 control signals H1 and H0 that performs the following
operations (bit values given in parenthesis are the values of control variables H1 and H0 respectively):- No shift
(00), Shift-right (01), Shift left (10), Transfer 0's to S (11).(3 mark)
4) Design a 2 stage ALU.(6 mark)
5) Show the block diagram that executes the following conditional control statements
T1 : CA
T5 : CB
A, B, C are registers.(4 mark) P.T.O

6)With neat sketch explain the bus interconnection between processor registers and ALU.(5
mark).
7) Draw a labelled block diagram of a processor unit with sever registers R1 to R7, a status
register, ALU with 3- selection variables and Cin, and shifter with 3 selection variables.(5 mark)

Module 2

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Module 2

Uploaded by

Copyright:

Available Formats

CST 202 : Computer

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

✓ R1 - Processor Register(general purpose register’s)

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

➢An efficient scheme is common bus system.

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

Basic arithmetic micro-operations are:

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

1. MUX A Selector : place R2 contents onto bus A

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

Assume memory has 8 registers, 3 bits for addressing

Control must provide binary selection variables to

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

Logical section Design

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

3/17/2024 PREPARED BY ASHA ROSE THOMAS,AP,CSE(AI),ASIET,KALADY

▪ For s2s1s0 = 101 or 111(XOR and NOT operation)

▪ For s2s1s0 = 100 - provide the OR operation