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GNIOT Group of institution, Greater Noida

Department of Computer science Engineering
Affiliated to Dr. A.P.J. AKTU, Lucknow

LAB MANUAL
Department of Computer Science & Engineering
Subject Name: Computer Organization Lab
Subject Code: KCS-352
Session: 2021-22
Semester: 3rd

SUBMITTED TO: SUBMITTED BY:

Dr. HARERAM SINGH DHIRAJ KUMAR
SECTION- A
ROLL NO:2001320100048

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INDEX

S.NO NAME OF EXPERIMENT DATE PAGE SIGNATURE REMARKS

NO.
1. Implementing HALF ADDER,
FULL ADDER using basic logic
gates
2. Implementing Binary to Gray,
Gray to Binary code conversions
3. Implementing 3-8 line
DECODER and Implementing 4
X 1 and 8 X 1
MULTIPLEXERS
4. Verify the excitation tables of
Various Flip-Flops

5. Design of an 8-bit Input/Output

system with four 8-bit Internal
Registers
6. Design of an 8-bit
ARITHMETIC LOGIC UNIT

7. Design the data path of a

computer from its register
transfer language description

8. Design the Control unit of a

computer using either hardwiring
or microprogramming based on
its register transfer language
description
9. Write an algorithim and program
to perform matrix multiplication
of two n*n matrices on the 2-D
mesh SIMD model, Hypercube
SIMD model or multiprocessor
system

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GREATER NOIDA INSTITUTE OF TECHNOLOGY

To be leading institution in technical education providing education

Institute Vision and training enabling human resource to serve nation and world at
par with global standards in education

1) Developing state of art infrastructure which also includes

establishment of centre of excellence in pursuit of academic and
technical excellence
Institute Mission 2) Valuing work force inculcating belongingness and professional
integrity
3) To develop human resource to solve local, regional and global
problems to make technology relevant to those who mean it most

Department
Vision
To provide excellence by imparting knowledge to the learners
enabling them to become skilled professionals to be
recognized asa responsible citizen.

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1) Provide quality education in the field of computer science and

engineering through experienced and qualified faculty members.
2) Motivate learners for higher studies and research oriented activities
Department
Mission by utilizing resources of Centers of Excellence.
3) Inculcate societal values, professional ethics, team work, and
leadership qualities by having exposure at National and International
level activities.

Program Educational Objectives (PEOs)

Graduates of the program are expected to be employed in IT industry or

PEO1
Indulge in higher studies and research.
Graduates of the program are expected to exhibit curiosity to learn new technologies and
PEO2
work with ethical values and team work.
Graduates of the program are expected to design and develop innovative solutions related
PEO3
to real world problems of the society.

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Program Specific Outcomes (PSOs)

PSO 1 Solve complex problems using data structures and other advanced suitable algorithms.
Interpret fundamental concepts of computer systems and understand its hardware and
PSO 2
software aspect.
Analyze the constraints of the existing data base management systems and get experience on
PSO 3
large-scale analytical methods in the evolving technologies.
Develop intelligent systems and implement solutions to cater the business specific
PSO 4
requirements.

Program Outcomes (POs)

PO1 Engineering knowledge

PO2 Problem analysis
PO3 Design/development of solutions
PO4 Conduct investigations of complex problems
PO5 Modern tool usage
PO6 The engineer and society
PO7 Environment and sustainability
PO8 Ethics
PO9 Individual and team work
PO10 Communication
PO11 Project management and finance
PO12 Life-long learning

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EXPERIMENT NO: 1

AIM: - Implementing HALF ADDER, FULL ADDER using basic logic gates.

APPARATUS REQUIRED: Power supply, IC’s, Digital Trainer, Connecting leads.

BRIEF THEORY: We are familiar with ALU, which performs all arithmetic and logicoperation but
ALU doesn’t perform/ process decimal no’s. They process binary no’s.

Half Adder:It is a logic circuit that adds two bits. It produces the O/P, sum & carry.The Boolean
equation for sum & carry are:
SUM = A + B
CARRY = A. B
Therefore, sum produces 1 when A&B are different and carry is 1when A&B are 1. Application of
Half adder is limited.

Full Adder:It is a logic circuit that can add three bits. It produces two O/P sum & carry.The Boolean
Equation for sum & carry are:
SUM = A + B + C
CARRY = A.B + (A+B) C
Therefore, sum produces one when I/P is containing odd no’s of one & carry is one when there
are two or more one in I/P.

PROCEDURE:
(a) Connect the ckt. as shown in fig. For half adder.
(b) Apply diff. Combination of inputs to the I/P terminal.
(c) Note O/P for Half adder.
(d) Repeat procedure for Full wave.
(e) The result should be in accordance with truth table.
RESULT: The Half Adder & Full Adder circuits are verified.

PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

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EXPERIMENT NO. 2

AIM: Implementing Binary -to -Gray, Gray -to -Binary code conversions.

APPARATUS REQUIRED: Digital board DB06, DC Power Supply +5 V from external source or
ST2611 Digital lab, Digital Multimeter or Digital Lab ST2611.

BRIEF THEORY: The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital system. It is sometimes
necessary to use the output of one system as the input to another. A conversion circuit must be
inserted between the two systems if each uses different codes for the same information. Thus, a
code converter is a circuit that makes the two systems compatible even though each uses a
different binary code.

Procedure :
1. Connect +5 V and ground to their indicated position on experiment board from external DC
power supply or from DC power block.
2. Connect inputs B0, B1, B2, B3 as per truth table 2 to binary to gray code Converter.
3. Switch ON the power supply.
4. Observe output G0, G1, G2, G3 on multimeter or on LED Display.
5. Repeat above step for remaining inputs and prove truth table.
6. Repeat above steps for gray to binary code converter and prove truth table.

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EXPERIMENT NO. 3
AIM: Implementing 3-8 line DECODER and Implementing 4x1 and 8x1 MULTIPLEXERS.

APPARATUSREQUIRED:Power Supply, Digital Trainer, Connecting Leads, IC’s74153(4x1

multiplexer).

BRIEF THEORY:

MULTIPLEXER:Multiplexer generally means many into one. A multiplexer is acircuit with many
Inputs but only one output. By applying control signals we can steer any input to the output .The
fig. (1) Shows the general idea. The ckt. has n-input signal, control signal & one output signal.
Where 2n = m. One of the popular multiplexer is the 16 to 1 multiplexer, which has 16 input bits,
4 control bits & 1 output bit.

PIN CONFIGURATION:

IC 74153 (4x1 multiplexer)

(4x8 multiplexer)
PIN NAMES

S0–S2 Select Inputs

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E Enable (Active LOW) Input

I0–I7 Multiplexer Inputs

Z Multiplexer Output (Note b) Z’

Complementary Multiplexer Output

PROCEDURE:
1. Fix the IC's on the bread board &give the input supply.
2. Make connection according to the circuit.
3. Give select signal and strobe signal at respective pins.
4. Connect +5 V Vcc supply at pin no 24 & GND at pin no 12.
5. Verify the truth table for various inputs.

RESULT: Verify the truth table of multiplexer for various inputs.

3-8 LINE DECODER

BRIEF THEORY:
3-8 LINE DECODER is designed to be used in high-performance memory-decoding or datarouting
applications requiring very short propagation delay times. In high-performance memory systems,
this decoder can be used to minimize the effects of system decoding. When employed with high-
speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time
of the memory are usually less than the typical access time of the memory. This means that the
effective system delay introduced by the decoder is negligible. The conditions at the binary-select
(A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters
when expanding. A 24-line decoder can be implemented without external inverters and a 32-line
decoder requires only one inverter. An enable input can be used as a data input for
demultiplexing applications.

PIN CONFIGURATION:

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PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

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EXPERIMENT NO. 4
AIM: Verify the excitation tables of various Flip-Flops.
APPARATUS REQUIRED: IC’ S 7400, 7402 Digital Trainer & Connectingleads.

BRIEF THEORY:

• RS FLIP-FLOP:There are two inputs to the flip-flop defined as R and S. WhenI/Ps R = 0

and S = 0 then O/P remains unchanged. When I/Ps R = 0 and S = 1 the flip-flop is switches
to the stable state where O/P is 1 i.e. SET. The I/P condition is R = 1 and S = 0 the flip-
flop is switched to the stable state where O/P is 0 i.e. RESET. The I/P condition is R = 1
and S = 1 the flip-flop is switched to the stable state where O/P is forbidden.

• JK FLIP-FLOP:For purpose of counting, the JK flip-flop is the idealelement to use. The

variable J and K are called control I/Ps because they determine what the flip- flop does
when a positive edge arrives. When J and K are both 0s, both AND gates are disabled and
Q retains its last value.

• D FLIP –FLOP: This kind of flip flop prevents the value of D fromreaching the Q output
until clock pulses occur. When the clock is low, both AND gates are disabled D can change
value without affecting the value of Q. On the other hand, when the clock is high, both
AND gates are enabled. In this case, Q is forced to equal the value of D. When the clock
again goes low, Q retains or stores the last value of D. a D flip flop is a bistable circuit
whose D input is transferred to the output after a clock pulse is received.

• T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock edge, giving an
output which is half the frequency of the signal to the T input. It is useful for constructing
binary counters, frequency dividers, and general binary addition devices. It can be made
from a J-K flip-flop by tying both of its inputs high.

PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.

RESULT: Truth table is verified on digital trainer.

PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin

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EXPERIMENT NO. 5
AIM: Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.

BRIEF THEORY:
A universal shift register is an integrated logic circuit that can transfer data in three different
modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it can
load and transmit data in serial fashions, through left shifts or right shifts. In addition, the
universal shift register can combine the capabilities of both parallel and shift registers to
accomplish tasks that neither basic type of register can perform on its own. For instance, on a
particular job a universal register can load data in series (e.g. through a sequence of left shifts)
and then transmit/output data in parallel.
Universal shift registers, as all other types of registers, are used in computers as memory
elements. Although other types of memory devices are used for the efficient storage of very large
volume of data, from a digital system perspective when we say computer memory we mean
registers. In fact, all the operations in a digital system are performed on registers. Examples of
such operations include multiplication, division, and data transfer.
In order for the universal shift register to operate in a specific mode, it must first select the mode.
To accomplish mode selection the universal register uses a set of two selector switches, S1 and
S0.

The transfer of information from a bus into one of many destination registers can be
accomplished by connecting the bus lines to the inputs of all destination registers and activating
the load control of the particular destination register selected. The symbolic statement for a bus
transfer may mention the bus or its presence may be implied in the statement. When the bus is
includes in the statement, the register transfer is symbolized as follows:
BUS ← C, R1 ← BUS

The content of register C is placed on the bus, and the content of the bus is loaded into register
R1 by activating its load control input. If the bus is known to exist in the system, it may be
convenient just to show the direct transfer.
R1 ← C

From this statement the designer knows which control signals must be activated to produce
the transfer through the bus.
PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.

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EXPERIMENT NO. 6
AIM: Design of an 8-bit ARITHMETIC LOGIC UNIT.

BRIEF THEORY:
The arithmetic microoperations can be implemented in one composite arithmetic circuit. The
basic component of an arithmetic circuit is the parallel adder. By controlling the data inputs to
the adder, it is possible to obtain different types of arithmetic operations. It has four full-adder
circuits that constitute the 4-bit adder and four multiplexers for choosing different operations.
There are two 4-bit inputs A and B and a 4-bit output D. The four inputs from A go directly to the
X inputs of the binary adder. Each of the for inputs from B are connected to the data inputs of
the multiplexers. The multiplexer’s data inputs also receive the complement of B. The other two
data inputs are connected to logic-0 ad logic -1. Logic-0 is fixed voltage value (0 volts for TTL
integrated circuits) and the logic-1 signal can be generated through an inverter whose input is 0.
The four multiplexers are controlled by two selection inputs, S1 and S0. The input carry Cin goes
to the carry input of the FA in the least significant position. The other carries are connected from
one stage to the next. The output of the binary adder is calculated from the following arithmetic
sum:
D = A + Y + Cin

Where A is the 4-bit binary number at the X inputs and Y is the 4-bit binary number at the Y inputs
of the binary adder. Cin is the input carry, which can be equal to 0 or 1. Note that the symbol +
in the equation above denotes an arithmetic plus. By controlling the value of Y with the two
selection inputs S1 and S0 ad making Cin equal to 0 or 1, it is possible to generate the eight
arithmetic micro operations

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When S1 S0 = 00, the value of B is applied to the Y inputs of the adder. If Cin = 0, the output
D = A + B. If Cin = 1, output D = A + B + 1. Both cases perform the add microoperation with or
without adding the input carry.

When S1 S0 = 01, the complement of B is applied to the Y inputs of the adder. If Cin = 1, then D
=A +B+ 1. This produces A plus the 2’s complement of B, which is equivalent to a subtract with
borrow, that is, A – B – 1.

When S1S0 = 10, the input from B are neglected, and instead, all 0’s are inserted into the Y inputs.
The output becomes D = A + 0 +Cin. This gives D = A when Cin = 0 and D = A +1 when Cin =1. In
the first case we have a direct transfer from input A to output D. In the second case, the value of
A is incremented by 1.
When S1 S0 = 11, all 1’s are inserted into the Y inputs of the adder to produce the decrement
operation D = A –1 when Cin. This is because a number with all 1’s is equal to the 2’s complement
of 1 (the 2’s complement of binary 0001 is 1111). Adding a number A to the 2’s complement of 1
produces F = A +2’s complement of 1 = A – 1. When Cin = 1, then
D = A – 1 + 1 =A, which causes a direct transfer from input A to output D. Note that the
microoperation D = A is generated twice, so there are only seven distinct microoperations in the
arithmetic circuit.

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EXPERIMENT NO. 7

AIM: Design the data path of a computer from its register transfer language description.

Brief theory
This datapath circuit to be built requires several components that we will design and implement
and test individually. To facilitate successful implementation, verification and documentation of
complex designs, one should proceed in an incremental, modular fashion whereby each
component of a circuit is built and verified independently. The components are then put together
and may form another, larger component at the next level of the design hierarchy.
These combined components may then be combined to from even larger components and so on.
This continues to the top level of the design. This practice applies to the design of hardware,
software or any other system for that matter! Our final goal here is to design and implement the
logic for a hardware datapath that contains a simple arithmetic and logic unit (ALU) that can
perform low level processing.

Step 1 Decoder
The register file requires a 2‐line to 4‐line decoder with HI‐true outputs and one HI‐true enable
input as shown in the circuit of Step 4. This is similar to the decoder you designed in a previous
lab. Implement this component using the graphic design editor and test it in the MAX7000 device.

Step 2 Quad 4:1 MUX

The register file also requires a Quad 4:1 multiplexer. A Quad 4:1 MUX has four 4‐bit data

inputs, a 4‐bit data output and two select lines as shown below. Study the VHDL source code
given at the end of this lab that implements a Quad 4:1 multiplexer. Be sure you understand the
logic of the VHDL code. Compile this program, implement and test using the MAX7000 device.
Generate a symbol for this MUX which you will use later.

Step 3 Registers
The four registers R0, R1, R2 and R3 in the diagram below are to be implemented using the VHDL
code at the end of this lab. Each register comprises 4 positive edge‐triggered D flipflops. Each

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register has a 4‐bit input data and a 4‐bit output data. The clock input to all flipflops in the register
is defined as Clk. Compile this code and make a symbol for the register.
Step 4 Register File
Now we will design the register file using the graphic design editor by connecting the multiplexer,
decoder and four registers as shown below. Compile and test the register file circuit in the
MAX7000 chip to ensure that all four registers can be loaded using toggle switches on the
Data In lines, and read using LEDs connected at the Data Out lines. Be sure that you understand
the timing of the "load enable" input relative to all the other inputs and outputs.

Step 5 Datapath
The register file forms the basis of a "datapath" which is a fundamental building block of a
computer. See the diagram below. Data is selected from any register then stored back into any
other register in the register file, all in a single clock cycle ( a lo‐hi‐lo pulse applied to the load
enable LE input). A Quad 2:1 MUX included as shown below allows external data to be inserted
into the datapath. Data can thus be transferred between any two registers of our register file or
any register can be loaded with external data. This datapath can execute the following
operations:

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(a) any register can be loaded with external data from switches Rd ← data (4‐bits)
(where d=0,1,2 or 3)
(b) any register can be loaded with the data contained in any one of the other registers,
includingitself (register‐to‐register transfer) Rd ← Rs (where d, s = 0, 1, 2 or 3) The
implementation is shown below. The inputs [ D1, D0, S1, S0, DS ] form a 5‐bit "control" word
which specifies the source (S1, S0) and destination (D1, D0) registers of the register file and an
operation (DS) that is to take place. For DS=0, external data from switches is loaded into the
destination register; for DS=1, data is transferred from the source register to the destination
register. Once the control word and data input (if appropriate) are set on the level switches,
execution is achieved by applying a load enable (LE) input to the register file. This LE input may
be considered as the clock to the entire system. You can view the results of each operation
using four LEDs connected to the output of the register file as shown. Design this data path
using the graphic design editor. VHDL code for the Quad 2:1 MUX design is given at the end of
this lab. Test the circuit for various combinations of the register transfers summarized in the
following table.

Summary of register transfer operations

Note: (1) the first four lines of this table allow for initializing the register contents ( DS = 0 ).
(2) this is not a complete table of all possible microoperations that can execute
The VHDL source code for Quad 4:1 MUX
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY quad4to1mux IS
PORT ( a, b, c, d : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; s : IN
STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT
STD_LOGIC_VECTOR(3 DOWNTO 0) );
END quad4to1mux ;
ARCHITECTURE Behavior OF quad4to1mux IS
BEGIN
WITH s SELECT f <= a
WHEN "00", b
WHEN "01", c
WHEN "10", d
WHEN OTHERS ;
END Behavior ;

The VHDL source code for 4-bit Register

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY reg4 IS
PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

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Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END reg4 ;
ARCHITECTURE Behavior OF reg4 IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clk'EVENT AND Clk = '1' THEN Q <= D;
END IF;
END PROCESS ;
END Behavior ;

The VHDL source code for Quad 2:1 MUX

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY quad2to1mux IS
PORT ( a, b : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; s : IN
STD_LOGIC ;
f : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END quad2to1mux ;
ARCHITECTURE Behavior OF quad2to1mux IS
BEGIN
f <= a WHEN s='0' ELSE b ;
END Behavior

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EXPERIMENT NO. 8

AIM: Design the control unit of a computer using either hardwiring or microprogramming
based on its register transfer language description.
BRIEF THEORY
The purpose of this laboratory is to design and implement the control unit to provide control
signals to the 32-bit CPU data-path.

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Most of the control unit outputs all the control signals for the Registers, ALU and MUXes in the
datapath. It accepts as input the status bits (Zero and Carry) and the INST for instruction decisions
(Note: the diagram shows the entire INST as input to the control unit. However, if we refer back
to the CPU specification document, only INST[31..28] - opcode - and INST[27..24] function code -
arerequired). All instructions require 3 clock cycles to execute. Moreover, in situations when we
desire toinitialize or reset the CPU, an enable/reset input is needed. Please note that a control
signal required by the data-path, CLR PC is not produced by the control unit.The clearing of the
program counter occurs during initialization. Reset signal for the CPU and CLR PC are generated
by a reset circuit.
When we investigate the internal structure of the control unit, it can be divided it into three parts
(VHDL processes), namely a sequential state generator (for T0, T1 and T2), a memory signal
generator (for wen and en setup and hold times), and a combinational circuit for the decoding
operations. A brief description of these processes is given below.

State Generator
The state generator circuit is the synchronous, sequential component of the control unit. It
generates appropriate state signals based on the clock and the current state of the system. It also
generates a set of pulse signals T that can be used to indicate the current state of the instruction
being executed. (shown here for three states).

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Note: When ENABLE signal is not asserted, the circuit should go to state T0 and remain in this
state until the ENABLE signal is asserted again. At that point, the circuit resumes normal
operation.

Operation Decoder
The operation decoder is responsible for correctly setting the control signals being fed to the
data-path during instruction execution. It requires the current state, status bits (C and Z) and the
INST contents to determine which instruction to execute. Essentially, the operation decoder is
nothing more than an ifelse type of statement (MUX), which sets the control signals
appropriately. We have determined the correct settings of the control signals for each operation
in the data-path lab. Note that it is wise to use case statements to successfully synthesize the
VHDL for decoding all the CPU instructions.

Memory Signal Generator

To support the load and store instructions, the Write Enable (wen) and Enable (en) signals have
been included in the control unit specification. Assume the signal is active high; the signal must
be asserted correctly during the store and load operations as specified in memory lab manual
and cpu_specification document. The wen and en are sensitive to the Clk, mclk, and INST given.
The process template is given in the code on the next page for setting up "en" and "wen" in the
"Data Memory Instructions" process. Fill in the code with the appropriate values for "en" and
"wen" according to the template given in the specifications to achieve correct setup and hold
times for your CPU's memory operations.

VHDL Implementation
The declaration below is provided as a possible reference:
library ieee;
use ieee.std_logic_1164.ALL;
ENTITY control IS
PORT(
clk, mclk : IN STD_LOGIC; enable :
IN STD_LOGIC;
statusC, statusZ : IN STD_LOGIC;
INST : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
A_Mux, B_Mux : OUT STD_LOGIC;
IM_MUX1, REG_Mux : OUT STD_LOGIC;
IM_MUX2, DATA_Mux : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

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ALU_op : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

inc_PC, ld_PC : OUT STD_LOGIC;
clr_IR : OUT STD_LOGIC; ld_IR : OUT
STD_LOGIC;
clr_A, clr_B, clr_C, clr_Z : OUT STD_LOGIC; ld_A, ld_B,
ld_C, ld_Z : OUT STD_LOGIC;
T : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
wen, en : OUT STD_LOGIC);
END control;
ARCHITECTURE description OF control IS
TYPE STATETYPE IS (state_0, state_1, state_2, etc...);
SIGNAL present_state: STATETYPE;
BEGIN
-------- OPERATION DECODER ---------
PROCESS (present_state, INST, statusC, statusZ, enable)
BEGIN
-------- YOU FILL IN WHAT GOES IN HERE (DON'T FORGET TO CHECK FOR ENABLE)
-------- OUTPUT ASSIGNMENTS
END process;
-------- STATE MACHINE ---------
PROCESS (clk, enable)begin
-------- YOU FILL IN WHAT GOES IN HERE
END process;
-------- DATA MEMORY INSTRUCTIONS --------- PROCESS
(mclk, clk, INST)
BEGIN
IF(mclk'EVENT and mclk = '0') THEN
IF(present_state = state_1 AND clk = '0') THEN
--LDA and LDB Signals
--STA and STB Signals
--Default Case Signals
ELSIF(present_state = state_2 AND clk = '1') THEN
--LDA and LDB
--STA and STB
--Default Case
ELSIF(present_state = state_1) THEN --or alternatively just an ELSE statement
--fill in
END IF;
END IF;
END process;

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 lOMoARcPSD|16087745

EXPERIMENT NO. 9

AIM: Write an algorithm and program to perform matrix multiplication of two n * n matrices on
the 2-D mesh SIMD model, Hypercube SIMD Model or multiprocessor system.

BRIEF THEORY
The pipeline for matrix multiplication example has 4 stages. These are:
1. A = a[i][k],B = b[k][j]
2. P = A * B
3. if (k=0) then Sum = Pelse
Sum = P + Sum
4. if (k=7) then c[i][j] = Sum,if
(count=511) then done=1

Source listing for pipelined implementation of the Matrix Multiplication example is given below.
The matrix.vhd file multiplies two 8 × 8 matrices that have initialized with some arbitrary integers.
The test bench compares the results of the matrix muplicator to the correct results. Note how
the states S1, S2, S3 fill up the pipline and how the states S5, S6, S7 flush the pipeline. In state S4
the pipeline is full and all stages are simultaneously active (ofcourse, on different sets of data).

VHDL Implementation

library IEEE; use

IEEE.std_logic_1164.all; use
IEEE.std_logic_arith.all;

entity mult is port ( Clk : in

STD_LOGIC;
Start : in STD_LOGIC;
Done : out STD_LOGIC;
Dout : out INTEGER); end mult;

architecture sequential of mult is

signal Count0, Count1 : UNSIGNED (8 downto 0):="000000000"; signal
Count2, Count3 : UNSIGNED (8 downto 0):="000000000";
signal A, B, P, Sum : INTEGER;
begin process(Clk) type STATE_VALUE is (S0, S1, S2, S3, S4, S5, S6,
S7, S8);
type RF is array (0 to 7, 0 to 7) of INTEGER; variable
i0, j0, k0, k2 : INTEGER; variable i3, j3, k3 :
INTEGER; variable State : STATE_VALUE := S0;

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 lOMoARcPSD|16087745

-- some random numbers for the A matrix

variable A_Matrix : RF := (
(1, 1, 2, 3, 4, 5, 6, 7),
(8, 9, 0, 1, 2, 3, 4, 5),
(6, 7, 8, 9, 1, 3, 4, 5),
(4, 1, 2, 3, 4, 5, 6, 7),
(8, 9, 0, 1, 2, 3, 4, 5),
(6, 7, 8, 9, 1, 3, 4, 5),
(7, 1, 2, 3, 4, 5, 6, 7),
(8, 9, 0, 1, 2, 3, 4, 5));

-- some random numbers for the B matrix

variable
B_Matrix : RF := (
(6, 7, 8, 9, 1, 3, 4, 9),
(0, 1, 2, 3, 4, 5, 6, 7),
(8, 9, 0, 1, 2, 3, 4, 8),
(0, 1, 2, 3, 4, 5, 6, 7),
(6, 7, 8, 9, 1, 3, 4, 5),
(8, 9, 0, 1, 2, 3, 4, 5),
(8, 9, 0, 1, 2, 3, 4, 5),
(0, 1, 2, 3, 4, 5, 6, 7)); variable

C_Matrix : RF;

begin
if (Clk'event and Clk = '1') then
i0 := CONV_INTEGER( Count0( 8 downto 6 ) );
j0 := CONV_INTEGER( Count0( 5 downto 3 ) ); k0 :=
CONV_INTEGER( Count0( 2 downto 0 ) );

k2 := CONV_INTEGER( Count2( 2 downto 0 ) );

i3 := CONV_INTEGER( Count3( 8 downto 6 ) ); j3 :=

CONV_INTEGER( Count3( 5 downto 3 ) ); k3 :=
CONV_INTEGER( Count3( 2 downto 0 ) );

case State is

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 lOMoARcPSD|16087745

-- State S0 (wait for start signal)

when S0 =>
Done <= '0';
Count0 <= "000000000";
if( Start = '1' ) then
State := S1; else
State := S0;
end if;

-- State S1 (filling up of pipeline)

when S1 =>
A <= A_Matrix(i0, k0);
B <= B_Matrix(k0, j0);
Count1 <= Count0;
Count0 <= Count0 + 1;
State := S2;

-- State S2 (more of filling up)

when S2 =>
A <= A_Matrix(i0, k0); B
<= B_Matrix(k0, j0);

P <= A * B;
Count2 <= Count1;
Count1 <= Count0;
Count0 <= Count0 + 1;
State := S3;

-- State S3 (even more of filling up)

when S3 =>
A <= A_Matrix(i0, k0); B
<= B_Matrix(k0, j0); P
<= A * B;

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 lOMoARcPSD|16087745

if (k2 = 0) then
Sum <= P; else
Sum <= Sum + P;
end if;
Count3 <= Count2;
Count2 <= Count1;
Count1 <= Count0;
Count0 <= Count0 + 1;
State := S4;

-- State S4 (pipeline full, complete work)

when S4
=>
A <= A_Matrix(i0, k0);
B <= B_Matrix(k0, j0);
P <= A * B; if (k2 = 0)
then
Sum <= P; else
Sum <= Sum + P;
end if;

if (k3 = 7) then
C_Matrix(i3, j3) := Sum; end
if;

Count3 <= Count2;

Count2 <= Count1;
Count1 <= Count0;

check if all initiations done

if
(Count0 = 511) then
State := S5; else
State := S4;
Count0 <= Count0 + 1; end
if;

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 lOMoARcPSD|16087745

-- State S5 (start flushing the pipeline)

-
when S5 => P <= A *
B;

if (k2 = 0) then
Sum <= P; else
Sum <= Sum + P; end
if;

if (k3 = 7) then
C_Matrix(i3, j3) := Sum; end
if;
Count3 <= Count2;
Count2 <= Count1;
State := S6;

-- State S6 (more of flushing)

when S6 =>
if (k2 = 0) then
Sum <= P;
else
Sum <= Sum + P;
end if;

if (k3 = 7) then
C_Matrix(i3, j3) := Sum;
end if; Count3 <= Count2;
State := S7;

-- State S7 (completion of flushing)

when S7 =>
if (k3 = 7) then
C_Matrix(i3, j3) := Sum;
end if; State := S8;
Count0 <= "000000000";
Done <= '1';

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 lOMoARcPSD|16087745

-- State S8 (output the data)

when S8 =>
if( Count0 = 63 ) then
Count0 <= "000000000";
State := S0; else
Count0 <= Count0 + 1;
State := S8;
end if;
Dout <= C_Matrix( j0, k0 ); end
case;
end if;
end process;
end sequential;

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