. + a ¢ = s ote ; nee \I/ 100 DAYS OF RTL DAY 31 - SCAN CELL BY MAAZ AHMED ; eteNon-scan SE DFLIP FLOP so ck INTRODUCTION Ascan cell, also known as a scan flip-flop, is a type of flip-flop that includes additional functionality for testing and debugging digital circuits. It provides a mechanism for observing and controlling the internal states of a sequential logic circuit, which can be useful for various purposes such as functional testing, diagnosis of faults, and design validation. The primary feature of a scan cell is the inclusion of scan enable (se) and scan input (si) control inputs. When the scan enable signal is asserted, the flip-flop enters scan mode, allowing the external scan input signal to override the data input of the flip-flop. This enables the injection of specific test patterns or values into the flip-flop's internal state, independent of the circuit's normal operation. USECASE « Scan-based testing is widely used in the manufacturing testing of ICs. By inserting scan cells into the design, test patterns can be serially shifted into the circuit, and the responses can be serially shifted out for analysis. This method enables efficient and thorough testing of complex ICs, helping to identify and diagnose manufacturing defects. Scan cells are used during the design verification and validation phase to verify the correctness and functionality of digital designs. They facilitate the application of specific test patterns to the circuit and allow designers to observe and analyze the behavior of the design under various conditions. The Joint Test Action Group (JTAG) standard, also known as IEEE 1149.1, defines a serial test access port (TAP) controller that enables boundary scan testing of ICs. Scan cells are used as part of the boundary scan chain to provide access to internal circuit nodes for testing and diagnosis purposes.CODE module SCANCELL(d,si,se,clk,reset,so); input d,si,se,clk,reset; output so; wire mo; MUX2x1 A(se,d,si,mo); D_FlipFlop B(mo,clk,reset,so); endmodule module D_FlipFlop ( inputd, // Data input input clk, // Clock input input reset, // Reset input output reg q // Output always @(posedge clk or posedge reset) begin if (reset) q<=1'b0; // Reset state else q<=d; //D input is transferred to Q on clock edge end endmodule module MUX2x1 ( input sel, // Selection input input dO, // Data input 0 input d1, // Data input 1 output reg out // Output \ always @(*) begin case (sel) 1'b0: out = dO; 1'b1; out = d1; default: out = 1'b0; endcase end endmoduleTESTBENCH module testbench; reg d, si, se, clk, reset; wire so; SCANCELL scan_cell(.d(d),.si(si),.se(se),.clk(clk),.reset(reset),.so(so)) always begin clk = 0; forever #10 clk = ~clk; end initial begin reset = 1; #50; reset = 0; end initial begin // Apply test vectors d=0;si=0;se=0; #100; d=1;si=0;se=1; d=1;si=1;se=0; #100; d=1;si=1;se=1; #100; d=0; si =0;se=0; #100; $finish; end endmoduleSCHEMATIC ( SIMULATION WAVEFORM