AN238230

Quad SPI master emulation using AURIX™ GTM

About this document

Scope and purpose
This application note introduces how to emulate Quad SPI master with AURIX™ Generic Timer Module (GTM).

Intended audience
This document is intended for engineers who are familiar with Infineon AURIX™ GTM and want to use Infineon
QSPI flash devices in Quad SPI mode with AURIX™ MCU.

Application note Please read the sections “Important notice” and “Warnings” at the end of this document 002-38230 Rev. **
www.infineon.com 2023-07-18
Quad SPI master emulation using AURIX™ GTM

Table of contents

Table of contents
About this document ....................................................................................................................... 1
Table of contents ............................................................................................................................ 2
1 Introduction .......................................................................................................................... 3
2 Quad SPI signals and protocol ................................................................................................. 4
2.1 QSPI flash Quad SPI signals .................................................................................................................... 4
2.2 Quad SPI protocol ................................................................................................................................... 4
3 Signal mapping between Quad SPI flash and AURIX™ GTM .......................................................... 7
4 Quad SPI master emulation ..................................................................................................... 8
4.1 Required resources ................................................................................................................................. 8
4.2 Test conditions and limitations .............................................................................................................. 8
4.3 Test setup ................................................................................................................................................ 9
4.4 Emulation overview ................................................................................................................................ 9
4.5 GTM control flow ................................................................................................................................... 10
4.6 Software control flow ............................................................................................................................ 10
4.7 QSPI IOx emulation ............................................................................................................................... 12
4.8 ARU configuration ................................................................................................................................. 13
4.9 FIFO handling ........................................................................................................................................ 13
5 Conclusion ...........................................................................................................................14
References ....................................................................................................................................15
Revision history.............................................................................................................................16
Disclaimer.....................................................................................................................................17

Application note 2 002-38230 Rev. **

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Quad SPI master emulation using AURIX™ GTM

Introduction

1 Introduction
The AURIX™ SPI controller supports only single SPI protocol (queued SPI). However, it is possible to emulate
Quad SPI master with AURIX™ GTM so that users can use external QSPI flash with AURIX™ in Quad SPI mode to
achieve better read performance. This will improve the read performance by a factor of four.
Infineon Application Engineering team has implemented the emulation and verified with Infineon QSPI flash on
Infineon AURIX™ evaluation board.
The emulation is implemented and tested with Infineon AURIX™ TC375 Lite Kit board. Infineon S25FL-L series
QSPI flash and S25HL-T SEMPER™ Flash are tested. It can also be a reference for users who want to use other
Infineon QSPI flash devices in Quad SPI mode with AURIX™.

Figure 1 AURIX™ TC375 Lite Kit board V2 top view

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Quad SPI master emulation using AURIX™ GTM

Quad SPI signals and protocol

2 Quad SPI signals and protocol

2.1 QSPI flash Quad SPI signals
Table 1 lists the required flash signals for Quad SPI mode. Flash Quad mode needs to be enabled by configuring
Configuration Register. See S25FL-L and S25HL-T datasheets for information on how to enable Quad mode.

Table 1 QSPI flash Quad SPI signals

Signal name I/O type Description
SCK Input Serial
FL1-K clock
CS# Input FL-P
Chip select
SI/IO0 I/O Serial input
For single bit data commands input
Or IO0 for Dual or Quad commands.
SO/IO1 I/O Serial output
For single bit data commands output.
Or IO1 for Dual or Quad commands.
IO2 I/O IO2 when in Quad mode

IO3 I/O IO3 when in Quad mode

2.2 Quad SPI protocol

Figure 2 shows the Quad I/O command protocol. The gray bits are optional, and the host does not have to drive
bits during that cycle. The instruction is transferred from the host to the flash device on SI/IO0.

Figure 2 Quad I/O command protocol

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Quad SPI master emulation using AURIX™ GTM

Quad SPI signals and protocol

Figure 3 shows the Quad I/O command in QPI mode. The gray bits are optional, and the host does not have to
drive bits during that cycle. The instruction is transferred from the host to the flash device on IO0~IO3.

Figure 3 Quad I/O command in QPI mode

All communication between the host system and the QSPI flash device is in the form of units called commands.
All commands begin with an 8-bit instruction that selects the type of information transfer or device operation
to be performed. Commands may also have an address, latency period, data transfer to the flash, or data
transfer from the flash. All instruction, address, and data information are transferred sequentially between the
host system and flash device.
Quad SPI commands are structured as follows:
• Each command begins with CS# going LOW and ends with CS# returning HIGH. The flash device is selected
by the host driving the Chip Select (CS#) signal LOW throughout a command.
• The serial clock (SCK) marks the transfer of each bit or group of bits between the host and flash device.
• Each command begins with an eight-bit (byte) instruction. The instruction transfers occur on SCK rising
edges.
• The instruction may be stand alone or may be followed by address bits to select a location within the flash
device. The address transfers occur on SCK rising edge in SDR commands.
• The transfers following the instruction (i.e., address, data) are in 4-bit groups per transfer on the IO0-IO3
signals. Within the 4-bit groups, the least significant bit is on IO0. More significant bits are placed in
significance order on each higher numbered IO signal. Single bits or parallel bit groups are transferred in
most to LSb order.
• The address may be followed by write data to be stored in the flash device or by a read latency period before
read data is returned to the host.
• Write data bit transfers occur on SCK rising edge in SDR commands.
• SCK continues to toggle during any read access latency period. The latency may be zero to several SCK
cycles. At the end of the read latency cycles, the first read data bits are driven from the outputs on SCK
falling edge at the end of the last read latency cycle. The first read data bits are considered transferred to the
host on the following SCK rising edge. Each following transfer occurs on the next SCK rising edge in SDR
commands.
• If the command returns read data to the host, the flash device continues sending data transfers until the
host takes the CS# signal high. The CS# signal can be driven high after any transfer in the read data
sequence. This will terminate the command.
• At the end of a command that does not return data, the host drives the CS# input HIGH. The CS# signal must
go HIGH after the eighth bit of a standalone instruction or, of the last write data byte that is transferred.
Therefore, the CS# signal must be driven HIGH when the number of bits after the CS# signal was driven LOW
is an exact multiple of eight bits. If the CS# signal does not go HIGH exactly at the eight-bit boundary of the
instruction or write data, the command is rejected and not executed.
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Quad SPI master emulation using AURIX™ GTM

Quad SPI signals and protocol

• All instruction addresses are shifted into the flash device with the MSb first. The data bits are shifted in and
out of the flash device MSb first. All data is transferred in byte units with the lowest address byte sent first.
Following bytes of data are sent in lowest to highest byte address order i.e., the byte address increments.

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Quad SPI master emulation using AURIX™ GTM

Signal mapping between Quad SPI flash and AURIX™ GTM

3 Signal mapping between Quad SPI flash and AURIX™ GTM

Table 2 shows the proposed signal mapping between QSPI flash and AURIX™ GTM for the emulation.

Table 2 Signal mapping between QSPI flash and AURIX™ GTM

QSPI flash signal I/O type[1] AURIX™ GTM resource
SCK Input FL1-K
ATOM0_4 (out[3])
FL-P
CS# Input ATOM0_3 (out[3])

SI/IO0 I/O TIM0_1 (in[2]) / ATOM0_1 (out[3])

SO/IO1 I/O TIM0_0 (in[2]) / ATOM0_0 (out[3])

IO2 I/O TIM0_2 (in[2]) / ATOM0_2 (out[3])

IO3 I/O TIM0_5 (in[2]) / ATOM0_5 (out[3])

Note:

1. I/O type is in term of flash device. E.g., Input means input for flash device
2. in is in terms of GTM, i.e., input for GTM
3. out is in terms of GTM, i.e., output for GTM

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Quad SPI master emulation

4 Quad SPI master emulation

4.1 Required resources
• 1 GTM cluster
− 8 ATOM channels
− 7 TIM channels
− MCS (soft requirement)
• 1 GTM PSM
− 8 FIFO channels
− 8 A2F streams
• 200/400 Mbit/s GTM ARU
− Low CEND or
− Dynamic routing
• GTM CMU
− 3 CMU clocks (2 divided and 1 routed via TIM_EXT_TRIGGER)
• 5 fast pins and 1 slow pin connected to the same cluster
− 4 Data pins with TIM and ATOM connected
− 1 Clock pin with ATOM connected
− 1 CS pin with ATOM connected (slow)
• DMA
− 2 DMA channels

4.2 Test conditions and limitations

The emulation tests are functional tests only, which prove the emulation approach works. The tests were done
at room temperature, without swiping cross voltage and temperatures.
The maximum Quad SPI SDR clock frequency supported by this emulation is 50 MHz. This is substantially
improving the read throughput from 6.25 MB/s to 25 MB/s.
The GTM has some of the following limitations:
• Timing between pin output and input switching
− Lower bandwidth due to clock freeze (100 – 300 ns)
• Back-to-back transfers is not possible
− GTM requires new setup time.
− Data conversion can be parallelized
• Preloading of large TX transaction due to high GTM register latency
• Pin selections is difficult
− ATOM/TIM in the same cluster
− Fast pads for good signal quality
• Higher CPU load
− Transforming read and write buffers from/into Quad SPI buffers
• High load on ARU

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Quad SPI master emulation

4.3 Test setup

Prior to the emulation test, the following setup is needed:
• Configure AURIX™ GTM in single SPI mode
• Enable QUAD bit in Configuration Register of flash (for Quad I/O test, i.e., the instruction is transferred from
the host to the flash device on SI/IO0), or enable QPI bit in Configuration Register of flash (for QPI test, i.e.,
the instruction is transferred from the host to the flash device on IO0~IO3)
• Activate AURIX™ GTM in Quad SPI mode

4.4 Emulation overview

Figure 4 shows the overview of the emulation.

FIFO TIM
SDIO0
FIFO ATOM

RX DMA
FIFO TIM
SDIO1
FIFO ATOM

FIFO TIM
SDIO2
FIFO ATOM

TX DMA
FIFO TIM
SDIO3
FIFO ATOM

ATOM SCK

ATOM CS

DMA GTM PORT

Figure 4 Emulation overview

SPI output: ATOM in serial shift out mode with data read from FIFOs through the ARU
• SPI input: TIM in serial shift in mode with data send to FIFOs through the ARU
• SPI clock: ATOM in PWM mode (clock continuous waveform)
• SPI CS: ATOM in PWM mode (single waveform)
• SPI transfer: ATOM in PWM mode and MCS
• Buffer management
− Adapting to GTM format (24-bit words) and byte order
− Merging and splitting bits into lanes through TriCore™ instructions (BSPILT and BMERGE)
• Bidirectional pins
− Output drivers are enabled and disabled through software
− Clock is stopped until output drivers are disable
• DMA
− DMA relives the CPU from expansive GTM accesses

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Quad SPI master emulation

4.5 GTM control flow

Figure 5 shows the GTM emulation architecture.

CMU ARU FIFO

SDIO0 TIM ATOM SDIO0

SDIO1 TIM ATOM SDIO1

SDIO2 TIM ATOM SDIO2

SDIO3 TIM ATOM SDIO3

TIM ATOM SCK

Sync Forward TIM ATOM CS

Sync Trigger TIM ATOM Bit counter

Clock Forward TIM ATOM TIM sample clock

MCS AGC

Figure 5 GTM emulation architecture

GTM control flow is as follows:

1. Setup transfer
2. Enable Sync TIM -> Sync Pulse + Sync Forward enable ATOM channels
3. MCS waits for Sync Pulse and prepare ATOM channel disable
4. Bit Counter triggers disable of ATOM Channels except CS
5. Change Port direction
6. MCS starts SCK, TIM clock, new RX bit counter and prepare ATOM channel disable
7. Bit Counter triggers disable of ATOM Channels except CS
8. MCS waits for CS trigger and disables CS
9. MCS waits for full transfer in TIM channels and disables TIM channels
Step 9 is only required for RX and Steps 5 to 7 is only required for Quad RX.

4.6 Software control flow

Software control flow is as described below:
1. Convert write buffer into ATOM format and place it into FIFO or DMA buffer
− Quad TX transfers use optimized BSLIPT instruction to split data into 4 lanes
2. Setup DMA transactions
3. Setup GTM
4. Start transfer
5. Wait for CS high interrupt or RX DMA complete interrupt
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Quad SPI master emulation

6. Read data from FIFO or DMA buffer and place it into read buffer
− Quad RX transfers use optimized BMERGE instruction to merge data from 4 lanes
Software can run in FIFO mode or DMA mode for both RX and TX.
Bitcounter interrupt for port direction change with high priority is enabled if needed (Quad RX).

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Quad SPI master emulation

4.7 QSPI IOx emulation

Figure 6 shows how to emulate QSPI IOx signal.

FIFO0_CH0 ATOMx_Chy

IOx
ARU

FIFO0_CH1 TIMx_CHy

Figure 6 QSPI IOx emulation

• To emulate IOx, ATOMx_Chy, and TIMx_CHy with common pin Pa.b are used. The input from the pin is
always connected to the TIM channel and the output from the ATOM channel is enabled via software to align
with the Quad SPI protocol, otherwise the output is disabled.
• For output, ATOMx_Chy is set to SOMS mode with ARU_EN =1. Command, ADDR and data to be transmitted
is stored in the corresponding FIFO channel. The output is clocked with CMU_CLK1 running at SCK
frequency. CMU_CLK1 is not used for SCK generation to adjust to internal delay but a dedicated ATOM
channel running with CMU_CLK0 (CMU_CLK0 > CMU_CLK1).
• For input capture of data transmitted from memory, TIMx_CHy is set to TSSM mode with ARU _EN =1 (to
enable data transfer to FIFO). Data incoming from memory is captured in burst of 24 bits into GPR0 register
and then automatically transferred to the corresponding FIFO channel. As capture clock a dedicated bit
clock generate via an ATOM channel in SOMP mode and sourced via the CMU_CLK7 is used. This clock can
also be used to adjust the sample point in 5 ns steps. The bit clock is enabled at the time where the first bit is
received to align the incoming data to the 24-bit of the TIM channel.

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4.8 ARU configuration

ARU has a fixed round trip time in default round robin mode. For example, it is 1.2 µs. Reduce the roundtrip
time of the ARU by cutting short the number of addresses serviced by the ARU within GTM.
Limit the ARU address list to only until ATOM0_CH3 as only these are the channels used in the application with
ARU.
Set ARU_CADDR_END = 32. Resulting ARU RTT = (32+1) * 10 ns = 330 ns
While the shortest time between two captured 24-bits transfer via is 24*SCK. In case of SCK 50 MHz, Capture
time = 24*20 ns = 480 ns.

4.9 FIFO handling

• GTM offers three FIFOs, each with 1024 words of storage (words size is 29 bits)
• Each FIFO offers eight independent channels (0-7), which share the memory of 1024 words between them.
Each with minimum configurable size of 128 words
• Each FIFO channel offers its own LOWER and UPPER watermarks which can be used to trigger DMA transfer
• Due to limitation of the available size of FIFO and distribution of the same among 4 equal Tx and Rx buffers
• Tx Buffer is set to size of 128 words = 384 Bytes
• Rx buffer is set to size of 128 words = 128* (3 bytes) = 384 Bytes for all quad mode commands 1-4
• Each FIFO channel by default is 128-word size. No change of START_ADDR and END_ADDR is required
• Time between two bursts must be greater than accumulated time Tx, where Tx = Time required to transfer
data from GTM_FIFO + Time to process the data

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Quad SPI master emulation using AURIX™ GTM

Conclusion

5 Conclusion
Although AURIX™ SPI controller supports only a single SPI protocol, it is possible to emulate Quad SPI protocol
with AURIX™ GTM so that users can use external QSPI flash with AURIX™ in Quad SPI mode to achieve better
read performance. The read throughput is improved from 6.25 MB/s to 25 MB/s at 50 MHz SDR.
The AURIX™ TC375 Lite kit board and Quad SPI master emulation software source codes are available upon
request. Please contact Infineon local sales office for more details.

Application note 14 002-38230 Rev. **

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Quad SPI master emulation using AURIX™ GTMQuad SPI master
emulation using AURIX™ GTM

References

References
Flash datasheets
[1] 002-00124: S25FL128L, S25FL256L, 128 Mb (16 MB)/256 Mb (32 MB) FL-L Flash SPI Multi-I/O, 3.0 V
[2] 002-12345: S25HS256T, S25HS512T, S25HS01GT, S25HL256T, S25HL512T, S25HL01GT, 256 Mb/512 Mb/
1 Gb SEMPER™ Flash Quad SPI, 1.8 V/3.0 V

Application note 15 002-38230 Rev. **

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Quad SPI master emulation using AURIX™ GTMQuad SPI master
emulation using AURIX™ GTM

Revision history

Revision history
Document Date Description of changes
revision
** 2023-07-18 Initial release

Application note 16 002-38230 Rev. **

2023-07-18
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Edition 2023-07-18 The information contained in this application note Due to technical requirements products may contain
is given as a hint for the implementation of the dangerous substances. For information on the types
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002-38230 Rev. **