Chapter3 Lecture Notes

Diode Applications (Outline)
Ø Rectifiers
Ø Half-Wave Rectifier
Ø Bridge Full-Wave Rectifier
Ø Power-Supply Filters
Ø Diode Clampers
Ø Diode Limiters
Ø Zener Diodes
Ø Zener Regulators
Ø Power-Supply Regulators
© Dr. Ezzeldin Soliman PHYS-2211: Diode Applications 1
After completing this section, you should be able to
0 V
ac rectifiers Transformer Rectifier
Explain and analyze the operation
❏ of full-wave
Rectifiers
❏ Describe how a center-tapped full-wave rectifier works
◆ Discuss the effect of the turns ratio on the rectifier output ◆ Calculate the
peak inverse voltage

Describe how athat
bridge full-wavetherectifier worksvoltage to a pulsating DC voltage.
zH 06 V, 021
• The rectifier is❏a diode circuit converts
egatlov deifitcer evaw-flaH
◆ Determine the bridge output voltage
• It can be either a half-wave or a full-wave rectifier:
AC input
(a) Complete◆ Calculate the peak inverse voltage
power supply with transformer, rectifier, filter, and regulator
f,in60 Hz
120 V
Ø The half-wave rectifier allows foutrectified
Half-wave = fin voltage
Half-Wave
Rectifier
unidirectional currentallows
A full-wave rectifier throughunidirectional (one-way) current through the load during
the
theentire
load 360°
onlyofduring
the input cycle, whereas
one-half of 0 a half-wave rectifier allows current through the
Half-Wave
Rectifier 0
rectifier
load only during one-half of the cycle. The result of full-wave rectification is an output
the input cycle.
0 reifitceR
voltage with a frequency twice the input frequency and that pulsates every half-cycle of the
input, as shown in Figure 2–29.
(b) Half-wave rectifier 0
! FIGURE 2–19
fin fout and

Block diagram of a dc power supply with a load = 2afinrectifier.
reifitcer evaw-flaH )b(

Full-Wave
Full-wave
Rectifier
0V Vin Vout 0V
rectifier
91–2 ERUGIF
! FIGURE 2–29
Ø The full-wave rectifier allows unidirectional current through the load during the
!
Full-wave rectification.
entire input cycle.
© Dr. Ezzeldin Soliman PHYS-2211:
that make upDiode Applications 2
The number of positive alternations
.reifitcer a dna daol a htiw ylppus rewop cd a fo margaid kcolB
the full-wave rectified voltage is twice
that of the half-wave voltage for the same time interval. The average value, which is the
originally established by the EPA as L
originally established by the EPA as an
all ac source
ground and to represent
symbols a load resistor, RL, point
the same forming a half-wave
electrically. Let’srectifier.
examine Keep in mind td
what happens
a voluntary labeling program all
a voluntary labeling program
designed to indicate energy-efficient ingground symbols
one cycle of therepresent the same
input voltage usingpoint electrically.
the ideal model forLet’s
theexamine what the
diode. When happens d
sinusoi
designed to indicate energy-efficient ing
inputone cycle of
voltage the
(Vin inputpositive,
) goes voltage the
using the is
diode ideal model for theand
forward-biased diode. Whencurrent
conducts the sinusoi
throu
products. In order for power
products. In order for power
supplies to comply with the Energy Half-Wave Rectifier (1/3)
input voltage (V ) goes positive, the diode is forward-biased and conducts current
the load resistor,in as shown in part (a). The current produces an output voltage across
the
throu
supplies to comply with the Energy
Star requirements, they must have a loadload
RL, resistor,
which has as the
shown
sameinshape
part (a). Thepositive
as the currenthalf-cycle
produces ofanthe
output
inputvoltage
voltage.across
Star requirements, they must have a load RL, which has the same shape as the positive half-cycle of the input voltage.
minimum 80% efficiency rating for
minimum 80% efficiency rating for
Theoutput.
all rated•power diodeTryistoforward- 0.7 V
+ –
all rated power output. Try to
+ve Half-Cycle
+ –
biased.
choose a power supply that carries
choose a power supply that carries
as 80 PLUS logo on it. This means
• Current
as 80 PLUS canmeans
logo on it. This flow Vin +
+ I
I
+ Vout
that the power supply efficiency has Vin Vout
through
that the power the load.
supply efficiency
been tested and approved to meet
has 0 RL 0
0 t0 t1 t2 RL 0 t0 t1
• The
been tested
the Energy output tovoltage
and approved
Star guidelines.
meet
Not all t0 t1 t2 – - t0 t1
the Energy Star guidelines. Not all –
equals:
power supplies that claim to be high
power supplies that claim to be high
efficiency meet the Energy Star
V the=Energy
efficiency meet Vin −Star
0.7 V
requirements.out (a) During the positive alternation of the 60 Hz input voltage, the output voltage looks like the positive
(a) During the input
positive alternation of the 60 Hzisinput voltage, theback
output voltage looks like the positive
requirements. half of the voltage. The current path through ground to the source.
half of the input voltage. The current path is through ground back to the source.
• The diode is reverse- –

–
+
+
-ve Half-Cycle
biased. I=0A
– I=0A
• Current can’t flow Vin
Vin – Vout
Vout
0 RL 0
through the load. 0 t0 t1 t2 0V RL 0 t1 t2
t0 t1 t2 + t1 t2
• The output voltage +
equals:
Vout = 0 (b) During the negative alternation of the input voltage, the current is 0, so the output voltage is also 0.
(b) During the negative alternation of the input voltage, the current is 0, so the output voltage is also 0.

Vout Diode Applications 3
Vout
0
0 t0 t1 t2
Half-Wave Rectifier (2/3)
• The time-average value of the output
Vp ! FIG
voltage can be calculated as follows:
Avera
1 2π Area
VAVG(out) = ∫ Vout (θ) dθ rectif
2π 0 VAVG
2π 0
1 ⎡π ⎤
θ
= ⎢ ∫ Vp(out) sin(θ) dθ + ∫ 0 dθ⎥ 2π
2π ⎣ 0 π ⎦
Vp(out) π Vp(out) Vp(out)
= ⎡ ⎤
⎣−cos(θ) ⎦ 0 = − (−1− 1) ⇒ VAVG(out) 2–2
EXAMPLE half-
= What is the average value
2π 2π wave π
" FIGURE 2–22
50 V
• The peak inverse voltage (PIV) is PIV
PIV at tp
defined as the maximum reverse-bias – +
voltage applied on the diode: tp –
I=0
Vin 0
0V
PIV ≡ peak inverse voltage = Vp (in ) Vp (in) 0V RL
+
– Vp(in)
• The PIV should be less than VBR of the diode. Solution

! F I G U R E 2 – 2Diode
6 Applications 4 is 31.
Notice that VAVG
The PIV occurs at the peak of each half-cycle of the input voltage when the diod
2–26
urs at the peak of each half-cycle of the input voltage when the diode is reverse-biased. In
Half-Wave Rectifier (3/3)
the PIV occurs at the peak of each negative half-cycle.
• The required level of the pulsating DC at the output is usually much smaller than the level of the
rmer Coupling
AC at the input.
ve seen, a transformer is often used to couple the ac input voltage from the
• For as
he rectifier, thisshown
reason,
in aFigure
stepping-down transformercoupling
2–27. Transformer is usuallyprovides
used to two
couple the AC input voltage
advan-
from the source to the rectifier.
, it allows the source voltage to be stepped down as needed. Second, the ac source
ally isolated from the rectifier, thus preventing a shock hazard in the secondary
• The turns ratio (n) controls the level of the AC voltage applied on the rectifier, such that:
Vsec = n Vpri , where n ≡ turns ration = N sec N pri
F Npri : Nsec " FIGURE 2–27

Half-wave rectifier w
coupled input voltag
Vin Vpri Vsec RL

ount that the voltage is stepped down is determined by the turns ratio of the
48 ◆ D IODES AND A PPLICATIONS
Solved Problems (1/2)

EXAMPLE 2–3 Draw the output voltages of each rectifier for the indicated input voltages, as shown in
Problem (1): Draw the output2–24.
Figure voltages of each
The 1N4001 rectifierarefor
and 1N4003 the indicated
specific input voltages, as
rectifier diodes.
shown in figures below.
+5 V +100 V
Vout Vout
Vin 0 Vin 0
1N4001 1N4003
–5 V RL –100 V RL
1.0 k! 1.0 k!
(a) (b)
Vp (out ) = Vp ( in) − 0.7 V Vp (out ) = Vp ( in) − 0.7 V
! FIGURE 2–24
= 5 − 0.7 = 100 − 0.7
Solution= 4.The
3 V peak output voltage for circuit (a) is = 99.3 V
Vp(out) = Vp(in) - 0.7 V = 5 V - 0.7 V = 4.30 V
The peak output voltage for circuit (b) is
Vp(out) = Vp(in) - 0.7 V = 100 V - 0.7 V = 99.3 V

Vout Vout
The output voltage waveforms are shown in Figure 2–25. Note that the barrier po-
© Dr. Ezzeldin Soliman tential could have beenPHYS-2211: Diode(b)
neglected in circuit Applications
with very little error (0.7 percent); but,6
if it is neglected in circuit (a), a significant error results (14 percent).
D A PPLICATIONS

–4 Determine the peak value of the output voltage for Figure 2–28 if the turns ratio is 0.5.
Problem (2): Determine the peak value of the output voltage for the circuit below. What is the
8
PIV across the diode?
F 2:1
156
170VV
1N4002 +
Vin 0 RL
V
1.0 k! out
–
Vp ( pri ) = Vp ( in) = 156 V

Solution Vp(pri) = Vp(in) = 170 V
Vp ( sec ) = nVp ( pri ) = (1 2 )× 156 = 78 V
The peak secondary voltage is
Vp (out ) = Vp ( sec ) − 0.7 V = 78 − 0.7 = 77.3 V
Vp(sec) = nVp(pri) = 0.5(170 V) = 85 V
PIV = Vp ( sec ) = 78 V
The rectified peak output voltage is
Vp(out) = Vp(sec) - 0.7 V = 85 V - 0.7 V = 84.3 V
© Dr. Ezzeldin Soliman
where PHYS-2211: Diode Applications
Vp(sec) is the input to the rectifier. 7
lated Problem (a) Determine the peak value of the output voltage for Figure 2–28 if n ! 2 and
The bridge rectifier uses four diodes connected as shown in Figure 2–38. When the input
The bridge rectifier uses four diodes connected as shown in Figure 2–38. When the input
cycle is positive as in part (a), diodes D1 and D2 are forward-biased and conduct current in
cycle is positive as in part (a), diodes D1 and D2 are forward-biased and conduct current in
the direction shown. A voltage is developed across RL that looks like the positive half of
the direction shown. A voltage is developed across R that looks like the positive half of
Bridge Full-Wave Rectifier (1/2)
the input cycle. During this time, diodes D3 and D4 are Lreverse-biased.
the input cycle. During this time, diodes D3 and D4 are reverse-biased.
F ! F
F !
• D1 and D2 are forward- Ope
O
biased, while D3 and D4 I
I D3 D1
+ve Half-Cycle
D + + D1
are reverse-biased. + + 3
+ +
- -
• Current flows in the Vin
Vin Vsec A
+
load from A towards –
–
–
–
+ + RL
+
Vout 0
ground, i.e. A is +ve. D2
D2 - - D4D RL – Vout 0
4 –
• Applying KVL along
current flow loop: (a) During the positive half-cycle of the input, D1 and D2 are forward-biased and conduct current.
(a) During the positive half-cycle of the input, D1 and D2 are forward-biased and conduct current.
Vsec − 0.7 −Vout − 0.7 = 0 ⇒DD3 and
V D4 are reverse-biased.
3 and
=4 Varesecreverse-biased.
out D − 1.4 V
F
• D1 and D2 are reverse- F
biased, while D3 and D4 I
-ve Half-Cycle
are forward-biased. I D3
D3 - -
D1
D1
– –
• Current flows in the – – + + A
same direction from A Vin V sec
Vin +
to ground, i.e. A is +ve. +
+
+
+ - - R V
+
D2 + + D4 RL – Vout 0 0
L out
• Applying KVL along D 2 D4 –
current flow loop:
(b) During the negative half-cycle of the input, D3 and D4 are forward-biased and conduct current.
Vsec − 0.7 −Vout − 0.7 = 0 (b)
⇒ D1 andVDout Vsec half-cycle
During the=negative − 1.4 Vof the input, D3 and D4 are forward-biased and conduct current.
2 are reverse-biased.
D1 and D2 are reverse-biased.
When the input cycle is negative as in Figure 2–38(b), diodes D3 and D4 are forward-
When the input cycle is negative as in Figure 2–38(b), diodes D3 and D4 are forward-
biased and conduct current in the same direction through RL as during the positive half-cycle.
biased and conduct current in the same direction through R as during the positive half-cycle.
reverse voltage across D3 and D4. Visualizing D1 and D2 as shorts (ideal model), as in
Figure 2–40(a), you can see that D3 and D4 have a peak inverse voltage equal to the peak
secondary voltage. Since the output voltage is ideally equal to the secondary voltage,
Bridge Full-Wave
PIV = Vp(out)
Rectifier (2/2)
areadrops
underofa complete cycle
•IfVAVG
the(outdiode
) = the forward-biased diodes
Vp
are included
V
Vpp
as shown in Figure 2–40(b), ! F I G U
the peak inverseperiod voltage
of a complete cycle
across each reverse-biased diode in terms of Vp(out) is
VArea Area Average
same area of the half-wave rectifier AVG Area
= PIV ! VVp(out) " 0.7 V
VAVG rectified
V
half of the period of the half-wave rectifier
AVG AVG
0
The PIV= rating of the
2 ×VAVG(out) half- bridge diodes is less than
0 that required
0 for the center-tapped
2π config-
θ
2π π 2π
uration. If the diodewave drop is neglected, the bridge rectifier requires diodes with half the PIV
rating
V of those
= 2V in a center-tapped
π rectifier for the same output voltage.
AVG(out) full- p(out)
wave EXAMPLE 2–2 What is the avera
F
EXAMPLE 2–2
EXAMPLE 2–2 What is the average
What is value o
the ave
" FIGURE 2–22
50 V
• PIV ≡ peak inverse voltage " F I G U R E 2 –"2 2F I G U R E 2 – 2 2
50 V 50 V
+ 0.7 V
D3 + = 0V V
p ( sec ) − 0.7 V +
D1 + + –
– PIV = Vp ( out ) + 0.7 V Vp( pri ) Vp(sec)
– PIV 0V
0V 0V
0V D4 + +
+ – – + +
Vp(out)
Rdiodes: RL Vp(out)
D2 • To protect the L Solution
– PIV – 0.7 V – – PIV –
VBRmin = PIV Solution Solution
Notice that VA
© Dr.
rd-biased Ezzeldin
diodes D1 andSoliman
D2 are PHYS-2211:
(b) For the practical diodeDiode
modelApplications
(forward-biased diodesNotice
D1 andthat
D2 are 9 isthe
VNotice thatavV
31.8%
shown in green), PIV = V + 0.7 V. Related Problem Determine
AVG
p(out)
EXAMPLE 2–7
Solved Problem
Determine the peak output voltage for the bridge rectifier in Figure 2–41. Assuming
practical model, what PIV rating is required for the diodes? The transformer is speci
fied to have a 12 V rms secondary voltage for the standard 120 V across the primary
Problem (3): Determine the
! FIGURE 2–41
peak output voltage for the
bridge rectifier shown besides. D3 D1
Assuming the practical model,
what PIV rating is required for 120 V Vp(sec)
the diodes? The transformer is RL
+
Vp(out)
specified to have a 12 V rms D2 D4 10 k! –
secondary voltage for 120 V
rms across the primary.
Vp (sec) = 2 Vrms (sec) = Solution
2 × 12 = 16.97peak
The V output voltage (taking into account the two diode drops) is
Vp (out ) = Vp (sec) − 1.4 V = 16.97 − 1.4 = 15.57 V Vp(sec) = 1.414Vrms = 1.414(12 V) ! 17 V
Vp(out) = Vp(sec) - 1.4 V = 17 V - 1.4 V = 15.6 V
PIV = Vp (sec) − 0.7 V = Vp (out ) + 0.7 V = 16.97 − 0.7 = 15.57 + 0.7 = 16.27 V
The PIV rating for each diode is
PIV = Vp(out) + 0.7 V = 15.6 V + 0.7 V = 16.3 V
Related Problem Determine the peak output voltage for the bridge rectifier in Figure 2–41 if the trans-
former produces an rms secondary voltage of 30 V. What is the PIV rating for the diod
Open the Multisim file E02-07 in the Examples folder on the companion website.
Measure the output voltage and compare to the calculated value.
half-wave rectifier or the 120 Hz pulsating output of a full-wave rectifier must be filtered to
reduce the large voltage variations. Figure 2–42 illustrates the filtering concept showing a
nearly smooth dc output voltage from the filter. The small amount of fluctuation in the fil-
Power Supply Filters (1/4)
ter output voltage is called ripple.
• The filter is
the second Vin
stage in the 0V
Full-wave
0V
rectifier
power supply
system.
(a) Rectifier without a filter
• Its function is
to reduce the Ripple
large voltage Vin VOUT
Full-wave
variations of 0V rectifier
Filter 0
the rectifiers’
output.
(b) Rectifier with a filter (output ripple is exaggerated)
! FIGURE 2–42
• The small amount of fluctuation in the filter output voltage is called ripple.
Power supply filtering.
• The simplest power supply filter is formed by connecting a large capacitor between the rectifier
output and the ground. It is referred Filter
Capacitor-Input to as capacitor-input filter.
© Dr. Ezzeldin Soliman
A half-wave rectifier with aPHYS-2211: Diode
capacitor-input filterApplications
is shown in Figure 2–43. The filter is 11
sim-
ply a capacitor connected from the rectifier output to ground. RL represents the equivalent
+ – P OWER S UPPLY F ILTE
Vp(in)

I
+ Vp(in) – 0.7 V P OWER S+UPPLY F ILTE
+ – +
0Vp(in) Vin VC RL
t 0
I –
– 0t
• The diode is forward-biased. + + – 0 Vp(in) – 0.7 V –
+
Quarter-Cycle
Vp(in) +
0 Vin I VC RL
t0
First +ve
– Vp(in) – 0.7 V
–+ 0t +
–
• τcha = r’d C, is small. 0
t0 Vin
+
VC
0
RL
(a) Initial charging of the capacitor (diode is forward-biased) happens
– only once when power is turned on.
– 0t –
0
• The capacitor is fastly – +

(a) Initial charging of the capacitor (diode is forward-biased) happens only once when power is turned on.
charging through the diode. I
(a) Initial charging of the capacitor (diode is forward-biased) happens only once when power is turned on. +
• The diode is reverse-biased. 0
t0 t1 t2 V in
– + +
VC RL
✖ – I
0t
– + I t1 t2 –
Vin < VC
0 +
+
• τdis = RL C, is large. 0
t0 t1 t2 Vin VIC RL
– +
0t t1 t2 –
+ 0
0 V V RL
t0 t1 t2 in
• The capacitor is slowly
C
(b) The capacitor discharges through RL after peak of positive alternation
– when the diode is reverse-biased.
0t
This discharging occurs during the portion of the input voltage indicated by thet solid darkt 2blue curve. –
0 1
discharging through the load RL.
(b) The capacitor discharges through R after peak of positive alternation when the diode is reverse-biased.
• The diode is forward-biased.
L
exceeds + –
This dischargingVoccurs during the portion of the input voltage indicated by the solid dark blue curve.
in
V C
(b) The capacitor discharges through RL after peak Iof positive alternation when the diode is reverse-biased.
This discharging occurs during the+portion of the input voltage indicated by the solid dark blue curve. +
Vin > VC
• τcha = r’d C, is small. 0

t0
Vin exceeds
t1 V C t2 Vin
+ – +
VC RL
I –
Vin exceeds - + – 0t t1 t2 –
0 +
+
• The capacitor is fastly 0
t0 t1
VC
t2 Vin I VC RL
–
charging through the diode. 0 Vin
+ 0 t0
VC
t1 t2
+
–
RL
t0 t1 t2
(c) The capacitor charges back to peak of input when the diode–becomes forward-biased. This charging occurs
© Dr. Ezzeldin Soliman PHYS-2211: Diode Applications
during the portion of the input voltage indicated by the solid dark0 blue
t 0 curve. t 1 t2 –12
! FIGURE 2–43
(c) The capacitor charges back to peak of input when the diode becomes forward-biased. This charging occurs
a! half-wave
F I G U R E 2 – 4rectifier,
3 as illustrated in Figure 2–45. This ! makes
FIGUREa 2–45
full-wave rectifier easier
to filter because
Operation of the
of a half-wave shorter
rectifier with atime betweenfilter.
capacitor-input peaks. Whenindicates
The current filtered,charging
the full-wave
or rectified
The period of a full-wave rectified
voltage
discharging hasof a
thesmaller
capacitor.ripple than does a half-wave voltage for the same load resistance and
voltage is half that of a half-wave
capacitor values. The capacitor discharges less during the shorter interval between full-0
rectified voltage. The output (a)
T
Half-wave
wave
Ripplepulses,
Voltage as shown
As youinhave Figure
seen,2–46.
the capacitor quickly charges at the beginning of a
frequency of a full-wave rectifier is
• The capacitor discharge rate isL related to the timetwice
cycle and slowly discharges through R after the positive peak constant
of the inputof
that of a
the discharge
voltage (when
half-wave rectifier.
circuit (τdis), which
the diode isRreverse-biased). The variation in the capacitor voltage due to the charging and
! Fequals
I G U R E 2 L
–C.
4 5
discharging is called the ripple voltage. Generally, ripple is undesirable; thus, the smaller
•theThe largerbetter
the time constant the narrower the ripples and the more effective filtering we get.
The ripple,
period the the filtering
of a full-wave rectifiedaction, as illustrated in Figure 2–44.
• Hence, a capacitor with relatively large capacitance is always used in power supply0 filters.
voltage is half that of a half-wave 0 T
T
rectified voltage. The output (a) Half-wave (b) Full-wave
frequency of a full-wave rectifier is τ dis2
τ dis1
twice that of a half-wave rectifier.
0 ! FIGURE 2–46 0 Same
(a) Larger ripple (blue) means less effective filtering. (b) Smaller ripple means more effective filtering.
Ripple Generally, the larger the disch
Comparisonτof ripple
dis1 < τ voltages
dis2 ⇒ forR C
L 1 < R C
capacitor
L 2 ⇒ C < C
value, the1smaller
2 the ripple for the same input and load.
half-wave and full-wave
0 rectified volt-
! FIGURE 2–44 T
ages with the same (b)filter capacitor
Full-wave
Half-wave ripple voltage (blue line).
• If connected to and theload
sameand capacitor,
derived fromfull-wave
the same rectifier produces smaller ripple than half-wave
rectifier. sinusoidal input voltage. 0
• This is because the full-wave rectifier allows a (a) Half-wave
smaller
Same discharge
slope (capacitor interval.
Ripple discharge rate) Ripple
r
volt-
r
me
0 0
©
(a)Dr. Ezzeldin
Half-wave Soliman PHYS-2211: Diode Applications
(b) Full-wave 13
Ripple
• The performance of the filter is measured using the ripple factor (r). The smaller the ripple
factor, the better the filter:
r ≡ ripple factor = Vr ( pp ) VDC ,
where : Vr (pp ) ≡ peak - to - peak ripple voltage
= Vp (rect ) − VC (min ) = Vp (rect ) − Vp (rect ) e −t RLC
t =t dis ≅T
(
≅ Vp (rect ) 1 − e −T RLC
)
⎡ ⎛ T ⎞⎤ T Vp (rect )
≅ Vp (rect ) ⎢ 1 − ⎜⎜ 1 − ⎟⎟ ⎥ = Vp (rect ) ⇒ Vr ( pp ) =
T << RLC ⎣ ⎝ RLC ⎠ ⎦ RLC frect RLC
Vr (pp ) ⎛ 1 ⎞
VDC ≡ average value of output voltage = Vp (rect ) − = ⎜ 1−
⎜ ⎟⎟ Vp (rect )
2 ⎝ 2frect RLC ⎠
T
Hence, the ripple factor t chr t dis
can be expressed as Vp (rect )
follows: Vr (pp ) VDC
VC (min )
Vr ( pp ) 1
r= = VC = Vp (rect ) e −t RLC
VDC frect RLC − 0.5
www.pearsonhighered.com/floyd.
EXAMPLE 2–8 Solved Problem

Determine the ripple factor for the filtered bridge rectifier with a load as indicated in
Figure 2–48.
! FIGURE 2–48
Problem (4): F
10:1
Determine Vp(rect),
Vr(pp), VDC, and the D3 D1
ripple factor for the Output
120VVrms
115 rms
filtered bridge 60 Hz
60 Hz
Vp(pri) Vp(sec)
rectifier with a load as C + RL

D2 1000 µF 220 !
shown besides. D4 50 μF 2.2 kΩ
All diodes are 1N4001.

Vp( pri ) = 2 Vrms( pri ) = 2 ×115 = 163 V, n = N sec N pri = 1 10 = 0.1, Vp( sec ) = n Vp( pri ) = 0.1×163 = 16.3 V
Solution The transformer turns ratio is n ! 0.1. The peak primary voltage is
Vp( rect ) = Vp( sec ) − 1.4 V = 16.3 − 1.4 = 14.9 V, frect = 2fin = 2 × 60 = 120 Hz
Vp(pri) = 1.414Vrms = 1.414(120 V) = 170 V
Vp( rect ) 14.9
Vr ( pp) = = = 1.13 V voltage is
The peak secondary
frect RLC 120 × 2.2 k × 50 µ
V = nV = 0.1(170 V) = 17.0 V
Vr ( pp)1.13 p(sec) p(pri)
VDC = Vp( rect ) − = 14.9 The = 14.3 Vpeak full-wave rectified voltage is
− unfiltered
2 2
r = Vr ( pp) VDC = 1.13 14.3 = 0.079 < 0.1 Vp(rect) = Vp(sec) - 1.4 V = 17.0 V - 1.4 V = 15.6 V
The frequency of a full-wave rectified voltage is 120 Hz. The approximate peak-to-
© Dr. Ezzeldin Soliman peak ripple voltage atPHYS-2211:
the output is Diode Applications 15
1 1
If the adds
A clamper capacitor discharges
a dc level during Clampers
to an ac voltage. the periodare ofsometimes
the input knownwave, asclamping
dc restor-action
fected.
ers. Figure If 2–63
the RC timea constant
shows diode clamper isVp(in)
100that times
– 0.7 V the
inserts period,dc
a positive thelevel
clamping action
in the output is excellen
wave- ! FIG
form.
RC time
If the capacitor Thedischarges
operation
constantofof this
duringtencircuit
– can
times
the the
period
+ be period
seen by will
of the considering
inputhavewave, athe first negative
small
clamping amount half-cycle
action of is
distortion
af- Positia
of the input
ground levelvoltage.
due to When the input voltage initially goes negative, the diode is forward-
isthe charging current.
fected. If the
RC time constant
RC
biased,
shown
mately
time
Theallowing
inequal
Diode Clampers (1/2)
constant
net effect
of ten times
Figureto2–63(a).
the peak
100
the capacitor
times the
to charge to
of the– clamping
the period
Justvalue
after thewill
of
period,
near the
action
negative
the input
the clamping action is excellent. An
is
– have aP OW
peak,
Forward-
peak the
that
small
less
E R
the
the
S
of the
UPPLY
diode
diode
input (Vp(in)
capacitor
amount F of
ILTERS
is drop.
- 0.7aV),
retains
distortion
AND R EGUL
reverse-biased.
The
at
as
charge
the
ATORS ◆
app
This isvoltage
capacitor
5
R
ground level 0 due to the charging current.
because
essentially the cathode is heldin
as a battery +near Vp(in)
series with- +0.7 biased
theVinput
by thevoltage.
L
charge on Thethedccapacitor.
voltageThe capac-
of the capacitor
• The diode clamper isThe a simple
netitor
effectbiasing
can of
only the circuit
clamping
discharge that
through adds
action
the is
highDCthat level
the
resistance (positive
capacitor
of R . So, or negative)
retains
from the a charge
peak of to
one an AC
approxi-
negative
to the input
–Vp(in) voltage by superposition, I as in Figure L 2–63(b).
voltage
Vp(in)waveform. Its circuit
mately equal analysis
toIf the
half-cycle to
diodeis value
very similar
is turned to the
thearound,
input less filtered
the diode
a negative Half-Wave
dc drop. The
voltage isRectifier
+ the–next, the capacitor discharges very little. The amount that is discharged, of
the peak of capacitor
added (HWR),
voltage
to the as
inputacts
voltage to
the diode and capacitor course,
areas
essentially just
duce depends
swapped.
a battery
the on the
I in series
output value
voltage of
withasthe R .
inputin
shown
L voltage.
FigureThe 2–64.dc voltage of the capacitor adds
V – 0.7 V
to the input (a)
+
voltage by superposition,
+ as inp(in)
Figure 2–63(b). +
0
If the diode isVturned
Ø 1stt0+ve quarter cycle: in around,VCa ≈negative
Vp(in) – 0.7 dc
Vp(in)voltage
V RL the input voltage to pro-
– 0.7 V is added Vto ! FIG
– p(in) – 0.7 V +0.7 V
duce the output
– voltage as shown 0 t Figure 2–64.
in
V reaches V -0.7. –
-ve Clamper
V 0 –
– + + Positi
C p(in) Vp(in) p(in) + – 0
Vout
Ø D is RB afterwards. +
Vp(in)
0 – – P OW E R RS UPPLY F ILTERS AND R EGUL ATORS–V ◆ +5
Ø C discharges very 0
0 t
- I Vout
Forward-
V out RRLL V+0.7
L
out V
0
! F
p(in)
biased
slowly through
(a) Initial charging ofVtheRcapacitor
L
p(in)
. (diode 0is forward-biased)
+ happens
– +only once when power
+ 0 on.
is turned – 0.7 V Neg
V I
Ø Vout = Vin - Vc
Vp(in)
–Vp(in) + – p(in)
≅ Vin - Vp(in) 0 + 0.7 V (b) – I + Vout

V
RL Vout
– 0.7 V
–Vp(in) + 0.7 V
+
(a) p(in) +
+ I
Ø 10st –ve quarter cycle:
t0 Vin VC ≈ Vp(in) – 0.7 V + RL
V0 Ct reaches Vp(in)-0.7. +– Vp(in) – 0.7 V
+ve Clamper
–If the
Vincapacitor discharges
VC t 0 during the period of the input
0 –RL wave, clamping action is af-
t1 t2
fected. IfVp(in)
0 – +
Ø D is RB afterwards. the RC time constant
–
0 t is 100 times t1
the period, the clamping action is excellent. An
t2 – Vout
Ø C discharges very t 0 constant of ten times
RC time 0
-
the period will have a small amount of distortion at the
0
ground level due to the charging current.I Vout RL
slowly through R L. +
The net effect of the clamping action is that the capacitor retains
(a) Initial charging of the capacitor (diode is forward-biased) happens only once when power is turned on.
0
a charge approxi-
– 0.7 V
Ø Vout = Vin + Vc mately equal to the peak value of the input less the diode drop. The capacitor voltage acts
(b) The capacitor discharges through RL after peak
essentially asofa positive
batteryalternation
in series when
withthethediode
inputis voltage.
reverse-biased.
The dc voltage of the capacitor adds
Vin + Vp(in)
≅ discharging
This – during
occurs 0.7 Vthe portion of the input
to the input– voltage voltage indicated by the solid dark blue
+ by superposition, as in Figure 2–63(b). curve.
(b)
© Dr. Ezzeldin Soliman If the diode is turned around, a Diode
PHYS-2211: negativeApplications
dc voltage is added to the input voltage to pro-
duce the output voltage
I
as shown in Figure 2–64.
16
Vin exceeds + – +
VC +
0 If theVincapacitor discharges
V during the period of the input
RL wave, clamping action is af-
mately
RCnotime
P OW E R S UPPLY F ILTERS AND R EG Forward-
Vp(in)
o the input voltage by superposition,
ected.
ssentially
shown in Figure 2–63(a).in Just after the negative peak, theRdiode is dc
reverse-bia
uce the output voltage as shown in Figure
round level due to the charging current.
(b)
–Vp(in)
(a)
0
Neg
a egrahc a sniater roticapac eht taht si noitca gnipmalc eht fo tceffe ten ehT
2–64. ! F
F
0
essentially asdca battery series with the input voltage. The voltage
i(pV–
ssentially as a battery in series with the input voltage. The voltage of the capacitor adds
oticapac eas
Vp(in
Pos
nIf
t If
RL59 F
icapac eht fo egatlov cd ehT .egatlov tupni eht htiw seires ni yrettab a sa yllaitne
oitrotsid fo tnuoma llams a evah lliw doirep eht semit net fo tnatsnoc emit
L
the capacitor
ellecxIfe the
small a
lecxe si noitca gnipmalc eht ,doirep eht semit 001 si tnatsnoc emit CR eht fI .det
to the input voltage by superposition, as in Figure 2–6
tlov roticapac ehT .pord edoid eht ssel tupni eht fo eulav kaep eht ot lauqe ylet
pThe
acts drop.
voltage. biased
the clam
The dc v
)ni(pV–
If the diode is turned around, a negative dc voltage
is added
itca gnipmalc ,evaw tupni eht fo doirep eht gnirud segrahcsid roticapac eht fI
gatlov tupni eht ot dedda si egatlov cd evitagen a ,dnuora denrut si edoid eht fI
ofThe a
atlovequal
oitthe
!
egthe
+near V
a egrnet
+ V by the charge on the capacitor
S UPPLY
because the cathode is held - 0.7
input
o(b)the input voltage by superposition, as in Figureto(b)the input voltage by superposition,
2–63(b). p(in) as in Figure 2–63(b). )b(
RL
itrotsconstant
RL
atlodiode
ca gcapacitor
by superposition, as in Figure 2–63(b).
becomes forward-biased. This charging occurs

RL
RL
RL
itor can only+discharge through the high I resistance of R . So, from the peak of o
V 7.0 –
–Vp(in)
to pro-
is thatapproxi-
voltage.adds
is af-
V V
period, An
at athe
diode
L
If the diode is turned around, a negative dc If theisdiode
voltage added is turned
– toE the Paround,
R S Uinput I LTaE negative
P LY voltage R S to D Rdc
A Npro- voltage
L ATO R Sis added toE the
0
+
+
half-cycle to the next, the capacitor discharges very little. The amountPthat isRdiS
–
P F 59
Diode Clampers (2/2)
little.
out
P OW E R ◆
Vp(in)
OW EGU ◆ OW
V 7.0 –
of positive alternation when the diode is reverse-biased.
roticato
ahceffect
R + 0.7
is turned on.happens only once when power is turned on.
v tupnis
that is discharged,
Vp(in)
of the
thecurve.
si no
nipmalc ,discharges
excellent.
dc voltage
duce thedepends
output voltage as shown
of RLV. in Figure 2–64.
Forward-
duce the output voltage as shown in Figure 2–64.
id fo tnuof
input
will have
voltage
ATORS
course, I on the value
capacitor
Vout
htafobattery
action
biased
Vout
L
–Vp(in)
-fa sidischarges
noitca gnipduring malc ,ethe vawperiodtupniof eh+the
t foinput
doirep ehdischarges
t gclamping
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ahcsidthe isroaf-tperiod
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with thevery
If the capacitor wave, action
of distortion
If capacitor – 0.7 V
V 7.0+
a sniaof
(a)
RC
in –Figure
input voltage
blue
V 7.0 – pV
pathe
I voltage as shown in Figure 2–64.

itcatime
V 7.0+
+
period
0.7 V
a charge
nAtime
ected. If the RC .tne+lconstant
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terthe
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omten
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the period
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n
T .povalue
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I
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– 0.7 V V – 0.7 V
Vout Clamper
V
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raVhp(in)
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ap(in)
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the net of p(in) action p(in)
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LR
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1/4
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+
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inamount
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during the portion of the input voltage indicated by the solid dark blue curve.
+ Vp(in)
ILTERS
.)b(36–2 erugiF ni sa ,noitisoprepus yb egatlov tupni eh
icapac ehtaction
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rd edoofidthe
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ams athe
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the clamping
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mately equal s
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h t
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am drop.
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mately equal to the peak value of the –input less the The
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Filtered
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0 –
0
V –V out
tuoV
0 V I V V 0 R V R I V V R
indicated
p(in)
–
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1/4 level due to the charging

in out L out L out L
+
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C C P S F
Vp(in)
–
0 OW E R
- UPPLY ILTERS
-
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ssentially as asdbattery (a)
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reswith when
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tainputturned on.
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discharges
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eht fo the
–
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– 0t
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– + +
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o the input voltage by superposition, as0 in Figure .)to
b(3 62–63(b).
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itisoprepus ybas e0ginatlFigure
ov tupn2–63(b). i eht ot
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RL
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C
C
2–63(b).
tuoV
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oiretimes
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I
RVL
RVL
RVL
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-ve
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.46–2 erugiF ni nwohs sa egatlov tuptuo eht e
diode
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voltage toE the
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◆ P59
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reverse-biased.
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.46–2 e2–64.
taht siisno
lov input
0.7 V +ve
of the
curve.
Vp(in)
anext,
p eht sthe
forward-biased)
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doirperiod
asvoltage.
dc voltage
(b) the .output
46–2I ervoltage ugiF nIias nwshown ohs sain egFigure
atlov tu2–64. ptuo eht ecud
Forward-
uce the output voltage as shown in Figure 2–64.
ugin
duce
I
charging
ssel tless
the
will have
Vout
input
voltage
the
biased
tuoV
RL
capacitor
tothe
Vout = Vin+−VC ≅ VinV−p(in)(V–p(in)
0.7 V− 0.7V) ⇒ +shift down
+
tupni voltage.
Vout = VC ≅ Vp(in) − 0.7V ⇒ +ve constant
very
–
Vout
time constant
the– output
iF Figure
is effect
(a) +
in Figure
blue
+
ep eht of
2–64.
that
theRC
tuoV
the
when
the output
to as
the period
+
the
.tnerruc gnigrahc eht ot eud level dnu
ni sa ,n2–63(b).
less
If the diode
0
upnithe
t2
I
t2
V R
rugiF ni nwohs sa egatlov tuptuo eht
emperiod,
0 tInitial charging
+– VVCC ≈–Vp(in) – happens vitvoltage
after peak
This
–(a) of the capacitor V(diode is forward-biased) only once when RLL power is turned on.
oirehave
e capacitor (diode is forward-biased) t00 happens t1 only once t 2 when power is turned on.
+
+
+ in 0.7 V
discharges
dark
V 7.0 –
–
equal
whenispower
in
the input
.tnerruc gnigrahc eht ot eud level d
If the
that
of
essentially
Vp(in)
RUGIF If– the capacitor discharges – V0 during the period of the input wave, –clamping
netis
F– I G U R E) – 20.7
Vp(in 6V4
eht htiw The
to theasinput
Vp(in) V 7.0+ +0.7
Vin
Vin
Vin
! ! +0.
to peak of input
+ – 0.7 V
Vout
itcathe
agen a ,d
V 7.0)n–i()pni(pV
I
essentially
it 001 sithe
0 tt 0
+
theportion
input
in Figure
–
f the diode is turned around, a negative

100 times
t1 t2
half-cycle
RC period
backforward-biased.
–
RLdiode
solid
action
fected. IfVp(in)0the RC time constant –+ is– 100
+– + times the period, the clamping action is e
HWRVp(in)
p ehtasesmall
0
ehtdiode
gnithe
Vout
If tthe
RL
+ – V0p(in)
current.
Vlp(in)
c evitageN I Negative 0
)niclamper.
+
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rse, depends on the value of Rcourse,
1st -veground
The
ofmately
ed. If the RC time constant is fected.
–Vp(in)
t1
≈ Vp(in) – 0.7 V
oitisoprepus yb egatlov tupni

I
Vp(in)RC – 0.7timeV constant of ten times the

V period will have a –small
0.7 Vamount of disto
gnicapacitor
Vp(in) Vout
+ve Clamper
+Vp(in) – + +)Vnp(in)
Filteredduce
V0p(in)
p(in)
–
when the
+ +
–
I voltage as shownduce
p(in)
rudinput
–
he input voltage by superposition,

i(p
the
the
0 t during
–
fo euldrop.
+
1st -ve 01/4
(b)
+
(a)
curve.
)ni(pV
ntially as a battery in series with

alternationthrough
Vout
0 ground level due to the charging current.
–
-0 + +
L.
V
time constant of ten times the
V
by
-
clamping
-cycle to the next, the capacitor
Vout RLR Vout

of the capacitor
–0 +
pmalc ehtretains
isnadded
– V
during
seiredc
0
)ni(pV
V 7 .
V 0 + V – V RV VR V V R –V + 0.7 V V
t0 I capacitor V R L L Voutretains
tnaclamping
0 VIC 0tuo LThe netpeak effect
tuo of in the clamping I Vp(in)
action is that out
out the capacitor 0 0 a char
indicated
)ni(p
–
segrawave,
–
und level due to the charging

in out L out L
+
Vin exceeds
mit namount
IC
uora detonrthe
+ (a)
t2
t2
blue
(b) Initial
The discharges through R after of positive +
alternation when the diode is reverse-biased.
Vp(in)
RL
value
– charging of the capacitor (diode is forward-biased) happens only once when
– power is turned on.
becomes
L
av kaeThe
mately equal toinput

the voltage
peak–+value p(in)
V ofbythe theinput lessbluethecurve.
diode drop. The capacitor
0
discharges
0
0
positivedischarges
tsnoc emiaction
– 0 t occurs during – the 0 dark – 0.7 V
peakoccurs
0t
0t
+
This discharging the portion of indicated solid

–
s nvoltage
Vp(in) – 0.7 V
t
Initial charginghappens
V p(in)
charges
+
dark
+ 0 essentially as a battery in series + with – +the input 0 voltage. The dc voltage 0 of the ca
VC
hcsid rclamping
VC
VC
I
VC
the voltage
et fo tnaof
i yrettabofathe
V 0 V R
of the
t0 VC t1 V
+
+
+0
–
–
to thet 2 input –voltage by superposition, asC in Figure 2–63(b).
solid
Vout
t2 + in
todischarging
in L
the diode
p ehcapacitor
-ve
– –
fo tcefafecharge
V exceeds + –
capacitor
forward-biased)
capacitor
+0.7 V
If the diode is turned–around, a negative 0 tdc voltage is added to the input vo
t1
t1
0 t Vin
ut sinput
(b)
the
t t2
input
t t I 0 1 oticapac eacti f the capacitor
Vout = −VC ≅ −Vp(in) + 0.7V0⇒ −ve constant 1 2
t CR ehist exce
I Vvoltage V V V 0.7V shift up
C
+
–
–
duce the output as shown in Figure 2–64. ( )
effect
t ot lauqevol
= +V ≅ + − ⇒
by
+
i edoivoltag
out in C in p(in)
when
The of
e the output
duce the output voltage+ as shown in Figure 2–64.+
tsndistortio
the
ltage indicated
This
I
(c) The
)ni(pV
0
– 0.7 V
V RL power is turned on.
(b)peak
capacitor (diode is forward-biased) 0 happenst1 only oncet 2 when power inis turned on.+ VC
Vp(in)
(a) tInitial charging of the capacitor (diode is forward-biased) happens only once when
+
+
sa ycapac
equal
© Dr. Ezzeldin Solimant0 PHYS-2211: Diode 0Applications
of
17
t0
t0
t0
0 IfIfthe
the diode is turned– VC around,
duringathe
negative dcthe
voltage is added to the
Vp(in)
)ni(pV
V RL wave,
oc emi
capacitor discharges period of input clamping

0Vin
0Vin
0Vin
ak of input
t1 t2
he net
in
iode is(a)
ten e
portion
–
d eht
RL after
– t0 t1 t2 +0.7 V
tofected.
the inputIf thevoltage
RC time by superposition, as
thetin Figure – 2–63(b).
llait
constant
0 t is 100 times period, the clamping action is e
fI .d
t1
eely
0 2
p(in)
+ –
ht
–Vp
Vp(in)time constant of ten times the period will have a small amount of disto 0
yl
)ni
RC
)ni
+
n)
)
)
EXAMPLE 2–13 What is the output voltage that you would expect to observe across
circuit of Figure 2–65? Assume that RC is large enough to prevent s
Solution
Solved
discharge.
Problem
Ideally, a negative dc value equal to the input peak less the diode drop
! FIGURE 2–65 the clamping circuit.
Problem (5): What is the output C
voltage that you would expect to VDC ! - (Vp(in) - 0.7 V) = - (24 V - 0.7 V) = ! 23
+24 V 10 µ F
observe across RL in the clampingActually, the capacitor will discharge slightly between peaks, and, as
RL
circuit shown besides? Assume V
put voltage
in 0 V 1N914 V
will have an average value of slightly out
less than
10 that
k! calcula
that RC is large enough to prevent
output waveform goes to approximately +0.7 V, as shown in Figure 2
–24 V
significant capacitor discharge.
! FIGURE 2–66
• First +ve Quarter-Cycle: the capacitor is rapidly +0.7 V
Output waveform across RL for 0
charged through the forward-biased diode up to
Figure 2–65.
VC = Vp(in) - 0.7 V = 24 - 0.7Solution
= 23.3 V. Ideally, a negative dc value equal to the input peak less the diode dr
the clamping circuit. –23.3 V
• Rest of Cycles: the diode is reversed-biased, andVDC ! - (Vp(in) - 0.7 V) = -(24 V - 0.7 V) = !
the capacitor is discharging very slowly through
Actually, – 47.3slightly
the capacitor will discharge V between peaks, and,
RL. Its voltage is almost constant at 23.3 V.
Hence: Vout = Vin - VC = Vin - 23.3 V. put voltage will have an average value of slightly less than that calc
output waveform goes to approximately +0.7 V, as shown in Figure
Related Problem What is the output voltage that you would observe across RL in Figure
C = 22 mF and RL = 18 k Æ?
© Dr. Ezzeldin Soliman PHYS-2211: Diode Applications
! FIGURE 2–66
+0.7 V18
Output waveform across RL for 0
Open the Multisim file E02-13 in the Examples folder on the compa
❏ Describe the operation of a diode limiter
Describe the operation of a diode limiter
❏
66 ◆ D IODES AND A PPLICATIONS ◆ Discuss
◆ Discuss biased limiters ◆ Discuss voltage-divider bias
biased limiters ◆ Discuss Describean
voltage-divider bias ◆ ◆Describe an
EXAMPLE 2–13 What is the output voltage that you would expect to observe across RL in the cl
application
application
Describe
❏circuit of the
Describe
❏ the
Figure operation
2–65?
operation of aofAssume
a diode
diode clamper
that RC is large enough to prevent significant c
clamper
Diode
discharge. Limiters
Biased Limiters (1/4)
The level to which an ac voltage is limited can be adjusted by ad
P S OW E R U
bias voltage, VBIAS, in series with the diode, as shown in Figure 2–55. The voltage a
! FIGURE 2–65
DiodeADiode
must Limiters
Limiters
equal VBIAS + 0.7 V before the diode will become forward-biased and co
• The diode limiter (clipper) is a circuit Once
Figure that
Figure the
2–52(a)clipsdiode
2–52(a) shows the
begins aportion
a diode
shows to conduct,
positive
diode positive from
Climiter
limiter the
the(alsovoltageinput
called
(also called waveform
atclipper)
point
clipper) islimits
Athat
that limited
limits that
oror falls
to Vthe
clips
clips the pos-+ 0.7 V
pos-
70 ◆ D IODES AND A PPLICATIONS itive BIAS
either above or below certain reference voltage
part
allitive of of thelevel.
the
part voltage
input input voltage.
input
above It+is
voltage.As very
the
As
this input
the input
level useful voltagefor
voltage
is clipped
–is limited goes
goes
off.protection.
positive, the diode becomes
positive, the diode becomes forward- forward-
biased biasedand
+24 V conducts
and conducts current.
current.Point A
Point A is limited to +0.7
to +0.7 V Vwhen
whenthe theinput
inputvoltage
voltageexceeds
exceedsthis this
Vp(in) 10 µ F
Ø Vin =!VFIGURE
p(in) :
! F I G!UR 2–55
F IEG2U–R5E2 2 – 5 2 Vin 0 V I RR1 RL
1N914
1 R1 A A AVout V 10– k0.7 ! V
D is AFB,66 V ◆ =ofD 0.7V, AND A + p(in)
across RL in the+
Max. Limiter
positive
Examples IODES
limiter.
diode limiters PPLICATIONS
(clippers).
D
EXAMPLE 2–13
Examples of diode limiters (clippers). What is the output voltage that Iyou+ would expect to observe
Vout = 0.7V0 t Vin–24 V + FB
in + AssumeI thatVRC
I
circuit
Vp V
p of FigureV2–65? C is large enough
VBIAS +to 0.7prevent
V significant
0 +
Vin 0discharge. Vp(in) – RRLLRL Vout 00
+0.7 V
+0.7 V
0
Biased –Limiters The level to which 0 tac voltage
an is Vlimited can be adjustedP OW Eby –
V 0 0
+ 0
V :
in out
= −V – R
Ø in p(in) –Vp bias voltage, VBIAS, in series with
–
I the diode,VBIAS as shown in Figure 2–55. The voltag
A must equal VBIAS++ 0.7 V before the – diode will become RBforward-biased and
–Vp
D is RB, ID = 0 2–65
! FIGURE
C
Vout = Vin RL R1 + RL Solution ( ≅ Vin = −V
) Ideally,Onceathe
(a) Limiting
p(in) of
negative
the
diode begins
positive
dc value
alternation. The
equal tothe
to conduct,
diode is
thevoltage
forward-biased
input peak
during
at point
the
lessA the
positive
diode to
is limited
alternation
drop
(above
VBIAS
0.7
is insert
V)
+ 0.7
R1<<RL the
and clamping
(a)all inputof voltage
Limiting
reverse-biased circuit.
theduring above
positivethe +this
alternation.
negative – isisforward-biased
The level
diode
alternation. clipped off. during the positive alternation (above 0.7 V)
Vp(in) +24
and V
reverse-biased during the negative alternation.
10 µ F
(a) Initial charging of the capacitor To limit(diode a is forward-biased)
voltage to a specified happens only
R10.7negative
oncethe
level, when diode power is turned on. m
V = V : V ! - (V I - V) = -(24 V - RL V)and
0.7 = bias
!23.3 voltage
V
Ø in p(in) ! FIGURE 2–55 Vin 0 V
connected
DC
as+ in Figure 2–56. In
p(in) R
1N914
R11
this case,
A
A A the Vout
voltage
Vp(in)10 –k at!0.7point
V A must go
D is RB, ID = 0
A positive limiter. Actually, the capacitor will discharge +slightly between peaks,action and, as as shown.
a result, t
Min. Limiter
-V Vin V - 0.7 V to forward-bias +

I
theI diode and initiate limiting
0
Vp BIAS –24
Vin–an average + I of RB
Vout = Vin RL R1t0+ RL ≅ Vin = VV put
( ) p(in)
voltage
Vp will have –
–
value VCslightly less Vthan
RL BIAS +that 0.7 Vcalculated abov
R1<<RL in 0
output – +0.7 V,RLas shown V 0
Vin0 0 waveform – goes +to V approximately in Figure 2–66.
out
! FIGURE 2–56
p(in) R1 0 t RL Vout 0 0 – 0.7 V
I A + 0 – 0.7 V
V
Ø in =A−Vnegative
p(in) : limiter. –Vp +
I V BIAS +
V –Vp
! Fin IGURE 2–66 + + –
FB
D is FB, VD0= t0.7V, t Solution (b) Ideally, t
Limiting of a
thenegative
negative
V indc value
alternation. The equal
diode is to Vthe
C
forward-biased input
during peak
the
+0.7the
less
negative
V diode drop is inse
alternation (below
0 1 Output2
Vout = -0.7V 0–(b) V) waveform
0.7Limiting
and reverse-biasedacross during forpositive
RLthe –
alternation. 0 during
RL the negative alternation0
the clamping
Figure– 0.7
of the circuit.
negative alternation. The diode is
V) and reverse-biased during the positive alternation. –
2–65.
forward-biased
0t –VBIAS
t – 0.7 V t
(below
–
0V 1 2
(a) Initial charging of the capacitor (diode is forward-biased) happens only once when power is turned on BIAS
To limit Va DC !Diode
voltage - to Applications
(Vap(in) specified
- 0.7–23.3 negative
V) =V -(24
+ level,V the- 0.7 diode V) and= !23.3 19 voltage
bias V
connected as in Figure 2–56. In this case, the voltage at point A must g
Actually,
-VBIAS the - 0.7 capacitor will discharge
V to forward-bias the diodeslightlyand between
initiate limitingpeaks,action and, as asashown.
result
66 ◆ D IODES AND A PPLICATIONS bias voltage, VBIAS, in series with the diode, as shown in Figure 2–55. The voltage at point
EXAMPLE 2–13 WhatA must is the output
equal VBIASvoltage
+ 0.7 Vthat youthewould
before diode expect to observe
will become across Rand
forward-biased L in the cla
conduct.
circuit
OnceoftheFigure 2–65?toAssume
diode begins conduct, that RC is atlarge
the voltage pointenough to prevent
A is limited to VBIAS significant cap
+ 0.7 V so that
Diode Limiters (2/4)
discharge.
allBiased
input voltage
LimitersaboveThethislevel
leveltois which
clippedanoff.ac voltage is limited can be adjusted
bias voltage, VBIAS, in series with the diode, as shown in Figure 2–55. The voltage at p
by addin
P OW ER
! FIGURE 2–55 R1
70 ◆ D!IODESF I G UAND
R E 2A–PPLICATIONS
65 A must equal VBIAS + 0.7 V before theA diode will become forward-biased and cond
• If VBIAS is connected is
A positive limiter. series with the diode,
Once the diode begins to conduct, the voltage at point the
such that it tends C to reverse-bias diode,to the
A is limited VBIASRB + 0.7 V so
interval is wider than the FB interval. Hence, in inputthe
Vall
+24 V
majority
voltage above + oflevel
this the
– iswaveform
clipped off. passes. VBIAS + 0.7 V
Vp(in) 10 µ F
Ø Vin = V!p(in) : 2–55
FIGURE
0
Vin 0 V I R1 +
1N914
RL
V
0 RL
V10 – 0.7 V
Reverse-Biased
A out k!across
EXAMPLE
D is FB, 2–13
VD =limiter.
A positive
66 0.7V, What is
D IODES AND A PPLICATIONSthe output +voltage that you would expect V to observep(in) RL in the clamp
FB capac
Max. Limiter
◆
+
+ that RC is– large enough to prevent significant
BIAS
0 circuit of
–24V Figure
V 2–65? Assume
V I
Vout = VBIAS +t00.7V in
in V C VBIAS + 0.7 V
discharge. –
0 – Vp(in) 0 t RL 0
Biased Limiters The level to which+ an0 ac voltage is limited can P OW ER SU
be adjuste
V
Ø in = −V :
p(in) biasavoltage,
To limit voltage VtoBIAS
a specified I negative
, in series with the V
diode,
BIAS as shown in Figure 2–55. The v
– level, the diode and bias voltage must be
! FIGURE 2–65
D is RB, ID = 0 A mustas inequal
+2–56.
VBIAS + In
0.7this
V before the the voltage
diode will become forward-biased
Solution Ideally,connected a negative Figure
dc value Cequal to thecase,
input peak lessatthepoint
diode dropRB
A must go below
is inserted
Vout = Vin RL R1 + RL ≅ Vin =
( ) -V Once the diode begins to conduct, the voltage at point A is limited to V BIAS +
the−V BIAS - 0.7
clamping
p(in) V to forward-bias
circuit. + – the diode and initiate limiting action as shown.
V(a)
R1<<RL +24 V all input voltage above this level is clipped off.
p(in)Initial charging of the capacitor (diode is forward-biased) 10 µ F happens only once when power is turned on.
To limit
V a ! -
voltage to
(V a -
specified
0.7 = -(24
negative
V) level, -
VRthe diode
0.7 V)and= bias
!23.3 V must
voltage
Ø Vin = Vp(in) ! :FIGURE
I 1N914
! FIGURE 2–56 2–55 DC p(in) R1 L
Vin 0 V V
connected + as in Figure 2–56. In this case,
A R
AV
1 out the voltage k!– 0.7 V
at point RB go be
A must
Reverse-Biased
10
p(in) +
A negative
D is RB,0AIDpositive limiter.
= 0 limiter. Actually, the-capacitor will discharge slightly between peaks,action
and,as asshown.
a result, th
-V 0.7 V to +–
forward-bias the+diode and initiate limiting
Min. Limiter
VVvoltage BIAS
–24 average+ valueVof
V
I
t put in
will
Vin havein an C slightly less than that calculated aboveR
Vout = Vin RL 0 R1 + RL ≅ Vin output
( ) = Vp(in)waveform goes to approximately – +0.7 V, as shown in Figure 2–66.
VBIAS + 0.7 V
! FIGURE 2–56 R1<<RL 0 0 – Vp(in) R1 0I tRL RL0 0 –
– A 0
+–VBIAS – 0.7 V
Ø Vin : limiter.
A negative
= −V V
I
p(in) ++ BIAS VBIAS
! F I GVUinR E 2 – 6 6 FB
0
D is FB, VD =t00.7V, t1 t2
+
Vin VC – +0.7 V
Solution Output
Ideally, a waveformdc
0 negative across
value for to the input
RLequal – peak0 R less the diode 0 drop is inserted b
Vout = -VBIAS -0.7V Figure 2–65. –
0 t L –V –t 0.7
0 BIAS 1 V t2
the clamping circuit. VBIASonce when power is turned on.
(a) Initial charging of the capacitor (diode is forward-biased) happens only
© Dr. Ezzeldin Soliman ByPHYS-2211:
turning
To the
limit aDiode
diode around,
voltage Applications
tothea positive
–23.3limiter
specified V can belevel,
+ negative modified 20
to limitand
the diode the bias
output
vo
V DC
voltage connected! - (V p(in) - 0.7
to the portionasofintheFigure V)
input voltage= -(24 V - 0.7 V) = !23.3 V
- 0.7 V,at aspoint
2–56. waveform above the
In this case, VBIASvoltage shownAbymu
the output waveform in Figure 2–57(a). Similarly, the negative limiter can be modified
FIGURE 2–57 VBIAS
! R1 R1
66 ! ◆FIGURE 2–57
D IODES AND A PPLICATIONS A R1+ A
A
EXAMPLE 2–13 What To limitoutput
is the a voltage to a specified
voltage that you negative level, the
would expect diode andacross
to observe bias voltage mustclampi
RL in the be
connected
circuit of
Vin as in
Figure Figure
2–65? 2–56. that
Assume In this
RCcase, the enough
is large voltage to at prevent
point A significant
must go below
capacit
Vin V – 0.7 V V – 0.7 V
-V
discharge.
BIAS - 0.7 V to forward-bias the diode
BIAS and initiate limiting
BIAS action as shown.
VBIAS – 0.7 V
By turning Biased
0 Limiters
RL The level to which an ac voltageRL is0 limited0 can be adjusted by add P OW EtR1 S U P
0t0+ tthe 1
diodet2 around, the positive limiter + canRbe L modified to limit 0tt00 thet1 output
t t1 voltage at p
! FIGURE 2–56 voltagebias to the voltage,
t 0 portiont
V1 BIAS VBIAS t
of the 2 , ininput
series with the
voltage
R1
diode,VBIAS
waveform + as shown
above VBIAS in Figure
- 0.7 V,2–55. 0
as shownThe by
V
A must –
the output waveform inBIAS equal V + 0.7 V before
Figure 2–57(a). Similarly, the the
A diode
– will
BIAS
become
– negative limiter
forward-biased
can be modifiedand con
• If VBIAS! isFAI Gconnected – 6 5 is series with
U R E 2limiter.
negative the diode, such that it tends
C portion to forward-bias the diode, the FB + 0.7 V so
to limit VOnce the the diode
output begins
voltage to
to conduct,
the the voltage
of the at point
input A
voltageis limited
waveform to V below
BIAS
interval
70 ◆ isDwider than the RB interval. Hence, the majority of– the waveform part is (b).clipped.
in
IODES AND A PPLICATIONS -VBIAS(a)all +input 0.7 V, voltage
as shown above by+the
thisoutput
level is clipped
waveform off.
in
Vp(in) +24
0 (a)V 10 µ F RL 0
V
Ø! FIGURE
in = V p(in)
! FIGURE 2–55
: I R R R1 – –V RL
BIAS – 0.7 V
2–57 R1
Forward-Biased
Vin A 0V V10 k!– 0.7 V

1 1N914 1 V V
A out
DA66is FB,
positive V
limiter.= 0.7V, + R1 A
+
A BIAS
A p(in) +
Max. Limiter
◆
66 D
D IODES AND A PPLICATIONS
D IODES AND A PPLICATIONS +
Vin + that you expect to observe across RL inFB
◆
EXAMPLE
Vout = -V 0 2–13+ 0.7V What –24Vis in the output voltage
V would the clampi RL
t0
BIAS Vin Vin
V I V C V BIAS + 0.7 V
circuit of Figure 2–65? Assume that RC–is large enough
in V BIAS – to prevent
0.7 V
t1t1 significant
t2 tcapacit
0 0
0
discharge.
t0 Biased
– R L V p(in)
R 0
L t R L R
R L 0 0 t 0 0 t 1 t 2
2
–
0t0t– t 1Limiters
t t2 t The level to which an –ac voltage
0 is limited t
0 can1 be adjusted by add
0
V
Ø in = −V p(in) : By 0 V Biased
1 tturning t 1 Limiters
2the diode
2 around, The the
–VBIAS level +
to
positive +limiter
which
VBIAS+
–
VBIAS V
an
0.7
L
canac voltage
be modified
V+ 0.7 V
–VBIAS
+
is
0.7
limited
V
to can
limit PtheOWbeoutput
E R S
adjusted
UP
bias+
voltage voltage,
to bias
BIASVBIAS,ofin
the portion
voltage, Vthe
+
series
input Iseries
, inwithvoltagethewithdiode,
– waveform
–+the
as shown
Vdiode,
BIAS
BIAS above
–V
asin Figure
VBIAS
shown
BIAS 2–55.
-in0.7
Figure The
V, as voltage
shown
2–55. at
by vol
The
D is RB, I
! F I G U R E 2 –D6 5
= 0 must Aequal
theA output mustVdc
waveform equal
BIAS in +
BIAS
V0.7
Figure V2–57(a).
+before
0.7 the
V Similarly,
before
+
diode will
thethe become
negative
diode forward-biased
limiter
willdiodebecome be RB
canforward-biased and cona
modified
Solution Ideally, a negative value BIAS
equal to the input peak less the drop is inserted
Vout = Vin RL R1 + RL ≅ Vinto=Once ( ) limit
−Vp(in) the
the diode
output begins to
voltage conduct,
C the the
to voltage
portion at
thepoint
of voltage input is
A point limited
voltage to VBIASto+below
waveform 0.7 Vbyso
the clamping Oncecircuit.the diode begins to conduct, the at A is limited V BIAS +
R1<<R(a) (b)
-V all input +all voltage
0.7 above
V, asvoltage
shown + this
by – output
level
the is level
clipped
waveform off. in part
Vp(in)
(a)
L
Initial charging of the capacitor
(b)BIAS
+24 V
input
(diode is forward-biased) above this happens is clipped
only off.(b).
once when power is turned on.
To limit a voltage to a µF
10specified negative level, the diode
Ø V!in! FIGURE
= Vp(in) 2–55: V DC ! - (V p(in)
I R1- 0.7 V) = -(24 V - 0.7 V) = and !23.3 biasVvoltage mu
Forward-Biased
R1 A this Rcase, the voltage R

FIGURE 2–57
! FIGURE 2–55 Vin connected
0V as in Figure 2–56. 1N914R1 In
A 1AVout V10 L
– 0.7 at Vpoint A must go b
DAispositive
RB,A limiter.
ID = 0 limiter. + A p(in)k!
the+ou
Min. Limiter
Actually,
-VBIAS the -capacitor0.7 V to+will discharge
forward-bias theslightly
diode and betweeninitiatepeaks,limiting and,actionas aasresult,
shown.
positive Vin VVin +average
– BIAS + + RB
Vout = Vin0 RtL0 R1 + RL ≅ V ( put )–24 V
voltage willVin haveVan value of slightly less than that calculated above. Th RL
I
in = V inp(in) in V V C –V BIAS V + + 0.7
0.7 V
BIAS t1 V t2 + 0.7 V V
R V – 0.7 V
L R1 – +0.7
t2 1 <<R L output
0 waveform goes–to approximately – RL V, as shown BIAS 0 in Figure 2–66.
BIAS
! FIGURE 2–56 t0 00 t1
t0 t01
– t2
t2
Vp(in) R I
+
0A t 0 –V L + 0.7RVL 0 0 t 0 t
R L R 0
t1 –
Ø VAinnegative : V BIAS 0 1
= −Vp(in)limiter. I
+
BIAS
VBIAS V
+ +
Vin + BIAS V
D is FB,0 VtD0 = 0.7V, t1 Vin +
! FIGURE 2–66 – BIAS
t2 A
VC – +0.7 V FB RL
Vout = VBIAS -0.7VSolution R(b)Ideally, Output
1 a negative
0 waveform dc value
across RL for equal to the–input 00 peak
–t 0
RLless the diode 0 drop is inserted by
t 1 – 0.7 V t 2
–VBIAS –
the
Figureclamping
(a) 2–65. circuit.
VBIAS
© Dr. Ezzeldin Soliman (a) Initial charging of the capacitorPHYS-2211: (diode is forward-biased) Diode Applications happens +only once when power is turned 21 on.
To limitToa !
VDC voltage
limit to a specified
- a(Vvoltage
p(in) - to
0.7
R1 a V) negative
= V-(24
–23.3
specified level,
V - the
negative 0.7 diode
= and
V) the
level, biasand
!23.3
diode Vvoltage
bias mu
volt
connected as in Figure
connected as in 2–56. In
Figure thisA In
2–56. case,
thisthe voltage
case, at pointat Apoint
the voltage mustAgomub
Actually, the capacitor will discharge slightly between peaks, and, as a result, the ou
–
• A voltage divider can be used to provide the required bias voltage (VBIAS) as a portion of a
bigger supply voltage (VSUPPLY), according to the well-known voltage-divider formula:
VBIAS = ⎡⎣R3 (R 2 + R3 )⎤⎦ VSUPPLY
• The resistors of the divider (R2 and R3) should be very small compared to R1 in order to have a
stiff voltage divider, and to minimize the AC voltage drop on (R2 || R3) which may affect VBIAS.
68 ◆ D IODES AND A PPLICATIONS
• The three commonly used voltage-dividers are shown below:

R1 R1 R1
+VSUPPLY –VSUPPLY +VSUPPLY
Vin R2 Vout Vin R2 Vout Vin R2 Vout
R3 R3
Reverse-Biased
(a) Positive limiter Max. Limiter Forward-Biased
(b) Negative limiter Max. Limiter Adjustable RB
(c) Variable positive Max. Limiter
limiter
© Dr. Ezzeldin Soliman ! FIGURE 2–60 PHYS-2211: Diode Applications 22

Diode limiters implemented with voltage-divider bias.
EXAMPLE 2–10
What would you expect to see displayed on an oscilloscope connected across RL in th
!limiter
F I G Ushown
R E 2 –in
5 3Figure 2–53?
Problem (6): WhatSolution

would you The diode is forward-biased and conducts R1 when the input voltage goes
expect to see displayed on So, for the negative limiter, determine10the

k!
peak output voltage across R
an oscilloscope connected ing equation:+10 V
across RL in the limiter Vin 0 V RL 1N914 V out
RL
100 kÆ 100 k!
circuit besides? Vp(out) = a b Vp(in) = a b 10 V = 9.09 V
–10 V R1 + RL 110 kÆ
The scope will display an output waveform as shown in Figure 2–54.
• Vin = 10V: ! FIGURE 2–53 +9.09 V
D is RB ⇒ I D = 0,
Solution The diode is forward-biased and conducts when the input voltage goes below - 0.7 V
⎛ RL ⎞ ⎛ 100So, k for⎞the negative limiter, determine the peak output voltage across RL by the follow
Vout = ⎜ V =
⎟ in ⎜ ⎟ ×10
⎝ R1 + R L ⎠ ing equation:
⎝10 k + 100 k ⎠ Vout 0
–0.7 V
= 9.09 V RL 100 kÆ
Vp(out) = a b Vp(in) = a b 10 V = 9.09 V
R1 + RL 110 kÆ
• Vin = −10V: ! FIGURE 2–54
The scope will display an output waveform as shown in Figure 2–54.
D is FB ⇒ VD = 0.7V, Output voltage waveform for Figure 2–53.
Vout = −0.7V
Related Problem
+9.09 V
Describe the output waveform for Figure 2–53 if R1 is changed to 1 kÆ
Open the MultisimVout
file 0E02-10 in the Examples folder on the compan
–0.7 V
+10 V 1.0 k!
D1 D2
EXAMPLE 2–11
Vin 0 Figure 2–58 shows a circuit combining
+ a–positiveVout
limiter with a negativ
–10 V
Solved Problems (2/3) 5V
Determine the output voltage waveform. 5V
– +
! FIGURE 2–58
Problem (7): The circuit Diodes areR1N914.
1
A
besides combines a biased
1.0 k!
positive limiter with a biased +10 V
D1 D2
negative limiter. When
Solution Determine
the voltage Vatin point
0 A reaches +5.7 V, diode D1+ conducts – and Vlimits
out the
the output voltageform
waveform.
to +5.7 V. Diode D2 does not conduct until the voltage 5V 5V
reaches - 5.7 V. Th
–10 V – +
positive voltages above +5.7 V and negative voltages below - 5.7 V are clipped
resulting output voltage waveform is shown in Figure
Diodes2–59.
are 1N914.
• Vin = 10V: ! FIGURE 2–59

Solution When the voltage at point A reaches +5.7 V, diode D1 conducts and lim
D1 is FB ⇒ VD1 =Output
0.7V, D 2 is RB
voltage I D2 =to0for
⇒form
waveform +5.7
Figure
V. Diode D2 does not conduct until the voltage reaches - 5
+5.7 V
Vout = 5 + 0.7 = 5.7V
2–58. positive voltages above +5.7 V and negative voltages below - 5.7 V are
resulting output voltage waveform
Vout 0 is shown in Figure 2–59.
• Vin = −10V: ! FIGURE 2–59 –5.7 V
D1 is RB ⇒ I D1 = 0, D2 is FB ⇒ VD2Output
= 0.7Vvoltage waveform for Figure +5.7 V
2–58.
Vout = −5 − 0.7 = −5.7V Vout 0
Related Problem
© Dr. Ezzeldin Determine the output voltage
Soliman waveform
PHYS-2211: in Figure 2–58
Diode Applications –5.7 V if both dc sources
24 are
the input voltage has a peak value of 20 V.
–18 V
R3
220 !
EXAMPLE 2–12 SolvedDescribe
Problems (3/3)
the output voltage waveform for the diode limiter in F
" FIGURE 2–61

Problem (8): Describe
Solution the is a positive limiter. Use the voltage-divider
The circuit R1
formula to deter
output voltage waveform for
voltage. 10 k!
the diode limiter shown Vout
+12 V
besides. R3 220 Æ 1N914
+18 V
VBIAS = a b VSUPPLY = a R2 b 12 V = 8
R2 +
Vin R03 100 Æ + 220 Æ
100 !
The output voltage waveform

–18 V is shown in Figure 2–62. The positive part
R3
voltage waveform is limited to VBIAS + 0.7 V. 220 !
⎛ R3 ⎞" F I G U R⎛E 2220 – 6 2 ⎞

• VBIAS = ⎜ ⎟ VSUPPLY = ⎜ 8.25circuit
⎟ ×12 =The
Solution V is a positive +8.95
limiter.VUse the voltage-divider formula
R
⎝ 2 + R 3 ⎠ ⎝ 100 + 220 ⎠ V 0
voltage. out
• Vin = 18V:
R3 220 Æ
D is FB ⇒ VD = 0.7V, Vout = 8.25 + 0.7 = 8.95V. VBIAS = a b V = a b1
R2 + –18
R3 VSUPPLY 100 Æ + 220 Æ
• Vin = −18V:
The output voltage waveform is shown in Figure 2–62. The pos
D is RB ⇒ I D = 0, Vout = Vin = −18V. voltage waveform is limited to VBIAS + 0.7 V.
Related Problem How would you change the voltage divider in Figure 2–61 to limit the ou
to +6.7 V? " FIGURE 2–62
+8.95 V
V 0
Zener Diodes (1/2)
• The zener diode is a heavily dopped silicon pn junction that is designed for operation in the
reverse-breakdown region.
Attribute Regular Diode Zener Diode

Dopping Density (N)
N ≡ number of impurities Light Heavy
per unit volume
Electric field
Same Value
at Breakdown (EBR)
Width of the Depletion
Region at Breakdown:
4ε Wide Narrow
WBR = EBR
eN
Reverse Voltage at Breakdown: High Low
VBR = WBR EBR (VBR ≅ 50 V) (VBR = VZ ≅ 5 V)
Power at Breakdown: High (exceeds rating Low (doesn't exceed
PBR = VBR IBR and damages the diode) rating, diode is safe)
–1.
Zener
!
Diodes
FIGURE 2–1 (2/2) !
! FIGURE 2
age should be.

breakdown voltage across it. Most schematics will indicate on th
erating normally, it will be in reverse breakdown and you sho
results and is much easier to use than more complicated models.
Cathode Anode Cathode
n The diode.
For most circuit analysis and troubleshooting work, the ideal

p The diode.
Regular Diode Zener Diode
Anode (A) Cathode (K) Anode (A) Cathode (K)
(a) Practical model

Depletion region
(a)(b) Symbol
Basic structure (b) Symbol
GREENTECH NOTE GREEN
The diodes covered in thisofchapter The diodes c
+
–
Diodeconfigurations
ysical Packages Several of through-hole
common physical configurations through-hole
ZZ
dhediodes
anode (A) and cathode (K) are indi- areanode
based on the junction just
pn cathode are based on
are illustrated in Figure 2–2(a). The (A) and (K) are indi-
VZ
+
–
Breakdown like the Breakdown
a diode
ype in several
of package. Theways, depending
cathode on the type
is usually of solar cell, also
package. Theknown
cathodeas is usually like the sola
those
by packages
a band, a tab,where oneother
or some is con- On the
leadfeature. photovoltaic
those packagescell or PVone
where cell,lead is con- the photovo
that was introduced in Chapter 1. that was intr
(b) Characteristic curve. The slop
o the case,
PD = the
VRIR case
× is the cathode.
VR
A solar cell is basically a diode A solar cell i
-Mount
Mount = P
Diode
shows typical Packages
diode
D(max) packages for sur-
Figure 2–2(b) shows typical diode packages for sur- region
operating with a different geometric operating with a differ
unting
OD and onSOT a printed
packages circuit
haveboard. The SOD and SOT packages have gull-wing
gull-wing
regions construction than rectifier and construction
eads.that
ads The SMA
bend underpackage has L-shaped
the package. The leadssignalthat bendTheunder
diodes. p andthe package. The
n regions signal diode
d SMAthe types have aTheband on one
typeend
is a to indicate thecell
cathode. The SOT type is a
!VZ
ndicate cathode. SOT in the solar ×Pmuch
are = P thinner in the solar c
D D(max)
eminal
or twopackage
diodes.inInwhich there are either
a single-diode SOT onetoPHYS-2211:
or twolight
diodes. Intoa activate
single-diode SOT to allow
© Dr. Ezzeldin Soliman allow energy
Diode Applications 27 ligh
,cathode.
pin 1 is usually the anode
In a dual-diode andpackage,
SOT pin 3 is the the
cathode. In a dual-diode
photovoltaic effect, and SOT
a solarpackage, the photovo
he common terminal and can be either the anode or the cathode. Always check the
ductivity,
the reverse voltage (VR) is increased, the reverse current (IR) remains extremely small up to
eometric
the “knee” of the curve. The reverse current is also called the zener current, IZ. At this
point, the breakdown effect begins; the internal zener resistance, also called zener imped-
Zener Breakdown Characteristics (1/2)
ance (ZZ), begins to decrease as the reverse current increases rapidly. From the bottom of
the knee, the zener breakdown voltage (VZ) remains essentially constant although it in-
• A zener diode operating
creases slightlyalong
as thethe breakdown
zener current, line acts as a voltage regulator as it maintains a
IZ, increases.
nearly constant voltage across its terminals over a relatively wide range of the reverse-current
! FIGURE 3–3
(IZK < IZ < IZM), where:
Reverse characteristic of a zener VZTVZ @ IZ
* IZK ≡ zener minimum (knee) current, VR
diode. VZ is usually specified at a
* IZM ≡ zener maximum
value current.
of the zener current known as Minimum IZK (zener knee current)
the test current. (Knee) Point
Test IIZT
• In addition to IZK and IZM, a zener Z (zener test current)
Point
diode is characterized by a test point
along the breakdown line. The
Maximum IZM (zener maximum current)
coordinates of this point are:
Point
* IZT ≡ zener test current,
Power Rating
* VZT ≡ zener test voltage = VZ I IR
Z = I ZT Exceeded
Zener Regulation The ability to keep the reverse voltage across its terminals essentially
constant is the key feature of the zener diode. A zener diode operating in breakdown acts
to avoid operating a zener diode near the knee of the curve because the impedance changes
dramatically in that area.
Zener Breakdown Characteristics (2/2)
!VZ !
• To complete the characterization of a VZ0
VR 0 Pr
zener diode, the slope of the offset
cir
breakdown line of the characteristic IZK
ill
curve is represented by a dynamic
+
impedance ZZ, such that:
Z Z ≡ zener dynamic impedanceZ
Z
ΔV
= slope −1 of the breakdown line =VZ Z
+ ΔI Z
– Test ZZ =
!VZ
!IZ
Point !IZ
• Using the previously defined dynamic–
impedance, the intersection between the
extension of the breakdown line and the
voltage axis, VZ0, can be obtained:
ΔV V −V IZM
Z Z = Z = ZT Z0
ΔI Z I ZT − 0
IR
VZ0 = VZT − Z Z I ZT
(a) Practical model (b) Characteristic curve. The slope is exaggerated for illustration.
Normally,
Normally, ZZ is specified at the zener test current. In most cases, Z is specified
you canZassume that ZZatisthe zener t
a small constant over the full range of zener current values anda is
small constant
purely overItthe
resistive. full range of z
is best
to avoid
to avoid operating a zener diode near the knee of the curve because theoperating
impedance a zener
changes diode near th
Zener Equivalent Circuit

dramatically in that area. dramatically in that area.
T HE Z ENER D
• Based on the required accuracy, the zener diode can be represented
!VZ
using either one of the ! FIGU
T HE Z ENER D IODE ◆
following models: 0 Practica
VR FIGURE 3–4
!
Ideal Model Practical Model circuit a
IZK diode eq
Ideal
! FIGURE 3–4
zener illustrat
VZ
VZT VZ VVZ0R 0
model and +the chara
VZ + VZ Ideal zener diode equivalent cir
VZ 0
IZ IZ ZZ
VR
ΔVZ I model andIthe characteristic
Z ZZ Z
cu
+
VV ΔI Z VZ
+ +– Z Z +
Test VZ0
–V–ZT
VZ !V
ZZ = Z !I–
Point General !IZ Z
– IZ –
Point
IZ IZ IR
IR
(a)Ideal
(a) Idealmodel
model (b) Ideal
(b) Ideal characteristic
characteristic curve curve I
VZ = VZT ≠ f (I Z ) VZ = VZ0 + ΔVZ = VZ0 + Z Z ΔI Z = VZ0 + Z Z I Z = fZM(I Z )
I Z 0 =0
ΔI Z =I Z IR
(a) Practical model (
Figure
Ø TheFigure
breakdown3–5(a)represents
3–5(a) represents
line the practical
the Practicalmodel
practical
(a)
is approximated by (second
model
model
Øapproximation)
an(second slope ofof the
Theapproximation) a zener diode, diode,
ofbreakdown
a zener
(b) Characteristic curve. The slope is exaggerated for illustration.
line is taken
where
thethe zenerimpedance
where
ideal zener
vertical lineimpedance (resistance), ZZZ, is, is
passing (resistance),
through VZT. Z included. Since
included.
care
the actual
Since
of viathethevoltage
actual
small
curve iscurve is
voltage
dynamic impedance ZZ.
not ideally vertical, a change in zener current (¢IZ) produces a small change in volt-
not ideally vertical, a change in zener current (¢I Z ) produces a small change in zener zener
For
volt-
© Dr. age (¢VZ),Soliman
as illustrated inmost
Figure 3–5(b). ByPHYS-2211:
Ohm’s law, the ¢VZthe
ratio Applications
of to ideal the willcircuit
¢IZ ismodelmost analysis and troubl
ageEzzeldin
(¢VZ), as illustratedFor in Figure circuit analysis
3–5(b). ByandOhm’s Diode
troubleshooting
law, work,
the ratio of ¢V to ¢I is thegive very good30
Zresults Zand is much easier to use than m
impedance, as expressed in and
results the following
is much easierequation:
to use than more complicated models. When a zener diode is op-
impedance, as expressed in the following equation: erating normally, it will be in reverse
erating normally, it will be in reverse breakdown and you should observe the nominal
Problem (9): A zener diode has ZZ of 20 Ω. The data sheet gives VZ = 6.8 V at IZ = 37 mA,
and IZK = 1 mA. What is the voltage across the zener terminals when the current is 50 mA?
When the current is 25 mA? Use both ideal and practical models of the zener diode.
• VZ0 = VZT − I ZT Z Z = 6.8 − 37 m × 20 = 6.06 V
• When I Z = 50 mA :
∗ Ideal model : VZ = VZT = 6.8 V
∗ Practical model : VZ = VZ0 + I Z Z Z = 6.06 + 50 m × 20 = 7.06 V
• When I Z = 25 mA :
∗ Ideal model : VZ = VZT = 6.8 V
∗ Practical model : VZ = VZ0 + I Z Z Z = 6.06 + 25 m × 20 = 6.56 V

Three-terminal voltage regulators.
Zener Limiter Solved Problems (2/2)

In addition to voltage regulation applications, zener diodes can be used in ac applications
to limit voltage swings to desired levels. Figure 3–18 shows three basic ways the limiting
Problem (10): Usingaction
the ideal model
of a zener diodeof canzener diode,
be used. Part (a)sketch
shows athe
zenerexpected output
used to limit voltage
the positive peak
waveform for each ofof the
a signal
zenervoltage to the
diode selectedcircuits
limiting zener voltage.
drawnDuring
below.the Try
negative alternation,
to obtain the the
samezener
acts as a forward-biased diode and limits the negative voltage to - 0.7 V. When the zener
output waveforms but using regular diodes.
R R
+ VZ
VZT +
I I 0.7 V
Vin Vp(in) RB FB 0 Vin Vp(in) FB RB 0
+ I – 0.7 V + I –VZ
-VZT
(a) (b)
+ +VVZ1ZT2
++0.7V
0.7 V
I FB D1 RB
Vin Vp(in) 0
I RB
D2
+ FB
-VZT1–V
-0.7V
Z1 – 0.7 V
(c)
! FIGURE 3–18
VR = IZMR = (100 mA)(220 Æ) = 22 V VR = IZMR = (100 mA)(220 Æ) = 22 V
hemaximum
maximum
XAMPLE 3–5 current values (IZK
zener Maximum
impedance zener andimpedance
atDetermine
the IZM) with
specified which
testminimum
the ZZ is the themaximum
zener cancurrent
maximum operate.
zener
and the maximum values
Resistor
impedance
input (IZK and
atRtheis specified
voltages the
IZMP ) with
that testwhich
can
D(max) 1Wthe zener can
be regulated by th
A,series
ZZ iscurrent-limiting
10 Æ at 76current,
mA. The resistor.
For The
IZ. maximum meters
Therefore,
example,zener indicate
forim-
a 1N4728A, theseries
relative
ZZ is current-limiting
10values
Æ at 76 andmA. trends. IZMThe
resistor.
The maximum = meters
zener im- = the relative
indicate = 100va m
zener diode in Figure 3–11. V Z 10 V
Tocurve
eristic illustrate regulation,
is specified
pedance,
at IZK , let’s
ZZK which use
, at the thecurrent
isknee
the ideal
of themodel of theTo1N4740A
characteristic illustrate
curve zener
regulation,
is specified diode
at IZK, let’s
(ignoring
which use thecurrent
is the ideal model of the 1N474
ZZK V
theis zener =
Æ resistance)
400IN(max) at 1 mA 22
at theV
for in +
knee Regulation with a Varying Input Voltage
10
a 1N4728A. V
theofcircuit
! = 32
theFIGURE
curve.V For
of Figure example,
3–11 3–10.ZThe V
theisabsolute
ZK 400 IN(max)
zener =
Æ resistance)
at lowest 22
1 mA for V + 10
a 1N4728A.
current
in V
the that =
circuit
R
32 V
willof Figure 3–10. The absolut
maintain
urrent
zener diode regulation
is specified
can ideally a is
Leakage
for specified
reverse
regulate current
voltageatThis
an input ZK , which
IReverse
that is less
voltage
shows forthis
leakage
from
that the 1N4740A
maintain
current
10.055zener is 32 regulation
Vis 0.25
to specified
Vdiode can formA
ideally a is and
specified
reverse
regulaterepresents
at Ithat
voltage
R input
an , which
is less
voltage
ZK for10.055
from the 1N4740A ! Fi
V to 32 V
at the
the no-load
zener is not in
than
current. reverse
the knee
breakdown
voltage. for
Thisthese
means that the zener is not in reverse breakdown for these
proximate • The10 V output.The
zener Themaximum
voltage,outputi.e. willcurrent
and Vvary isisnot
OUT, slightly
maintain given
analmost theonno-load
approximate
because the
of thedatasheet
10 current.
V output. but
The can
The maximum
be calcu-
output
100 ! willcurrent is not given
vary slightly +
because
+
on the
of thd
for a reverse
mAlated voltage
measurements.
ofspecification
1 V in a For 1N4728A.
example W,IRwhichis 100ismA for aon reverse voltage
powerofin inR
1 V 220 a!1N4728A.
hich hasfrom the
constant
been power
as long
neglected in these of 1impedance,
as calculations.
thezener
reverse-bias current given
whichlatedhasfrom thethe
been datasheet.
neglected
+
specification
Keep
these in mind of 1 W, which is given on the
calculations.
that both the minimum and maximum values are at the thatoperating
both the + extremes
minimumand andrepresent
maximum values are at the operatin
flowing through the zener diode is ranging V
VIN operation.
IN 1N4733A
1N4740A V
10OUT
V
worst-case operation. worst-case
from Iin
om the datasheet up to
ZKFigure IZM. a 1N4736A
EXAMPLE
3–7, 3–4 zener diode From has a Z the
Z of 3.5 Æ.–The
datasheet – Figure 3–7, a 1N4736A zener diode has a ZZ of 3.5 Æ
in
asheet
mum gives
EXAMPLE
and The
• the Z corresponding
=3–5
Vmaximum6.8 Vinput
at a test range
current,
voltages P of
Determine
that variation
IZ,can
of 37
D(max) be
themA. in
1minimum
W
regulated VINis
datasheet
What the
byandgives
thevoltageZ =across
theVmaximum 6.8 Vinput
at a test current,
voltages P IZ,can
that of 37
D(max) bemA.
1 WWhat is
regulated bythe
thevolt
I = = = 100 mA I = = = is 25mA
100
ezener
3–11.terminals
can be when the current
obtained asZM is 50zener
follows:mA? Whenin
VZdiode the current
the zener
Figure
10 V is 25
3–11. terminals
mA? Figure when3–8 the currentZM is 50 mA? VZWhen the 10current
V –
– mA?
resents the zener diode. represents the zener diode.
! FIGURE 3–11
K-Point
Solution R (IZ =the
RFrom IZKdatasheet
) in Figure
! F3–7
I G Ufor
RE 3the M-Point
RRV(I
– 1 01N4733A: IZMV) at IZ = 49 mA,
Z Z==5.1 ! FIGU
IZK = 1 mA, and ZZ += 7 Æ at IZ. For simplicity, assume this value of ZZ+over the
100!! + + 100!! + +
Rrange of current values. The equivalent circuit is220
220 R
shown in Figure 3–12.
+ + IZ
!IZZ
Z
I ZKZ
!V
+ + IZ
!IZZ
Z
I ZMZ
!V
– –
VINVIN
FIGURE 3–12 1N4733A
1N4740A V
10OUT
V VINVIN 1N4733A
1N4740A V
10OUT
V
R
– –in Figure
uivalent of circuit + –– 5.1 V ±V"V
+
VZ VZ0 –
VZ Z Z VZ0 –
VZ
11. 100 !
–
– 7! –
–
VOUT (min) = VZ 0 ++ I ZK Z Z , VOUT (max) = VZ 0 + I ZM Z Z ,
SolutionVVZ IN=From
n Figure 3–7 for the 1N4733A: 5.1 V IZ = 49 in
theatdatasheet mA,Figure 3–7 for+the 1N4733A: VZ = 5.1 V at IZ = 49 mA,
VIN(min) =assume
Z = 7 Æ at IZ. For simplicity,
VOUT (min) I ZK
1R
+=value
–this mA,
of and ZZ =the7 Æ at IZ. For
ZZ over VIN(max) =assume
VOUT (max) I ZMRof ZZ over the
this+value
IZK – simplicity,
ues. The equivalent circuit
Lineis regulation
shown in range
Figure
≡ of
ΔVcurrent
3–12. ΔV
values.
= $VThe equivalent
−V circuit& is
$Vshown −V
in Figure&3–12.
OUT IN % OUT(max) OUT(min)' % IN(max) IN(min)'
I G U R!E FIGURE
3–8 3–12 ! FIGURE 3–8
R © Dr. Ezzeldin Soliman PHYS-2211:
R Diode Applications 33
Equivalent of circuit in5.1Figure
V ± "VZ 5.1 V ± "VZ
0 ! 3–11. At IZK = 1 mA, the 100
output
! voltage is
MPLE 3–5
Solved Problem
Determine the minimum and the maximum input voltages that can be regulated by the
zener diode in Figure 3–11.
! FIGURE 3–11
Problem (11): Determine the minimum and R
maximum input voltages that can be regulated +
100 !
by the zener diode of the circuit besides,
+
knowing that VZ = 5.1 V at IZ = 49 mA, VIN 1N4733A VOUT
IZK = 1 mA, IZM = 196 mA, and ZZ = 7 Ω. –
Calculate the percentage line regulation.
–
• VZ0 = VZT − I ZT Z Z = 5.1 − 49 m × 7 = 4.757 V
• I Z = I ZK Solution
: From the datasheet in Figure 3–7 for the 1N4733A: VZ = 5.1 V at IZ = 49 mA,
Z ==
VOUT(min) = VZ0 + I ZK ZIZK 4.757 + 1 mand
1 mA, ×7Z =Z4.=
76 7V Æ at IZ. For simplicity, assume this value of ZZ over the
V =V
IN(min) + range
I R =of
OUT (min ) ZK
current
4.76 + 1 m ×values.
100 = 4The
.86 Vequivalent circuit is shown in Figure 3–12.
GURE 3–12
• I Z = I ZM : R
valent of circuit in Figure 5.1 V ± "VZ
VOUT(max) = VZ0 + I ZM Z Z = 4.757 + 196 m × 7 = 6.13 V
. 100 !
VIN(max) = VOUT(max) + I ZMR = 6.13 + 196 m × 100 = 25.73 V 7!
+
ΔV 6.13 − 4.76
• %Line regulation = VINOUT × 100% = × 100% = +6.56% < 10%
ΔVIN– 25.73 − 4.86 –
IN(max)
EXAMPLE 3–5 output voltages. Determine the minimum Zener
Figure
and thewithRegulation
3–13
maximum showsinput with
a zener
voltages a Variable
voltage
that canregulator
beCompareLoad
with
regulated byathe
variable lo
outputCompare
voltages. Compare
with the calculated the values.
calculated values.
output output
voltages. voltages. Compare
with w
the calc
ent is Leakage
specified for current
a reverse Reverse
voltage leakage
that
This is less
shows
this zener diode can ideally regulate an input voltagezener current
that
fromdiode this is specified
zener
10.055inVFigure diode
to 32 3–11.canfor
nals. a
The
ideallyreverse
zener
regulate voltage
diode
an that
maintains
input is
voltage less
a nearly
from constant
10.055 V
V Figure 3–13 shows a zener voltage regulator with a variable lo to 32 voltage
V ac
nthe zener isthan
approximate 10 the
not knee The
Vinoutput.
reverse voltage.
outputThis
breakdown means
for
willand
vary thesethatan
maintain
slightly the zener
approximate
because of the current
is not
10 is greater
Vinoutput.
reverse than Iwill
Thebreakdown
output ZK and
for less
vary thesethan because
slightly IZM. of the
! FIGURE 3–11 nals. The zener diode maintains a nearly constant voltage ac
e,for hasmeasurements.
a reverse voltage of 1inFor
V inexample
acalculations.
1N4728A.
Regulation with a Variable Load
IR isimpedance,
100 mA for a reverse voltage isofgreater
1inVthese
inthan
acalculations.
1N4728A.
which been neglected these zener which has been neglected
current R and less than I
IZK ZM.
100 +
R ! ! FI
Zener Regulation
ener Regulation with with aDetermine
a Variable Variable
Load Zener Regulation
LoadRegulation
Zener with
+ withFaYVariable
a Variable Load F YLoad
I by the
I be regulated
minimum andEXAMPLE
• As long
the datasheet 3–5
the maximum as IZK3–7,
inEXAMPLE
Figure IZa ≤1N4736A
input voltages that
≤ 3–4 the minimum
IZM, the output
can be regulated by theand the maximum input voltages that
zenerFrom voltage
diode the aVZOUT
hasdatasheet is3.5
in Æ.
Figure can
VIN 3–7, a 1N4736A zener diode has VOUTa ZZ of 3.5Zener
Æ.F I
Z of The I
R 1N4733A !
Figure Figure
3–11. 3–13 shows a zener zener
voltage diode
regulatorin Figure
with
Figure 3–11.
a
3–13 Figure
variable
shows 3–13
load shows
resistor a zener
across voltage
the termi- regulator with a variable load
gure 3–13 shows
VZ = a6.8 zener
V atvoltage regulator with adatasheet
variable load = a6.8
isresistor zener
across voltage
atthe termi-regulator with atemperature
variable loadis resistor acr
load.
T
–
heet gives almost
nals. The
constant regardless
a test current, IZof
, ofvariation
37 mA. in
What R L.
gives the
VZ voltage
nals. The
+Vacross
zener
a test
diode
current,
maintains
, of of
OneIZtype
a
37
nearly
mA.type
One What
constant
of the voltage
temperature
sensor
voltage
sen
Zene
across
ls. The zener diodezener diode amaintains
maintains a nearly
nearly !constant constant
nals.
voltage The voltage
acrosszener
R across
diode
as long R
as as
maintains
the long
a
zener as the
nearly zener
constant voltage across R as long
ener terminals
• The when
range the current
of is
variation50 mA? in When
FIGURE
R the
the
3–11
and zener terminals
current
I can is 25
be
L mA?
when theLcurrent
VINFigure 3–8 is 50ITmA? When
uses the the
IZ uses
zener current
thebreakdown
diode zener RL
IL isdiode
25 L mA?
breakdoFi
load.
currentthan
rrent is greater is greater
IZK andthan
lessIZK andIZM
than
R less
. than L IZM currentthan
. L is greater
current is greater
I–ZK and
+ than
lessIZK andIZM
than
R less
. than Ivoltage
ZM . as–a temperature ind
sents the zener diode.as follows: represents the zener diode. voltage as a temperature indicator.
obtained +
VIN
–
IZ IL
The breakdown
R
+
Thevoltage
breakdown L
voltage of a
of a zener
100 ! Solution 100 !
From the datasheet in Figure 3–7 for the 1N4733A: VZ = 5.1 V at IZ = 49 mA,
+ +I . For simplicity, assume is directly to
is directly proportional proportional
the to th
IZK = 1 mA, and Z Z = 7 Æ at Z this value of Z Z over the
VIN R R 1N4733A ! FIGURE 3
VOUT !– 1F3IVGINU RRE 3 – 1 3 R Kelvin temperature.
1N4733A Kelvin
V !temperature.
This
F I Gtype
U R Eof3!–This
F1I3G typ
UR
range of current values. The equivalent circuit is shown in Figure 3–12.OUT
– + Zener regulationZener with – a variable
regulation with a variable sensor is small, +sensor is small,
accurate,
Zener and accurate,
Zenerwith
regulation and
reg
! FIGURE
IT 3–12IT IT IT linear. linear.
The LM125/LM235/LM335 The LM125/LM235/LM is
+ I
+ Equivalent I !IZ
Z
!VZ load.
+ R From
load.
+ I No Load I to Full Load
!I Z Z!V
Z
Z load. load.
– Z –
Z Z
T in Figure T
5.1 V ± "VZan integrated –an – that is circuit
integrated
circuit more that is m
of circuit
I I
M-Point (IZ = IZM)

RL I LIN I LL than
K-Point (IZ = IZK)
VIN VIN IZ I
ZKZL I
V R L V
! INFromthe
When Nooutput
Loadterminals
IZto Fullof Load
complex
I
ZMZLthethan
zener I
RL regulator
complex
a simple
R
zener La are open
simple
diode. (R
zener
– – 3–11. L – 100 –
heet in Figure 3–7 for the 1N4733A: V = 5.1
Solution V atthe
From =+ 49 mA,in Figure 3–7
IZ datasheet zero for andthe 7 !of the Vcurrent
all 5.1is
Z = However,V through themA,
=+However, zener; this isa averyno-l
VZ Z V + VZ When the1N4733A:
outputVZterminals ofV
at IZitzener
the 49
displays regulatorit displays
aVvery precise
are open (R p
nd ZZ = 7 Æ at IZ. For simplicity, assume thisIZK =
valueZ0 1ofmA,
Z– over Z = 7 Æ at zero
and Zthe resistor
IZ. Forand (R ) is
simplicity, connected,
assume this part
value of the
Z0 of Z–zener total current
Z
overcharacteristic.
theaddition is through
VIN Z
L
all
+
of the current zener
is characteristic.
through Z the In
zener; isInaaddit
this to no-l
values. The equivalent circuit is shown in Figure range3–12. RL. Thecircuit
of current values. The equivalent total current
is shown through
in Figure
thepart R
anode remains
3–12. the essentially
anode and cathodeconstantterm
– resistor (R–L) is connected, ofandthe cathode
total terminals,
current is through
V
! FIGURE 3–12 OUT(min)
= VZ0 + I ZK Z Z lating. As R
RL. The totalL current VOUT(max)
is decreased, VZ0device
=this
through + Iremains
the
R
load
ZMhasZthis
current,
Zandevice
adjustment
essentially
I
has , increases
L anforadjustmen
constant
a
R R diode continues to regulate the voltage
calibration until
calibration
purposes. reaches
TheIpurposes.
Zsymbol isTheitssym
Equivalent of Icircuit in= "VINZ −VOUT(min)% R $ lating. As R is
I T(min)
L decreased, the
=Z#VisIN maximum,
" −V load $ current,
R I L , increases a
5.1 V
T(max) ±Figure
"V
# point the load 5.1 Vcurrent
± "V OUT(max) and
% a full-load condition
rom100 No
!
From
Load No Load to Full Load
3–11. to Full Load From NoFrom
100 !
Load diodeNo
to Full LoadLoad
continues
ple will illustrate this.
to toFull Load
shown
regulate thebelow.
voltageshown untilbelow. IZ reaches its m
7! Iterminals
= I T(max) I ZKAt Iare
the− zener q
point 7the !q I L(min)
load current is I T(min)
maximum,
=ofregulator − I ZM and a full-load condition
q ),(R
When the
hen the output output
terminals of L(max)
the zener ofregulator
+ ZK = 1 mA,
regulator
When
open are
the
(R the
L When
= open
output
output ),the
(R
voltage=
output
terminals
theL loadis ),terminals
ofthe
the
current
ple will illustrate this.
load
zener
is the
current zener
is regulator
are open (RareL =open L =
the l
ro and all zero and current
of the all ofRthe current is
is through thethrough the zero
zener;Vthis zener; and allzero
this
is a no-load isof andcurrent
a the
no-load
condition. of
all When the
condition.current
is through
a Iload = is
When V through
the azener; the
load this zener; this is condition.
is a no-load a no-load
+ L(min) = VOUT(min)VINI L(max) OUT ! 5.1 V - ¢VZ = 5.1 + V - (IZ R-L(max) ZK)ZZ =OUT(max)
5.1 V - (49 I L(min) - 1 mA)(7 Adjustment
mAAdjustment Æ)
Gsistor
U R E 3(R
–Lresistor
8 (RL) is connected,
) is connected, part of the part totalofcurrent
the
– total current
Fresistor
! is U R E (R
Ithrough
G isL8resistor
3 –the )through
is (R
connected,
zener and L) part
the iszener
connected,
part and
of the
through partpart ofcurrent
through
total the total current is
is through thethrough
zener and the
– = 5.1 V - (48 mA)(7 Æ)– = 5.1 V - 0.336 V = 4.76 V
Load regulation VOUT(min) L.current
=The total
$%VOUT(max) current through remains Determine
essentially constant as lo
OUT(min)' VOUT(min)
. The totalRL.current
The total current
through through
R remains R remains
≡ ΔVessentially
essentially RL. The
constant total
as R
constant
long as as
the long
through
zener
EXAMPLE asisR
−V the zener
remains
regu-
3–6 Rregu-
& isessentially constant as thelong as the
minimum a
OUT
ing. As lating. As RL is decreased,
RL is decreased, the load
the load current, L,current,
lating.
increases
ITherefore, IL,As
and lating.
increases
RILZ is As
andRILZ is
decreased,
decreases. decreased,
decreases.
The load The
thezener thezener
current, load IL,current,
increases L, and
Figure I3–14 increases and
IZ decrease
will maintain
EXAMPLE 3–6 Determine the minimum
©diode
ode continues continues
to regulate
Dr. Ezzeldin tothe
Solimanregulate
voltagethe voltage
until until
IZ reachesdiode Iits reaches
Z continues
minimum
PHYS-2211:diode continues
itstominimum
regulate to
.theregulate
thisIZK.the
value,
voltage At voltage
until this until Iits
IZ reaches VZZreaches
= 12 35
minimum V,itsIZK
mini
=
value
= IZKR + Diode
value, At
I Applications used?
VIN(min) VOUTZK = (1 mA)(100 Æ) + 4.76 V Figure
= 4.86 V3–14 will maintain
point
int the load the load
current current is maximum,
is maximum, and a full-load and acondition
full-load
point theexists.
load point
condition theexists.
current
The load current
Theexam-
is maximum,
following is maximum,
following
and a exam- and awhere
full-load conditionZZ =
full-load 0 Æ and
condition
exists. TheV exis
Zr
fol
, the output voltage is At IZKTo= find
1 mA, the output voltage is used? V Z = 12 V, IZK =
ple willthis.
e will illustrate illustrate this. ple
thewill pleinput
illustrate
maximum willthis.
illustrate
voltage, firstthis.
calculate the maximum zener simplicity.
current. Assume
where Z = 0 Æ and V r
Z E N E R D I O D E A P P L I C AT I O N
Solved Problem (1/2)

Problem (12):
! F(a)
I G UDetermine
R E 3 – 1 5 the value of R that
should be used to allow the maximum load R VOUT
resistance to be infinity (o.c.), and consequently the +
minimum load current to be zero.
+
(b) Find the maximum load current and minimum
VIN RL
load resistance for regulation. 1N4744A
24 V
(c) Calculate the load regulation. –
The data sheet of the zener diode gives the
following information: VZ = 15 V at IZ = 17 mA,
IZK = 0.25 mA, IZM = 66.7 mA, and ZZ = 14 Ω.
• V = V − I Z = 15 − 17 m × 14 = 14.76 V
Z0
Solution ZT ZT Z
The 1N4744A zener used in the regulator circuit of Figure 3–15 is a 15 V diod
• I Z = I ZM : datasheet in Figure 3–7 gives the following information:
VOUT(max) = VVZ0 + I Z = 14.76 + 66.7 m × 14 = 15.7 V
Z = ZM15Z V @ IZ = 17 mA, IZK = 0.25 mA, and ZZ = 14 Æ.
VIN − VOUT(max) V −V 24 − 15.7
I T(min) = (a) For IZK
= I:L(min) + I ZM = I ZM ⇒ R = IN OUT(max) = = 124.4 Ω
R IL(min) =0 I ZM 66.7 m
VOUT = VZ - ¢IZZZ = 15 V - ¢IZZZ = 15 V - (IZ - IZK)ZZ
© Dr. Ezzeldin Soliman = 15 V PHYS-2211:
- (16.75 mA)(14 Æ) = 15 V - 0.235 V = 3614.76 V
Diode Applications
Calculate the zener maximum current. The maximum power dissipation is
Solved Problem (2/2)
• I Z = I ZK :
VOUT(min) = VZ0 + I ZK Z Z = 14.76 + 0.25 m × 14 = 14.76 V
VIN − VOUT(min) 24 − 14.76
I T(max) = = = 74.28 mA
R 124.4
IL(max) = I T(max) − I ZK = 74.28 m − 0.25 m = 74.03 mA
VOUT(min) 14.76
RL(min) = = = 199.38 Ω
IL(max) 74.03 m
ΔVOUT 15.7 − 14.76
• Load Regulation = = = 0.0637 < 0.1
VOUT(min) 14.76

pacitors to complete the regulation portion of the power supply, as shown
Filtering is accomplished by a large-value capacitor between the input vol
An output capacitor (typically 0.1 mF to 1.0 mF) is connected from the ou
Power Supply Regulators
improve the transient response.
• The!voltage
FIGURE regulator
2–50 is a three Input
from Voltage
terminals Output
A voltagedevice,
regulatorwhich is used
with input and to regulator
rectifer
suppress the residual ripples in
output capacitors.
Gnd
the output of the filtered rectifier. C1
P OW E R S U P P LY F I LT E R S C2 D R E G U L ATO R
AN
• The main component of this

A basic is
regulator fixed supply with a +5 V voltage regulator is shown in Figure 2–51.
powerdiode.
a zener
Specific integrated circuit three-terminal regulators with fixed output voltages are covered
in Chapter 17.
• The figure below shows a complete power supply system.
On-off F1
T1
switch
0.1 A D3 D1
Voltage
SW1 120 V ac 12.6 V ac +5.0 V
regulator
D2 D4
+ +
C1 C2
D1–D4 are 1N4001 rectifier diodes.
©!Dr.F I Ezzeldin
G U R E 2 – 5 Soliman
1 PHYS-2211: Diode Applications 38
A basic +5.0 V regulated power supply.

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Diode Applications (Outline)

peak inverse voltage

fin fout and

reifitcer evaw-flaH )b(

• The diode is reverse- –

© Dr. Ezzeldin Soliman PHYS-2211:

© Dr. Ezzeldin Soliman PHYS-2211:

F Npri : Nsec " FIGURE 2–27

© Dr. Ezzeldin Soliman PHYS-2211: Diode Applications 5

Solved Problems (1/2)

Vp(out) = Vp(in) - 0.7 V = 100 V - 0.7 V = 99.3 V

Solved Problems (2/2)

Vp ( pri ) = Vp ( in) = 156 V

Power Supply Filters (2/4)

• The capacitor is fastly – +

• τcha = r’d C, is small. 0

EXAMPLE 2–8 Solved Problem

rectifier with a load as C + RL

All diodes are 1N4001.

≅ Vin - Vp(in) 0 + 0.7 V (b) – I + Vout

o the input voltage by superposition,

uce the output voltage as shown in Figure

round level due to the charging current.

by superposition, as in Figure 2–63(b).

becomes forward-biased. This charging occurs

If the capacitor wave, action

I voltage as shown in Figure 2–64.

.)b(36–2 erugiF ni sa ,noitisoprepus yb egatlov tupni eh

1/4 level due to the charging

uce the output voltage as shown in Figure 2–64.

eht htiw The

f the diode is turned around, a negative

oitisoprepus yb egatlov tupni

Vp(in)RC – 0.7timeV constant of ten times the

he input voltage by superposition,

1st -ve 01/4

ntially as a battery in series with

0 ground level due to the charging current.

Vout RLR Vout

und level due to the charging

mately equal toinput

This discharging the portion of indicated solid

If the diode is turned–around, a negative 0 tdc voltage is added to the input vo

capacitor discharges period of input clamping

-V Vin V - 0.7 V to forward-bias +

Vin A 0V V10 k!– 0.7 V

R1 A this Rcase, the voltage R

• The three commonly used voltage-dividers are shown below:

+VSUPPLY –VSUPPLY +VSUPPLY

Vin R2 Vout Vin R2 Vout Vin R2 Vout

© Dr. Ezzeldin Soliman ! FIGURE 2–60 PHYS-2211: Diode Applications 22

Problem (6): WhatSolution

expect to see displayed on So, for the negative limiter, determine10the

• Vin = 10V: ! FIGURE 2–59

• Vin = −10V: ! FIGURE 2–59 –5.7 V

" FIGURE 2–61

The output voltage waveform

⎛ R3 ⎞" F I G U R⎛E 2220 – 6 2 ⎞

Attribute Regular Diode Zener Diode

age should be.

For most circuit analysis and troubleshooting work, the ideal

(a) Practical model

Zener Equivalent Circuit

© Dr. Ezzeldin Soliman PHYS-2211: Diode Applications 31