Q No Question Answer Domain Subdomain

1 cross talk effect on timing? Cross talk delay effects the setup ROUTNG and hold. CROSSTALS
2 What is Cross Sectional Are Cross-sectional area is the Routing Routing Overview
3 In power planning for rings For rings and stripes we use Routing Route Steps
4 How the R, C of the net mode Equal segments of the net will have the R, C values.
Routing Distributed
Concept capacitance
of Metal layers and resiPDnce o
5 Tool could not able to PDrt • Pitch -Specifies the required Routingrouting pitch for the layer. Pitch is used to generate the rou
6 Why Filler Cell Insertion? •● Metal Width
For better yield, density of the chip needs to FILLER
ROUTING be uniform CELL INSERTION
7 ● Some placement
Why Metal Fill Insertion? ● Non uniform metal sites remain
density empty
causes
ROUTING on some
problems Rows
METAL manufacturing
during FILL INSERTION
8 a. Especially., Chemical
What's the effect on setup a1. It will improve setup timing mechanical polishing
for both full and Tiiming
Routing half cycle timing paths
Analysis
9 Does hold depend on frequ 1. 2. HoldIt willdoesn’t
not affect the hold
depend if it is a fullfor
on Routing
frequency clock
full cycle
cycle path
timing (as
Tiiming Analysis launch
paths (sameand reason
captureasedges
above)come
10 2. But hold depends
Why do antenna violations cPower nets are not connected on frequency
Routing for half cycle timing paths
Antenna Effect as the launch and capture ed
11 On a post signoff DB, if we Timing windows for each of th Routing Tiiming Analysis
12 Pre & post-route correlation● At pre-route stage, interconnect Routing RC delays are calculated
Route Steps with elmore delay engine by d
13 ● At the pre-route stage,
Why is the Metal Density R ●Metal Density Rule helps toRouting coupling caps were
avoid Over Etching or not considered
Metal of
Concept andIflayers
Erosion.
Metal hence
there cross-talk effect
is a lot of gap betw
14 ●We have to maintain
Why is thick metal layer ne These thick layer has more chance minimum Routingand maximum density
of variation in Concept of
manufacturing.a particular
of Metal layers layer within a specifie
15 As thickness is higher, less
Tell about Non-Default RuleNDR are mainly used in placeRouting spacing results in crosstalk
& routing section of design flow. issues due to more
when theycapecitance
actually route the
16 The Default routing guideline
How multiple vias are used tAs multiple vias are introduceRouting for the router would VIA's definitions and ty (incase of Encoun
be provided by tech Lef
17 Why double via insertion? To reduce the yield loss due tRouting VIA's definitions and ty
18 Red color region shows the 1. Placement density ROUTING
19 Why scan re ordering is req 2. Pin process
It is the density due to high fan
of reconnec in cells like AOI,OAI
ROUTING
20 Why HVH routing is used geSince logic cell interconnect usually ROUTING blocks most of the area on the m1 layer.
21 HVH is efficient
What is the difference betwGlobal Route (G Cells) if you have standard
ROUTING cells in the row fashion because the M2 vertical layer u
22 Why float output are ignored Channel
Float gateassignment
inputs may pickup ROUTING any value. So
23 What is the difference betw1.In VLSIBoth the transistors
design, both Process mayAntenna
form theViolation
ROUTING conduction(PAV)path andand short circuit
Geometry AntennaVDD&VSS.
ViolationPower
(GAVd
24 Which type of Antenna diodOnce the chip is fabricated, this cannot happen, since every net has at least some source/dr
ROUTING
25 Before routing your timing Taking
1. Before a small
routing metal
the jump to Routing
net delaystheare higher level isvalues,
estimated the firstbut
Tiiming step that
after
Analysis shouldthose
routing be tried, rather thaS
are accurate.
26 For antenna violation what e2.
a) While
when doing
we haverouting we will
antenna enable some
violation
Routing in top options likefirst
level,Antenna
then SI Effect
aware ( cross
observe porttalk ),so toofavoid
location cro
the bloc
27 Fixes:
Why Standard cell width is iStandard cell width is usuall Routing Concept of metal layers
28 What is the difference betwe Global routing: just you can see the lines with outRouting
Routing vias. Steps
29 Detailed
How the Ntap and Ptap are NTAP Routing:
= NSRC ANDPhysical
NWELL nets with
Routing vias Rule Deck File
30 How capacitance modeled for PTAPon
Nets = PSRC ANDlayers
different PSUBwill have Routingbelow components Concept of metal layers
31 How will you decrease the pro• Overlap (bottom and
• Anticipating the similar problems top) capacitance
Routing and comingFlow up withRun quick
Time fix solutions
•a) Setup:
Scripting the methodology/patches
1. Increase the metal width.
2. Route with highest metal
layers.
3. Hold :
32 How to fix setup and hold vio 1. Detour the net. Routing Tiiming Analysis
2. Route with lower metal
layers.

• cts netlist (.v)

• cts def
• sdc
33 What are the inputs for rou • lef ROUTING Routing Inputs
• lib
• captables
 • timing (drv’s , setup and
hold)
• drc’s ( design rule
checks )
34 After routing what you will • core utilization ROUTING Route Quality Checks
• cell legality
• congestion

spacing issues , shorts and

35 Tell me some DRC’S you fix opens. Routing Route Steps
DRC : DRC is design rule
violations. In DRC it checks
the design is meting DRC
rules given by foundry or
not.
LVS : LVS means Layout
versus schematic . It is a
36 What is DRC and LVS? method of verifying that the Routing Route Quality Checks
layout of the design is
functionally equivalent to
the schematic of the design.

opens and shorts are

37 Opens and shorts they are Lrelated to LVS issues. Routing Route Quality Checks
38 DRC is passing and LVS is faiYes Routing Route Quality Checks
39 LVS is passing and DRC is faiYes Routing Route Quality Checks
 When a long metal is
connected to the gate
terminal charge
accumulation takes place
on the surface of the metal
during the etching of
plasma. This charge tries to
discharge at gate and
damages the gate oxide.

Ways to fix congestion:

1. Metal jogging :

This is preferred when the

antenna effect occurs in
lower metals. We split the
metal near the gate and
40 What is antenna violation anadd a higher level metal routing Antenna Effect
parallel to that. Only higher
level metal are preferred
because during fabrication
lower metals are fabricated
first. If charge accumulation
takes place ,it can be
removed by process known
as rinsing.

2. Antenna diode:
This is preferred when the
A.E occurs in higher metals.
We connect it near the gate
terminal in a reverse biased
mode. As the charge flows
breakdown occurs and no
harm happens.
3. Break the net and add
If there are less no.of
metals than specified in
particular region then it
results in min density
violations. If there are min
41 What is min density and whydensity violations it results routing Route Quality Checks
in dishing effects it causes
opens.

If we over constraint the

max tran and max cap
42 More buffers are added on lvalues, then over buffering Routing Tiiming Analysis
will be happen.

43 Tool could not able to star • Pitch -Specifies the required routing pitch forRoute
Routing the layer. Pitch
Quality is used to generate the rou
Checks
44 • Metal Width
How to fix hold after routingA. Adding buffer Routing Tiiming Analysis
45 Why are metal layers taller B. Enable
After the view
reduction , route_opt
in width –hold,
resisRouting Concept of Metal layers
46 Ndr, non-default routing ruleA. Any change in default routing rule (minspace, minwidth),
Routing Route Stepsis called ndr
47 Why is shielding percentageB.A. Width:
Difference between routing estimation
Routing to actual routes
Route Steps
48 Checks after routing B. More areas
A. Open nets become congested, so
Routing the ndr reduced
RouteinQuality
design.Checks
49 Reporting in routing B. Drc
A. Qor (shorts
b g b and total drcs) Routing Tiiming Analysis
B. Group-by-group
50 What is z in routing comma A. 45-degree routing capability of the tool
Routing Routing Overview
51 B. Used for rdl
Changing the metal layer forA. By attribute routing or analog designs
Routing Concept of Metal layers
52 Why do we have different thiB.
AndBywhy
ndr is that the thicknessRouting Concept of Metal layers
 Subdomain Level
CTS 4
CMOS 2
Basics of Floorplan 3
Metal layers 1
3
3
3
4
5
4
3
3
Metal layers 3
Metal layers 3
3
signal integrity & cr 2
via definations 2
Routing overview 2
DFT 2
Routing overview 3
Routing overview 3
Electronics 3
Power Analysis at Si3
Power Analysis at Si3
Routing Overview 2
Antenna Effect 2
placement overview2
routing overview 2
LVS 2
metal layers 2
3

4
4

4
4
4
 4

4
4
3
Metal layers 3
4
4
4
4
 5
Metal layers 4
Metal layers 4