Q No Question Answer Domain Subdomain SubdomainLevel

1 while doing floorplano need of sdc whFLOORPLAN SDC INPUT 4

2 How much space/area 5 M, Horizontal= M1, M3,
Floorplan M5 Macro definition and place1
3 Can we place cells Vertical=
No, we cannotM2, M4 plaFloorplan Basics of Floorplan 1
4 What do we need toTo start a floor p Floorplan Floorplan Overview and st 1
5 What are the guidel● Place macrosFloorplan around chip periphery: If you don’t
Macro definition and have reasonable rationale to place the macro
place1
6 ● Consider connections
what happens if pinsActually the top l Floorplan to fixed cells when
Pin Placement placing macros: 2When you decide macro position, you
7 What are the physica ● End Cap cells: Floorplan Physical Cells and their im 1
8 Where do you get t ○ ● These
Wire LoadcellsModels
prevent
Floorplan cell damage
(WLM) duringDesign
are Physical
available fabrication.
from the Inputslibrary vendors.
4
9 What is a HALO? How ●
BlockWe don't
halos cancreate WLM.
beFloorplan Macro definition and Macr4
10 Whether macro powe For hierarchical d Floorplan rings, stripes and rails con 3
11 What are tie-high anTie-high and Tie-LFloorplan Physical cells placement g 3
12 What Is Partitioning● Partitioning isFloorplan the process of splitting a design into manageable 4 pieces. The purpose of partition
13 What parameters (or ● Partitioning
● Chip design has splits design for logical and
I/O pads; block design has pins.
Floorplan physical implementation.
4 For hierarchical physical imple
14 ● Chip design
What’s the purpose●o In lower technology uses all
Floorplan metal layers available;
nodes, transistor
Physical gate block
cells oxide
placementdesign
is so thinmay not use all metal
g 3 and it is sensitive tolayers.
voltage fluctuatio
15 ● So the
There are 10 macros● Total macro pinsTIE cell was introduced to
available areMacro
Floorplan prevent
10x200=2000 ESD
definition issues.
andand vertical
Macr4metal layers available are M3, M5 & M
16 How do you get llx ● ● Assume min horz
set llx [lindex [lindexspace
Floorplan needed
[dbGet [dbGetis H. Then
-p total space
top.instance.name
MACRO ATTRIBUTES AND needed is
4 $macro].box] 0] 0]
17 ● set lly [lindex
What does the delay● Input slew Floorplan [lindex [dbGet [dbGet -p top.instance.name
Physical Cells and their im 3 $macro].box] 0] 1]
18 Explain CEL and FR ● ● CEL Output load
is the complete
Floorplan view of the designCells
Physical with placement
all the layers G 3(like GDS) FRAM is just the skeleton vie
19 What are the recomm ● CEL view: The
For design with complex full layout
Floorplan view of
or fragmented a physical
Floorplan structure
floorOverview
plans thatand such
have as a via,
st 3narrow standarduse
channels, cell,
themacro, or whol
following setti
20 ● Look
What will you look for
● Enable forglobal-route-based
macros Floorplan high-fanout synthesis
Floorplan Overview and st 5 for the place_opt command, which can improv
21 If you have an alway●In AONGroup
domainmacrosFloorplan
acc to hierarchyPhysical Cells placement G 3
22 Why is input capacit● All STD cells are designed in two
Floorplan stagesCells
Physical [ 1stage=>2
and theirstage]
im 3
23 Why is TAP cells re ● 1st stage
a. LATCH issuewhich is mainly for functionality
Floorplan Physical Cellsofand thetheir
cell im 3
24 b. Atif65nm
Can macro be placeYES, macro TAPown cells start using Macro definition and place3
Floorplan
25 Can there be macroYes, with proper Floorplan Macro definition and place3
26 What is the conceptrows will be multiFloorplan Floorplan Overvphysical de2
27 What Is Latch Up? Latch-up pertainsFloorplan Basics of Floorp Electronic 2
28 What Is Latch Up? ELatch-up is a con Floorplan Basics of Floorp Electronic 2
29 Give 5 Important De• In digital design, decide
FLOOR PLAN the height of standardPD cells you want 2 to layout.It depends upon how big
30 • Use one
What checks you do1. Netlist uniquenessmetal in one
FLOOR PLAN direction only, This does not apply
Synthesized1 for metal 1. Say you are using metal 2 t
31 What Floor plan che2.• Assignment
IO timing statementsFLOOR PLAN Floor Plan 2
32 How do you calculatCoreMacro
• P/G Ring to macro
WiFLOOR timing
PLAN VLSI Desig 2
33 What is Pad limited Pad limited designFLOOR PLAN VLSI Desig 2
34 Is there any check l Yes. The SwitchingFLOOR PLAN Floor Plan 2
35 What is the tap less65nm and beyondFloorplan CMOS designs are commonly
Physical Cells aimplemented
PV 4 with “tapless” library cells which do n
36 Tap less spacing=
How we will assign channel standard Floorplan
cellofshould
no connect
pins*pitch/ Basics of Floorp Macro defi2 cells to have the good continuity. We
to
(total tap cells
number through
of metal filler
layers/2)
37 Make sure at least
What is tie-high andIn the lower technFloorplan one line of power switches
Physical Cellsshould be present
a Physical Ce1 in the macro channels
38 Explain macro guide1. If you don’t have reasonable rationale
Floorplan Macro to place the
definitio Macro macrodefi1inside the core area, then place macros
39 What is the differen2. Communicating
soft blockage : It won’t macros
Floorplanallowshould be
std cells placed
Basicsto place closure
in that
of Floorp toarea
Macro each other.global placement. But it allows buff
during
defi1
40 Hard blockage
How channel spacinChannel spacing : Itbewon’t allow std cells
Floorplan Basics toof place in that
Floorp Macro area during global placement and optimizatio
defi1
41 why you placed pinsThe IO ports locatFloorplan Pin Placement Floorplan 2
42 If we do macro abu There are two cases Floorplan Macro definitio Basics of F 2
43 In netlist we didn’t 1.
In If
deftwo
filemacros
we havcommunicating
Floorplan only
Pin with each other
Placement PD we can2abutment the macros
44 How will you place By using design brFloorplan Macro definitio Macro defi3
45 On what basis will • IP guide linesFloorplan Macro definitio PD 1
46 What are constraints •Generally
Sensitive blocks
PDndard (PLL,ADC,DAC,Macro
Floorplan touchdefinitio
screen) should
PD be placed
1 far from high frequency blocks a
47 How the IO pad arr Depending on theFloorplan Pin Placement Basics of F 2
• Signals coming direction in the board
48 What is the die size First decide whether it is pad limited
Floorplan or core
Basics limited
of Floorp design.
Basics of F 2
49 Can we place macros • Pad limited ,
It depends on whiFloorplan Macro definitio Macro defi2
50 Could you place theNO because Floorplan Basics of Floorp placement 2
51 How much placement •65 toNeed
75% to create
is allo the core rows Utilization
Floorplan to place, extendPhysical
the follow
ce2pins
52 How Latch up is take• Guard rings(analog) Floorplan, Tap cells(digital)
Physical will be added in checker board fashion in each row of the
cells(TaElectronics2
•StepsBody
in biasing (Nmos to ground, Pmos to VDD)
Floorplan
 Initialize
with Chip & Core
Aspect Ratio
(AR) —

initialize_floorpl
an -shape L -
orientation W -
side_ratio {2 2 1
2} -core_offset
{20}
 Initialize
with Core
Utilization —
 Initialize
Row
53 How we executed flo Configuration & Floorplan Floorplan Overview and st
Cell Orientation
a) Provide the
Core to Pad/ IO
spacing (Core to
IO clearance)
b) Pins/ Pads
Placement

create_placeme
nt –floorplan
create_pin_guid
e
set_block_pin_c
onstraints
create
Halos/keepout
margins
4
 Endcap cells are
the physical only
cells, which are
placed at the
boundary of the
chip to avoid cell
damage during
fabrication and
to provide nwell
54 What are Endcap celcontinuity to the Floorplan Physical Cells and their im
std cells at the
end of the rows.

4
CreatePlacemen
tBlockage –type
partial –density
65 –box {x1 y1 Floorplan
what is the command Types of Blockages & Over
x2 y2}

55 4
Halo is one type
of blockage; it
placed around
the macros to
56 why we use halo? avoid base drc Floorplan Types of Blockages & Over
violations.

4
I worked on
three projects ,
in that two are
57 what block shapes rectangle and Floorplan Floorplan Overview and st
one is square.
4
 Floor planning :
• define core
area
dimensions,
calculate
utilization and
aspect ratio then
• place IO ports
then
• place macros
what you will do in by following Floorplan Floorplan Overview and st
macro
guidelines then
• place physical
cells

58 4
In floorplan
stage only
Endcap cells and
59 what are the preplaWelltap cells are Floorplan Physical Cells and their im
placed.
4
 It loads the
netlist. But
shows errors like

LIB missing: The

design has been
initialized in
physical-only
mode because
the
init_mmmc_file
global variable
was not defined.
Timing analysis
will not be
possible within
this session. You
can only use
60 What happens if lef commands that Floorplan Floorplan Overview and st
do not depend
on timing data.
If you need to
use timing, you
need to restart
with an
init_mmmc_file
to define the
timing setup, or
you can save
this design and
use
restoreDesign -
mmmc_file
<viewDef.tcl> to
add the timing
setup
information. 4
 The stripes will
get power from
power rings.
And the macros
will get power
from stripes.
Generally for
power stripes
we will use
higher metal
layers (M8, M9)
but macro pins
are on M3, M4, Floorplan
Explain how power w Placement Overview and PG
M5, M6 layers,
so there should
be stacked via
from via3 to via9
to connect stripe
to macro pin.

61 4
 Placing a macro
centre of the
core can invite
serious
consequence
during routing
due to a lot of
detour routing,
because macros
are equal to a
large obstacle
for routing.
Another
advantage to
placing the hard
macros around
the core
periphery is it's
62 Why we should not easier
p to supply Floorplan Macro definition and place
power to them,
and reduces the
change of IR
drop problems
to macros
consuming high
amounts of
power.

4
After post route
optimization we
will add buffers
63 what stage filler ce in the design. Floorplan Physical Cells placement G

4
 Decap cells are
temporary
capacitors
added in the
design between
power and
ground rails to
counter
functional
failures due to
dynamic IR drop
happens at the
active edge of
the clock at
which a high
percentage of
sequential and
digital elements
What are Decap cellswitch. At active Floorplan
edge
of clock when
the current
requirement is
high, these
decaps
discharge and
provide boost to
the power grid.

One drawback
of decap cells is
that they are
very leaky, so
the more decap
cells the more
leakage.
64 Physical Cells and their im 4
65 How do you getllx &Set llx [lindex [l Floorplan 3
66 Can we increase grcNo user control inFloorplan 5
67 What is the type of A. Endcap: nwell ending
Floorplan Physical Cells and their im 2
68 B. Tap
Why is core to die s A. cells: body Floorplan
Ports bias contact Floorplan Overview and st 2
69 B. Avoid shorts b/w blocks
What is the factor l Poly manufacturinFloorplan Floorplan Overview and st 2
70 What we need to staTo start a floor p FLOORPLAN Physical design inputs 1
71 Why is decap calledThey get charge i FLOORPLAN Physical Cells and their im 2
72 Macro model: A. Having clock, from io port (macro
FLOORPLAN pin) to
Macro registersand
definition inside macro. I. Required during cts build (min a
place5
B. Transition and load information of all macro pins