Nishanth B V

PROFILE SUMMARY:

✔ Physical Design Engineer with 3 years of total experience in VLSI

✔ Technology Nodes: 10nm,14nm,16nm
✔ Tools Used: Synopsys Tools ICC2, Design Compiler, Innovus
✔ Language: basic TCL Scripting
✔ Technical Skills : Physical Design, Static Timing Analysis, Sign off, ECO, TCL scripting, Synthesis, ETC.
✔ Previous Client Experience: Texas.
EXPERIENCE SUMMARY:

● Physical Design Engineer- Mirafra Technologies - Present

● Physical Design Engineer Intern , Abhyatam Smartworks Pvt Ltd 12/2023
● Physical Design Engineer, 2021/june – 2023/December:

PROJECT DETAILS:

Project Description Role & Challenges

10nm Client : Texas Instruments
Node: 10nm Block: Clock
Frequency – 3clock and
1GHZ
Macro count – 40 macros
Tool Used:
Synopsys ICC2, Primetime.
 Multiple iterations of floor plan to achieve acceptable
congestion.
 Rectilinear floor plan with lots of congestion High congested
design where macro placement played a key role
 Timing closure of highly congested design by techniques such as
load-splitting, swaps, sizing, buffering
 Congestion fixing, Timing fixing DRV Fixing.
 DRCs (Shorts and opens)
 Timing Analysis &Optimization techniques.

16nm Client: Texas Instruments

Node: 16nm Block: Clock The following stages of Physical Design were covered in this project
Frequency -4 clock and work.
1GHZ; ● Floor plan: Used source file for placement of IO Ports. Placed Macros,
Macro count - 20 macros; created keep out margin for macros. Fixed Macros and IO ports. Added
Metal Layers-13 End-Cap Cells, Tap cells. Derived PG connection, created power straps
Tool Used: for nets VDD, VSS and pre route standard cell rails,
Synopsys ICC2 ● Placement: Create placement, legalized placement, Verified Cell
density, Pin density, Placement utilization & generated Congestion
report. Setup fix Drv fix.
● CTS: Defined the routing rules width and clock nets, specified CTS
buffers used for optimization. Setup fix hold fix Drv fix done.
● Routing: Defined routing layers for routing, fixing timing and shorts
and opens.

Internal
 14nm Client: SIPREL
Technology :14nm; ● Macro Placement using Flyline analysis.
Clock Frequency –
● Creating the secondary grid at initial Floorplan stage and Adding
1.6GHz;
Custom Buffers and verify the secondary grid after Floorplan
Tool used : Innovus stage.

● Port Placement.
● Bound creation (Hard bound) at pre-place stage with
specified region for cells.
● Place stage issues with congestion, cell density, pin
density.
● After CTS stage issues with Skew, Latency.
● After Post CTS issues with setup and hold violations.
● After Route OPT stage issues with shorts, opens.

ACADEMICS:

 BE (ECE) from M S Engineering College , Bangalore.

 Training: Physical design training from VLSI Guru, Bangalore.

Internal