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NK Arjun
NK Arjun
NK Arjun
Email: nkarjun9997@gmail.com
PROFILE SUMMARY:
● Physical Design Engineer, 2021– 2024: Working as Physical Design Engineer for Ai Micron client
from BigPerl Solutions Pvt Ltd.
PROJECT DETAILS:
TSMC 10nm Client: Ai Micron This Project is from RTL to GDS, and this block was critical with
respect to timing and congestion.
>Node: 10nm. Sanity checks in each stage
Responsible for timing closure using STA.
>Clock Frequency :1Ghz. DRC, LVS and IR checked as a sign-off checks.
Analyzed and changed the Bounds Placements for worst timing
>Block Dimension: critical paths.
620x2800um(WxH) Analyzed and fixed Intra and Inter Timing and DRC are by
several ECO Iterations.
>Tool Used:
Synopsys ICC2,Primetime
Nokia >Technology node : 5nm Block level Synthesis, SDC validation
Roject > Technology Node :7nm - Synthesis & STA Environment setup
Neolite - LIB/LEF & NDM generation across multiple corners
> Tool : Fusion Compiler, - Tech-Node Migration for the Modules
Prime Time - Synthesis, STA and CLP for the Modules
- Timing closure with usage of less leakage cells
> Frequency : 2.1 GHZ
- ECO (Engineering Change Order) done on netlist to swap the
> Cell count : 480 K memories (to reduce clock to q delay) and provided feedback to
design team
> Description : Block Level
Implementation
NXP PF8200 >Tech node : 45nm Done Block level Synthesis, SDC validation
Complete analysis of timing and constraints
>100k gate count. related issues
Involved in LEC implementation
>It has 2 clocks with
Operating frequency of Fixing of preserve related issue, timing lint issue,
0.25GHz SDC modifications, Checklist requirement
>Tool Used:
Genus, PT, Conformal
ACADEMICS: