Nishanth

Physical Design Engineer

Exp: 4 Yrs
TECHNICAL SUMMARY

● Having 4 years of experience as a Physical Design Engineer

● Hands on technical expertise in Block level physical design implementation from Netlist
to GDSII.
● Worked on 10nm, 14nm, 16nm , 28nm
● Good knowledge and Understanding of Synthesis.
● Good knowledge and Understanding of Low power management techniques.
● Good knowledge and Understanding on UPF creation.
● Good knowledge on Static Timing Analysis.
● Basic knowledge of TCL Scripting.
● Hands on experience on cadence Innovus, Synopsys ICC2 and Primetime.
● Ability to multi-task and flexibility to work in global environment.

TECHNICAL SKILLS
● Operating System : Windows and Linux.
● EDA Tools : Synopsys ICC2, Design compiler (DC), Primetime.
● Scripting Language : TCL

WORK EXPERIENCE:
● Working as Sr. PD Engineer at Logic Semi Technologies Pvt Ltd Feb 2023.
● Worked as PD Engineer in APPEX-Semiconductor Pvt Ltd from 25th July 2019 to Jan
2023.

EDUCATION QUALIFICATION:
● Bachelor of Engineering in Electronics & Communication in 2019, from M. S. Engineering
College [ISO Certified 9000:2015, Approved by AICTE, Accredited by NAAC], Bengaluru
[Visvesvaraya Technological University, Belgaum]
PROJECT DETAILS:
Project: 1
Duration : 7month
Client: Texas Instruments

Tools Used Synopsys ICC2,Primetime

Technology 10nm
Instant Count 2M
Macro 40
Clocks & Frequency 3clock and 1GHZ
Roles & Responsibilities Floor plan and timing closure responsible for block
DRC

Description and Challenges:

● Multiple iterations of floor plan to achieve acceptable congestion.
● Rectilinear floor plan with lots of congestion High congested design where macro
placement played a key role
● Timing closure of highly congested design by techniques such as load-splitting, swaps,
sizing, buffering
● Congestion fixing, Timing fixing DRV Fixing.
● DRCs (Shorts and opens)
● Timing Analysis &Optimization techniques.

Project: 2
Duration : 7 Month
Client: Texas Instrument
Technology/Layers 16nm/ 13 Metal layers
Instant count 2M
Macros 20
No. of clocks 4 clock
Frequency 1GHz
 Tool Used Synopsys ICC2, Primetime
Role Floor plan ,Place and route

Description and Challenges:

● The following stages of Physical Design were covered in this project work.
● Floor plan: Used source file for placement of IO Ports. Placed Macros, created keep out
margin for macros. Fixed Macros and IO ports. Added End-Cap Cells, Tap cells. Derived
PG connection, created power straps for nets VDD, VSS and pre route standard cell rails,
● Placement: Create placement, legalized placement, Verified Cell density, Pin density,
Placement utilization & generated Congestion report. Setup fix Drv fix.
● CTS: Defined the routing rules width and clock nets, specified CTS buffers used for
optimization. Setup fix hold fix Drv fix done.
● Routing: Defined routing layers for routing, fixing timing and shorts and opens.

Project: 3
Duration : 7 Month
Client : SIPREL
Tools Used INNOVUS
Technology 14nm
Instant Count 1M
Macro 11
Clocks 1.6GHZ
Roles and Responsibilities Block level PnR implementation

Description and Challenges:

● Macro Placement using Flyline analysis.
● Creating the secondary grid at initial Floorplan stage and Adding Custom Buffers and
verify the secondary grid after Floorplan stage.
● Port Placement.
● Bound creation (Hard bound) at pre-place stage with specified region for cells.
● Place stage issues with congestion, cell density, pin density.
● After CTS stage issues with Skew, Latency.
● After Post CTS issues with setup and hold violations.
● After Route OPT stage issues with shorts, opens.
Project: 4
Duration : 5 Month
Client : Arm
Tools Used Synopsys ICC2
Technology 28nm
STD Cells 36k
Clocks 6
Frequency 720MHZ
Roles Performed block level PnR implementation

Description and Challenges:

● Responsible for completion of block – Netlist to GDS.
● Understanding the design flow from import design to routing.
● Completed PnR action such as Floor planning, Placement, CTS and Routing.
● Come up with different floor planning by debugging congestion and timing issues.
● Perform placement by placing std. cells on core area and analyse and resolving
congestion.
● Completed CTS by applying NDR rule to clock net by taking care of Signal integrity issues
like Crosstalk.
● Capable of analysing skew optimization during CTS and analyse and resolving timing
issues.
● Challenges faced in macro placement and congestion and timing issues (setup).