CH7025/CH7026

Chrontel Brief Datasheet

CH7025/CH7026 TV/VGA Encoder

Features General Description
• TV encoder targets the handheld devices and other appropriate The CH7025/CH7026 is a device targeting
display devices used in consumer products. (i.e. automobile) handheld and similar systems which accept digital
• Support multiple output formats. Such as SDTV format (NTSC input signal, and encodes and transmits data
and PAL), HDTV format for 480p,576p,720p and 1080i,
analog RGB output for VGA. Sync signals can be provided in
through 10-bit DACs. The device is able to encode
separated or composite manner (programmable composite sync the video signals and generate synchronization
generation). signals SDTV format for NTSC and PAL
• Three on-chip 10-bit high speed DACs providing flexible standards and HDTV format for 480p,576p,720p
output capabilities. Such as single, double or triple CVBS and 1080i. Analog RGB output and composite
outputs, YPbPr output, RGB output and simultaneous CVBS SYNC signal are also supported. The device
and S-video outputs.
accepts different data formats including RGB and
• 16Mbits SDRAM is used as frame buffer. Supporting for frame
rate conversion.
YCbCr (e.g. RGB565, RGB666, RGB888, ITU656
like YCbCr, etc.). 16Mbit SDRAM is embedded in
• Flexible up and down scaling engine is embedded including de-
flickering capability. package. Frame rate conversion and Image rotation
• Programmable 24-bit/18-bit/16-bit/15-bit/12-bit/8-bit digital
are possible.
input interface supports various RGB (RGB888, RGB666,
RGB565 and etc), YCbCr (4:4:4 YCbCr, ITU656) and 2x or 3x
multiplexed input. CPU interface are also supported.
• Support for flexible input resolution up to 800x800 and
1024x680.
• Pixel by pixel brightness, contrast, hue and saturation
adjustment for each kind of output is supported. (For RGB
output, only brightness and contrast adjustment is supported).
• Pixel by pixel horizontal position adjustment and line by line
vertical position adjustment are supported.
• 90/180/270 degree image rotation and vertical or horizontal flip
functions are supported.
• Macrovision 7.1.L1 for SDTV is supported in CH7025.
(CH7026 is Non-Macrovision part.)
• MacrovisionTM copy protection support for progressive scan
TV (480p, 576p CH7025 only)
• CGMS-A support for SDTV and HDTV
• TV/Monitor connection detect capability. DAC can be switched
off based on detection result. (Driver support is required)
• Programmable power management.
• Flexible pixel clock frequency from graphics controller is
supported. (2.3MHz –120MHz) Flexible input clock from
crystal or oscillator is supported. (2.3MHz – 64MHz)
• Only slave mode supported.
• Offered in BGA or QFP package.
• Fully programmable through serial port.
• IO and SPC/SPD voltage supported is from 1.2V to 3.3V.

Note: the above feature list is subject to change without notice. Please contact Chrontel for more information
and current updates.

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SDRAM

Input
RGB/YCbCr data
format
decoder HUE
SAT
CSC CSC
BRI TV
MUX (YCbCr Scaler MUX (RGB to
CON formater
CSB to RGB) YUV)
VP
WEB HP
CPU
VSYNC interface
DIN

MUX
SPC

Serial
SPD port

R/Y/CVBS/Y_Svideo
DAC 1
BRI
CON G/Pb/CVBS/C-Svideo
DAC 2
XI VP
HP
G/Pr/CVBS
PLL DAC 3
XO

CSYNC
SYNC Composite
H,V,DE VSYNC
position sync
adjust generation HSYNC

Figure 1: CH7025/CH7026 block diagram

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1.0 Pin-out

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CHRONTEL

V A V D
D N N N G A H E/
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C1 C3 C2 SO B CS

Rev. 1.1,
C2 3 EM _ D EM Q
Package Diagram

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12/3/2008
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P L DD C1 9 12 14

Figure 2: BGA Package

D L _ EM _ 0 D D

A D D
V X D
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7

D I 1 11 13

V G A V
N X M DD M ND G D D D D D D
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G A G
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CH7025/CH7026
CHRONTEL CH7025/CH7026

DE/CSB

H/WEB

DGND
DVDD
D[23]
D[22]
D[21]
D[20]
D[19]
D[18]
D[17]
D[16]

D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
V

69

61
70

62
74

68

66
67

65
73
72
71

64
63
79
80

78

76
77

75
HSO 1 60 D[8]
VSO 2 59 D[7]
CSYNC 3 58 D[6]
ATPG 4 57 D[5]
AS 5 56 D[4]
ResetB 6 55 D[3]
AGND 7 54 D[2]
AVDD 8 53 D[1]
GNDQ_MEM 9 52 D[0]
VDDQ_MEM
AGND
10
11
CH7025/CH7026 51
50
VDDIO
GCLK
AVDD 12 49 AVDD
GND_MEM 13 48 AGND
VDD_MEM 14 47 GND_MEM
NC 15 46 GND_MEM
NC 16 45 VDD_MEM
NC 17 44 VDD_MEM
VDDQ_MEM 18 43 NC
GNDQ_MEM 19 42 NC
NC 20 41 NC
40
21

39
22

26

28
25

27
23
24

30
31
32

36

38
29

35

37
33
34
AGND_PLL
DAC2

DAC1

DAC0

ISET

AVDD_PLL

XI
NC
NC
NC

AGND_DAC

AGND_DAC

AGND

XO
AVDD
SPD
SPC
NC
AVDD_DAC

AVDD_DAC

Figure 3: 80 Pin LQFP Package

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1.2 Pin Description

Table 1: Pin Name Description (BGA Package)

Pin # Type Symbol Description

A3, E4, B4, A4, In D[23:0] Data[0] through Data[23] Inputs
E5, B5, A5, D4, These pins accept the 24 data inputs from a digital video
D5, D6, A7, E6, port of a graphics controller. The swing is defined by
B7, A8, F6, B8, VDDIO.
B9, C9, C8, D9,
D8, E8, F7, E9
C2 In/Out V Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical
sync input for use with the input data. The amplitude will
be 0 to VDDIO.

When the SYO control bit is high, the device will output a
vertical sync pulse. The output is driven from the VDDIO
supply.
B3 In/Out H/WEB Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a
horizontal sync input for use with the input data. The
amplitude will be 0 to VDDIO.

When the SYO control bit is high, the device will output a
horizontal sync pulse. The output is driven from the
VDDIO supply.

It is also the WEB signal of CPU interface.

A2 In DE/CSB Data Input Indicator
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
It is also the CSB signal of CPU interface
The amplitude will be 0 to VDDIO.
D2 In AS Address select
F5 In ATPG ATPG Enable
(Internally pull-down)
This pin should be left open or pulled low with a 10k
resistor in the application. This pin configures the pre-
condition for scan chain and boundary scan test when high.
Otherwise it should be low. Voltage level is 0 to 3.3V.
C1 In ResetB Reset * Input
When this pin is low, the device is held in the hardware
reset condition. When this pin is high, reset is controlled
through the serial port.
K9 In/Out SPD Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial
port. External pull-up resister is required.
L9 In SPC Serial Port Clock Input
This pin functions as the clock pin of the serial port.
External pull-up resister is required.

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Pin # Type Symbol Description
L4 Out DAC0 CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
L3 Out DAC1 CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
L2 Out DAC2 CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
L5 In ISET Current Set Resistor Input
This pin sets the DAC current. A 1.2k Ω, 1% tolerance
resistor should be connected between this pin and
AGND_DAC using short and wide traces.
K7 In XI Crystal Input / External Input
For some situation of the slave mode, a parallel resonance
crystal (± 20 ppm) should be attached between this pin and
XO. However, an external 3.3V CMOS compatible clock
can drive the XI/FIN input.
K8 Out XO Crystal Output
For some situation of the slave mode, a parallel resonance
crystal (± 20 ppm) should be attached between this pin and
XI / FIN. However, if an external CMOS clock is attached
to XI/FIN, XO should be left open.
F9 In GCLK External Clock Inputs
The input is the clock signal input to the device for use with
the H, V, DE and D[23:0] data.
B1 Out VSO Vertical sync signal output
B2 Out HSO Horizontal sync signal output
A1 Out CSYNC Composite sync output
F8 Power VDDIO IO supply voltage (1.2-3.3V)
B6 Power DVDD Digital supply voltage (1.8V)
D1, F1, L7, G9 Power AVDD Analog supply voltage (2.5 – 3.3V)
K6 Power AVDD_PLL PLL supply voltage (1.8V)
K4 Power AVDD_DAC DAC power supply (2.5 – 3.3V)
E2, H1 Power VDDQ_MEM SDRAM output buffer supply voltage
(2.5V)
G2, J8, H6 Power VDD_MEM SDRAM device supply voltage (2.5V)
A6 Power DGND Digital supply ground
F4, F2, L6, G8 Power AGND Analog supply ground
K5 Power AGND_PLL PLL supply ground
K3 Power AGND_DAC DAC supply ground
E1, J1 Power GNDQ_MEM SDRAM output buffer supply ground
F3, H9, H8 Power GND_MEM SDRAM device supply ground

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Table 2: Pin Name Descriptions (LQFP80 Package)

Pin # Type Symbol Description

52 - 67 In D[23:0] Data[0] through Data[23] Inputs
70 - 77 These pins accept the 24 data inputs from a digital video port of a
graphics controller. The swing is defined by VDDIO.
79 In/Out V Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical sync input
for use with the input data. The amplitude will be 0 to VDDIO.

When the SYO control bit is high, the device will output a vertical
sync pulse. The output is driven from the VDDIO supply.
78 In/Out H/WEB Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a horizontal sync
input for use with the input data. The amplitude will be 0 to VDDIO.

When the SYO control bit is high, the device will output a horizontal
sync pulse. The output is driven from the VDDIO supply.

It is also the WEB signal of CPU interface.

80 In DE/CSB Data Input Indicator
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
CSB signal input of CPU interface
The amplitude will be 0 to VDDIO.
5 In AS Chip address select
0: 76h
1: 75h
4 In ATPG ATPG Enable
(Internally pull-down)
This pin should be left open or pulled low with a 10k resistor in the
application. This pin configures the pre-condition for scan chain and
boundary scan test when high. Otherwise it should be low. Voltage
level is 0 to 3.3V.
6 In ResetB Reset * Input
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through the serial
port.
38 In/Out SPD Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port.
External pull-up resister is required.
39 In SPC Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull-up
resister is required.
29 Out DAC0 CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
27 Out DAC1 CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
25 Out DAC2 CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
31 In ISET Current Set Resistor Input
This pin sets the DAC current. A 1.2k Ω, 1% tolerance resistor should

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CHRONTEL CH7025/CH7026
Pin # Type Symbol Description
be connected between this pin and AGND_DAC using short and wide
traces.
35 In XI Crystal Input / External Input
For some situation of the slave mode, a parallel resonance crystal (± 20
ppm) should be attached between this pin and XO. However, an
external 3.3V CMOS compatible clock can drive the XI/FIN input.
36 Out XO Crystal Output
For some situation of the slave mode, a parallel resonance crystal (± 20
ppm) should be attached between this pin and XI / FIN. However, if
an external CMOS clock is attached to XI/FIN, XO should be left
open.
50 In GCLK External Clock Inputs
The input is the clock signal input to the device for use with the H, V,
DE and D[23:0] data.
2 Out VSO Vertical sync signal output,
The amplitude of this pin is from 0 to AVDD
1 Out HSO Horizontal sync signal output,
The amplitude of this pin is from 0 to AVDD
3 Out CSYNC Composite sync output,
The amplitude of this pin is from 0 to AVDD
51 Power VDDIO IO supply voltage (1.2 – 3.3V)
69 Power DVDD Digital supply voltage (1.8V)
8, 12 Power AVDD Analog supply voltage(2.5 – 3.3V)
37, 49
33 Power AVDD_PLL PLL supply voltage(1.8V)
24, 28 Power AVDD_DAC DAC power supply(2.5 – 3.3V)
10 Power VDDQ_MEM SDRAM output buffer supply voltage(2.5V)
18
14, 44 Power VDD_MEM SDRAM device supply voltage(2.5V)
45
68 Power DGND Digital supply ground
7, 11, 34 Power AGND Analog supply ground
48
32 Power AGND_PLL PLL supply ground
26, 30 Power AGND_DAC DAC supply ground
9, 19 Power GNDQ_MEM SDRAM output buffer supply ground
13, 46, Power GND_MEM SDRAM device supply ground
47

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2.0 Package Dimensions

A1 Conrer A1 Conrer

9 8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8 9

A
A

B
B

C
C

D
D
D
E
E

A C F
F

G
G

H
H

J
J

K
K

L
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F
( Top View )
E
B
( Bottom View )

K
H I J
G

Figure 4: 80 Pin BGA Package

Table of Dimensions
No. of Leads SYMBOL
80 (5 X 6 mm) A B C D E F G H I J K
Milli- Min 0.22
6.00 5.00 5.00 0.50 4.00 0.50 0.30 0.60 0.30
meters Max 1.20 0.30

Notes:
1. All dimensions conform to JEDEC standard MO-216.

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CHRONTEL CH7025/CH7026

A
B
I

A B

C D J

LEAD
CO-PLANARITY
F E
.004 “
G
Figure 5: 80 Pin LQFP Package

Table of Dimensions
No. of Leads SYMBOL
80 (10 X 10 mm) A B C D E F G H I J
Milli- MIN 11.90 9.90 0.13 1.35 0.05 0.45 0.09 0°
0.40 1.00
meters MAX 12.10 10.10 0.23 1.45 0.15 0.75 0.20 7°

Notes:
1. Conforms to JEDEC standard JESD-30 MS-026D.
2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.
3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.

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CHRONTEL CH7025/CH7026
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at
any time without notice to improve and supply the best possible product and is not responsible and does not
assume any liability for misapplication or use outside the limits specified in this document. We provide no
warranty for the use of our products and assume no liability for errors contained in this document. The
customer should make sure that they have the most recent data sheet version. Customers should take
appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc.
respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such
rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as
directed can reasonably expect to result in personal injury or death.

ORDERING INFORMATION

Copy
Part Number Package Type Operating Temperature Range
Protection

CH7025B-GF 80TFBGA, Lead-free Macrovision™ Commercial : -20 to 70°C

CH7025B-GFI 80TFBGA, Lead-free Macrovision™ Industrial : -40 to 85°C

CH7025B-TF 80LQFP, Lead-free Macrovision™ Commercial : -20 to 70°C

CH7025B-TFI 80LQFP, Lead-free Macrovision™ Industrial : -40 to 85°C

CH7026B-GF 80TFBGA, Lead-free None Commercial : -20 to 70°C

CH7026B-GFI 80TFBGA, Lead-free None Industrial : -40 to 85°C

CH7026B-TF 80LQFP, Lead-free None Commercial : -20 to 70°C

CH7026B-TFI 80LQFP, Lead-free None Industrial : -40 to 85°C

Chrontel
Chrontel International Limited
129 Front Street, 5th floor,
Hamilton, Bermuda HM12
www.chrontel.com
E-mail: sales@chrontel.com
©2008 Chrontel All Rights Reserved.

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