4-Apr-24

CS 252: Computer Organization and

Architecture II

LECTURE 1
INSTRUCTION SET AND DESIGN OF
INSTRUCTION SET ARCHITECTURE (ISA)

Dr. E. A. Kalinga|CSE|CoICT| 1

Introduction
• Computer architecture is the design of
computers, which include:
—Their instruction sets,
—Hardware components, and
—System organization
• The architecture of a computer consists of
two essential parts:
—The instruction set architecture (ISA), and
—The hardware-system architecture (HSA)
Computer architecture =
Instruction set architecture + Machine organisation
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Introduction
• The instruction set architecture defines the
software/hardware interface that is visible
to the machine language level programmer.
• It includes:
i. The instruction set (i.e. the available operations)
ii. The instruction formats
iii.The available addressing techniques (Addressing
Modes)
iv.The format of the available data types
(representation of data)
v. Organization of storage: the operational register
set, memory (All programmer-accessible
registers in CPU)
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Introduction

• The hardware-system architecture (sometimes

referred to as the computer organization),
deals with the major hardware subsystems
of the computer, including:
—The CPU,
—The storage system and
—The input/output system.

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Architecture vs. Organization

• Computer organisation
— Computer are built using a number of components i.e. hardware
details transparent to a programmer: operational units and their
interconnections, peripheral interfaces, memory technology i.e.,
computer organization.
— Computer organization shows how exactly all the units
in the system are arranged and interconnected.
— Or Sometimes defined as the electrical circuitry of a computer
that is sufficient for completely describing the operation of the
hardware.
• Computer architecture
— Contrast of computer organization, computer architecture is the
science of integrating those components to achieve a level
of functionality and performance.
— Attributes (features) of a system visible to a programmer:
instruction set, data types, I/O mechanisms, addressing of memory

Instruction Set Vs. ISA

• Instruction Set: Is the entire collection of all
the instructions possible in a machine language,
i.e.
—The complete collection of instructions that are
understood by a CPU
—Machine Code
—Usually represented by Assembly Codes
• But the programmer’s view is composed of a
machine and assembly language
instruction set of the machine, along with
the machine resources that can be managed
with those instructions e.g. memory.

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Instruction Set Vs. ISA

• The collection of instruction set and resources
is referred as Instruction Set Architecture
(ISA).
• ISA is the architecture, i.e., the interface between
the hardware and the software that is visible to the
machine language level programmer
• Thus ISA include:
—Instruction Set (identified by operation codes performed)
—Instruction formats
—Representations of data
—Modes of addressing and accessing data
—Organization of storage: registers, memory (All
programmer-accessible registers in CPU)

Compiler Vs. Assembler

• A Compiler
—Translates a High Level Language (HLL),
which is architecture independent into
assembly language, which is architecture
dependent
• An Assembler
—Translates assembly language programs into
executable binary codes. That is into actual
machine instruction (machine language or
machine code)
• The collection of machine instructions for a
given machine is referred to as the Instruction
Set of that machine
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Compiler Vs. Assembler Cont…

Instruction Set
• Programs written in High-Level languages (by a
programmer) must be translated (by a compiler)
to an appropriate sequence of assembly
instructions (assembly language).
• Later, assembly language will be translated into
executable binary codes.
• Assembly language provides mnemonics for
machine language instructions which must be
encoded as a series of binary digits.

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Instruction Execution Cycle

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Instruction Execution Cycle Cont…

• Machine program that is stored in the machine memory is
executed instruction by instruction (Sequentially).
1. One by one instruction is fetched out of the computer
memory , temporarily stored in the Instruction
Register (IR)
2. Then the instruction will be decoded
3. Operand/operands will be fetched
4. Execution will take place
5. The result will be stored
6. Machine will be provided with information about where to
find the next instruction to fetch. That information is
stored in the Program Counter (PC) or sometimes
called Instruction Pointer (IP).
• While fetching the instruction, the control unit is
incrementing the PC to point to the next instruction

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Instruction Fetch

Address
Memory

Select next
Program Instruction
instruction
Counter
Increment PC
CPU to locate next
instruction.
Instruction
Register

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Elements of an Instruction (Instruction Fields)

• Encoding is broken into fields, each of which
specifies part of the total instruction
• Operation code (Opcode)
—Specifies the operation that is to be performed
• Operand fields: Specifies where to get the
source and destination operands. This include: -
—Source Operand reference
—Result Operand reference
• Next Instruction Reference
—Specifying where the next instruction to be executed
is located
—Program Counter (PC) register is implicitly used

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Simple Instruction Format

Opcode Field Source and Destination Field

Source Source Destination

Opcode Field Operand 1 Operand 2 Operand

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What must any instruction specify

• Either explicitly or implicitly, any instruction must
specify:-
—Which operation to perform
– Specified by the opcode e. g. ADD, LOAD, MOVE etc.
—Where to find the operand or operands
– Operands may be contained in: CPU registers, in main
memory, or in an Input/Output ports
—Where to put the result
– Result location may need to be explicitly or implicitly
mentioned in the opcode
—Where to find the next instruction
– Implicitly in the word following this instruction
• e. g. ADD a, b, c
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Instruction
Instruction in Higher Level programming language:
a=b+c
Note:
Operation is “add”; source operands are “b” and “c”;
destination operand is “a”.

Instruction in Assembly language (after passing a

compiler), depending on the computer can be:
Add a, b, c
or
Add b, c, a
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Instruction

Add b c a
Source Source Destination
Opcode Field Operand 1 Operand 2 Operand
(Operation Code)

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Revisiting CPU Details

• Levels of
Memory
Hierarchy

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Revisiting CPU Details

• CPU uses registers as its working space (temporarily
storage)
• Registers include:
—User visible registers:
– Accumulator (A)
– General-Purpose-Registers (GPR): Base, count and
data
– Data register (D7 – D0)
– Address Register (A7 – A0)
—Control and status registers
– Program counter or instruction pointer
– Instruction Register
– Status word register or flag register

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Status and Control Flag

Status flags are: (e.g. for 8086 µp)
—Carry flag (CF), Parity flag (PF), Auxiliary flag (AF),
Zero flag (ZF), Sign flag (SF) and Overflow flag (OF)
Control flags are:
—Trap flag (TF): allowing a single-step-mode,
executing one instruction at a time
—Interrupt flag (IF): For interrupt servicing
—Direction flag (DF) : direction in which the string
operation will occur. Decrementing and incrementing
the address
Control Flags Status Flag

TF DF IF OF SF ZF AF PF CF

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Classification of ISA
• The type of internal storage in the CPU is the most basic
differentiator
• Computers can be classified according to the structure and
function of the registers in the CPU
• Operands may be named explicitly or implicitly
1. Accumulator Architecture
— Have a limited number of data accumulator often just one, in
addition to the address register within the CPU
— In an accumulator architecture one operand is implicitly the
accumulator
— Called accumulators because they serve both as the source of an
operand and as a destination for the arithmetic instructions:
thus, they serve to accumulate data
— Also known as 1-address machine, which makes the machine to
have the advantage of being cheap
— Having one or limited number of accumulator in the CPU, an
accumulator machine is quite limited when evaluating arithmetic
evaluations with many terms and factors

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Classification of ISA
2. Stack Architecture
— The operands in a stack architecture are implicitly on top of
the stack
— LIFO (Last-In-First-Out) is used to describe the storage
mechanism
— Arithmetic operations use two operands from the top of the
stack, and the result is placed on the top of the stack
replacing the operand
— When the expression evaluation is complete, the result is
POPPED into a memory location to complete the process
— No-operand addresses need to be specified during an
arithmetic operation, the class is also known as a 0-address
machine

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Classification of ISA
3. General-Purpose Register (GPR) Architecture
— Have only explicit operands – either registers or memory
locations
— The explicit operands may be accessed directly from memory
or may need to be first loaded into temporary storage
— They can be divided into two classes
a) Load-store or Register-register architecture:
– can access memory only with LOAD and STORE instruction
– LOAD moves data from memory to a processor register
– STORE moves data from processor to memory
– ALU and Branch operations in Load-Store machines can
accept only operands located in processor registers,
and they must store the result in the processor
registers.
– Hence also called Register-register Architecture.

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Classification of ISA
b) Register-memory machine
– Locate operands and result in a combination of memory
and registers
– One operand or a result must be an accumulator or
general register (1½ address)
– Can access memory as part of any instruction
4. Memory-memory machine (2 or 3 address)
— They are 2 or 3 address machine depending upon whether one
of the operands location also serves as a result location
— Allows both the operand to reside in memory, i.e. keeps all the
operands in memory
— Not commonly used
• The explicit operand may be accessed directly from memory
or may need to be first loaded into temporary storage,
depending on the class of instruction and choice of specific
instruction
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Classification of ISA
• Most early machines used stack or accumulator
style architecture
• Every machine designed after 1980 uses a
load-store register architecture due to the
following reasons:
—Registers are fast than memory
—Registers are easier for a compiler to use and can be
used more effectively than other forms of internal
memory
—Registers can be used to hold variables

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Summary
• Stack architecture: Operands are implicitly on top
of the stack.
• Accumulator architecture: One operand is
implicitly in the accumulator (a register). Examples:
IBM 701, DEC PDP-8.
• General-purpose register (GPR) architecture:
Only explicit operands.
—Register-memory architecture (one operand in memory).
Examples: Motorola 68000, Intel 80386.
—Register-register (or load-store) architecture. Examples:
MIPS, DEC Alpha.
• Memory-memory architecture: All operands in
memory. Example: DEC VAX.

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Code Sequence Example

• Example: c = a + b
• It is assumed that a, b, and c all belong in
memory

Stack Accumulator Register-memory Load-store

Push a Load a Load R1, a Load R1, a

Push b Add b Add R1, b Load R2, b
Add Store c Store c, R1 Add R3, R1, R2
Pop c Store c, R3

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ISA Characteristics
• Four main characteristics:
1. Register Organization
— # of registers & their sizes
2. Memory Organization
— Address space - # of memory locations
— Addressability - # of bits stored @ each location
– Byte addressable and provide access for byte (8 bits),
half word (16 bits), and word (32 bits)
– Conversions of ordering the bytes within a word (Little
Endian, Big Endian)
– Addressing modes – defines how operand values are
obtained

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ISA Characteristics
3. Instruction Set
— List of opcodes (operations)– defines instructions
supported
— Instruction Formats (Encoding an instruction set)
– binary format for encoding instructions (R-format, I-
format, J-format)
– How the instructions are encoded into a binary
representation for execution by the CPU
— Type and size of operands: Integer, single/double precision
floating point, character
4. The role of the compiler
− From HLL to assembly language

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Memory Organization

• Each location of the Address Memory

memory has an 0 8 bits
address, which is an 1 8 bits
index into the array. 2 8 bits
3 8 bits
• The memory map on
4 8 bits
the right contains one
5 8 bits
byte (8 bits) in every
6 8 bits
location.
7 8 bits
• Byte addressing 8 8 bits
means the index • •
points to a byte of • •
memory. • •

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Memory Organization Cont…

Address Memory
• A word is a unit of transfer
0 8 bits
between processor and 8 bits
memory. 8 bits
• Words are aligned. 8 bits
4 8 bits
• Virtually all computer 8 bits
architectures today are 8 bits
byte-addressable and 8 bits
must, therefore, have a 8 8 bits
standard for storing 8 bits

information requiring more 8 bits

8 bits
than a single byte.

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Types of Instruction Sets (Classes)

1) Data movement instructions:
— Moves data from:
– Memory to memory e. g. MOV A, B
– Memory to CPU e. g. MOV R1, Addr
– Constant to CPU e. g. MOV R1,455
– CPU to output e. g. STORE (R1), A2
– Input to CPU e. g. LOAD R1, KBD
— The source of data may be an input port, memory, a
register within the CPU, or a constant that is part of
instruction
— The destination may be an output port, memory or a CPU
registers
— Condition flags are not affected

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Types of Instruction Sets (Classes)

2) ALU (Arithmetic and Logic) instructions:
— Accepts one or more operands and produces a result
— Performs all arithmetic operations such as : addition,
subtraction, multiplication, division and logic operations
such as AND, OR, XOR, NOT etc.
— Operands and results of ALU are located in registers or in
memory
— Other operations used are Increment (a++), decrement (a-
-), negate (-a), shift and rotate operations
— Generates some side effects to condition flags to
indicate the status of a result

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Types of Instruction Sets (Classes)

3)Branch Instruction (change the flow of
Control)
— Program flow is being controlled by the program counter (PC)
or instruction Pointer (IP) which points to the next instruction to
be executed
— Changes the flow of control. Initiates conditional and
unconditional: jumps, calls, returns and restarts
— Branch or jump instructions are used
— Condition flags are not affected by this group of instruction
• Unconditional branch perform the specified operation on register
PC e. g. jump, goto
• Conditional branch instructions test various settings of flags
and branch or not according to their settings. The bit or bits
that describe the condition are stored in a register variously called
the processor status word (PSW), the condition code (CC)
register, or status register.
• Most common condition-code bits are: zero (Z), overflow, Carry (C)
etc. which shows the last result condition of an arithmetic
operation
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Branch Instructions (Control flow change)

• During normal program execution, the PC is
incremented during the instruction fetch to point to
the next instruction
• A transfer of a control or a branch to an instruction
other than the next one in sequence require
computation of a TARGET ADDRESS, which is the
address to which control is to be transferred
• A target address is specified in a branch or
jump instruction
• The target address is loaded into the PC,
replacing the address stored there

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Branch Instructions (Control flow change)

• Branch instruction loads new value in PC
• Conditional branch instructions branches
depending on the tested value settings in flags
• Generally, we can distinguish 4 different types
of control flow change
—Conditional Branch
—Jumps (Unconditional Branches)
—Procedure Calls
—Procedure Returns
• Branches use PC-Relative addressing to
specify their targets (i.e. displacement is added
to the PC)

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Address of the Next Instruction

• During normal program execution, PC is
incremented implicitly during the instruction
fetch
• Assuming that, we have an 8-bit memory
system, i.e., one location of a memory has only
8 bit (byte addressable memory system)
• Examples:
—For an 8-bit machine (i.e. 8 bits address bus from
the CPU), the increment will be ((PC) + 1)
—For a 32-bit machine (i.e. 32 bits address bus from
the CPU), the increment will be ((PC) + 4)), PC is
incremented to point to the next 4 bytes

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Target Address for Conditional Branching

• During branching to an instruction other than the
next instruction in sequence, target address has to
be calculated and loaded into the PC
• The addressing mode to be used is Relative AM to
specify the target address
Hence: Effective Address (EA) =(PC) + Displacement
Here the value of the PC () will be the newly incremented PC ,
base value
i.e. PC = (PC + 1) for an 8-bit machine and
PC = (PC + 4) for a 32-bit machine
Displacement will be the value given within the instruction itself
e.g. beq r1, r2, offset_value

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Target Address for Unconditional Branching

• The coding of the instruction itself in IR will be

used in finding the target address. This is done by:
—replacing the lower 28 bits of PC with the lower
26 bits of the IR coding instruction shifted left by
two (2)
—4 msb (upper 4 bits) of the PC will remain
unchanged
—The shift is accomplished by simply
concatenating “00”

PC = PC[31-28]||(IR[25-0]<<2);

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Branch Instructions (Control flow change)

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Data Sizes
A byte is composed of 8 bits. Two nibbles makes
up a byte.Words are composed of bytes as
shown: -
Bit  1 Bit length, Either ‘0’ or ‘1’
Nibble  4 bits length, or a half byte
Byte  8 bits length
Half word  16 bits length (2 bytes)
Word  32 bits length (4 bytes)
Double Word  64 bits length (8 bytes)
Quad words  128 bits length (16 bytes)

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Memory Organization
• Instruction Set to be discussed are byte
addressed and provide access for byte,
half word, word or double word

• The main memory can be viewed as a

large, single-dimension array of memory
locations, each location with a byte size.

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Access Paths to Operands : (Addressing Modes)

• To access an operand in memory, the CPU must

first generate an address, which it then issues to
the memory subsystem
• Addressing Modes dictates how architectures
specify the address of an object or data they
will access
• The address generated is known as an effective
address (EA)
• Some of the addressing modes are:
—Immediate addressing mode;
– involving assigning constants, i.e. operand is part of instruction
Example: ADD 5 //A ← A+5

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Access Paths to Operands : (Addressing Modes)

• Some of the addressing modes are:
—Direct addressing mode; Instruction contains address of
operand.
– i.e. the instruction contains the memory address of the operand
– Example ADD C //C is the address of memory with operand
—Indirect addressing mode;
– Instruction contains address of address of operand
– Eg ADD (C) //C has the memory address which has the address of
the operand
—Register Direct addressing mode;
– register contains operands
– Example ADD R
—Register Indirect addressing mode;
– Register contains the address of operands. ADD (R)

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Access Paths to Operands : (Addressing Modes)

• Some of the addressing modes are (cont.):
—Displacement (Register Based) addressing mode;
– Address of operand = [Register] + constant
– E.g. ADD 4(R2) //4 is the displacement, R2 is the number of
a register with base value
—Indexed addressing mode; Useful in arrays addressing
– Add R3, (R1 + R2);
– R1 base register, R2 index amount
—Relative Addressing mode;
– Base value is in PC register. E.g. LOAD 4(PC)
– Address of operand = (PC) + constant
• Addressing modes:
—have the ability to significantly reduce instruction counts
—add to the complexity of building a machine and may increase
the average CPI (clock cycles per instruction) of machine that
implement those modes.
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Addressing Modes

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Instruction Set Design

• It is the most controversial area of computer design
• It is the programmer’s means of controlling the
machine
• Factors to be considered are:
— How many and what type of operation should these operations be?
— What type of data should instructions act upon?
— What instruction formats should be used (Length of op code field,
Number of addresses)
– The architect is more interested in code size than performance will
pick variable encoding
– And the one more interested in performance than code size will
pick fixed encoding
— How many registers should be included in the CPU?
– Which operations can be performed on which registers?
— What type of addressing modes should be supported for specifying
operand addresses?

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Register Transfer Notation (RTN)

• Register Transfer Notation (RTN) are used to
specify movement of data among registers and
memory cells in a computer
e.g. ADD R1, R2, R3 R[R1]  R[R2] + R[R3]
IR  M[PC] : PC  PC + 4
PC  31 .. 0: 32-bit register named PC
Load R1, 24(R2) R[R1]  M[24 + R[R2]]

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Register Transfer Notation (RTN)

 Register Transfer: register on LHS stores value from RHS
[] Word index: selects word or range from a named memory
 Bit index: selects bit or bit range from named register
 If-then: true condition on left yields value and/or action on right
# Concatenation: bits on right appended to bits on left
: Parallel separators: actions or evaluations carried out
simultaneously
; Sequential separator: RHS evaluated and/or performed after LHS
{} Operation modifier: information about proceeding operation, e.g
arithmetic type
() Operation or value grouping: arbitrary nesting; used with operators
or separators
=  <  >  Comparison operators: produce 1 or 0 (true or false) logic values
+ -   Arithmetic operators: also   ,   , and mod
     Logical operators: and, or, not, exclusive or, equivalence

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