Fully Integrated Electronic Stability Control/electronic Stability Program Braking Chip

NXP Semiconductors Document Number: SC900719
Data sheet: Advance Information Rev. 6.0, 10/2016
Fully integrated electronic stability

control/electronic stability program 900719
braking chip
The 900719 is a SMARTMOS fully integrated analog with mixed-signal IC Automotive braking chip
intended for automotive electronic stability controllers (ESC/ESP).
A DC–DC switching regulator and multiple linear voltage regulators are available
to supply an MCU Core, I/Os, and external 5.0 V device. The 900719 has eight
current regulated valve drivers, four digital valve drivers, and a safe FET driver
for solenoid control. The 900719 also contains four configurable wheel speed
sensor interfaces and a half-bridge pre-driver for pump motor control. Alongside
this main functionality, the 900719 has a warning lamp driver and a K-line
transceiver. The digital I/O pins can be configured for both 5.0 V and 3.3 V levels
for easy connection to any microprocessor. The 900719 uses standard 32-bit AF SUFFIX (PB-FREE)
SPI protocol for communication. The built-in enhanced high speed CAN interface 98ASA00553D
fulfills the ISO11898-2 and -5 standards. Local and bus failure diagnostics, 100-PIN LQFP EXPOSED PaD
protection, and fail-safe operation mode are provided. The 900719, including
enhanced safety features, fits for high safety integrity level applications. Applications
Features • Electronic stability control
• Anti-braking system
• Twelve valve controls: four digital and eight current regulated
• High-side pre-driver for valve protection
• Four wheel speed sensor interfaces
• Pump motor pre-driver up to 16 kHz PWM with active recirculation control
• Power supply for MCU core, I/Os, and external 5.0 V
• Dual high-speed CAN interface without external choke
• 10-bit analog-to-digital converter
• 32-bit SPI interface with challenger watchdog
SC900719
VCCA
VBAT1 VCCA_SUP
VPWR VCCA_SW
CP
VPRE_SUP VCC5
VPRE_D VCC3P3
VBAT2 VCC5_EXT
VPRE_G
VPRE_S RST
PD_D SO
PD_G SI
CSB
SCLK
PD_S
TXD 2 MCU
M
FRW_G RXD 2
VBAT1 TxK
RxK
HD_D WSAI
4
WSOx
HD_G
VSO_IN
HD_S VSO
HSD1 3.3V(Debug mode)
LSD1 DEBUG
Solenoid LSD2
LSD3 WSx_SUP 2
Coil
LSD4 WSx_HS 4
LSD5
LSD6
IGN Wheel
HSD2
speed
LSD7 CANH 2
LSD8 VBAT1 Sensor
Solenoid LSD9 CANL 2
Coil LSD10
LSD11 ISOK
LSD12 GND_A GND_D GND_P WLDx 2
Figure 1. 900719 simplified application diagram
* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.
© 2016 NXP Semiconductors B.V.
Table of Contents
1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Digital I/Os characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Valve characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 Current references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4 Pre-linear voltage regulator VPRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5 DC/DC buck converter VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.6 3.3 V linear regulator VCC3P3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.7 5.0 V linear regulator VCC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.8 5.0 V external linear regulator VCC5_EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.9 Dual 5.0 V linear regulators VCCx_CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.10 Internal voltage regulators VINT_A and VINT_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.11 DOSV digital output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.12 Dual CAN interfaces (CAN1 and CAN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.13 Pump motor pre-driver with active re-circulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.14 High-side pre-driver for valve’s safe switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.15 Low-side switches for valves control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.16 Wheel speed sensor interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.17 Vehicle speed output VSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.18 Dual warning lamp pre-drivers WLDx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.19 Analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.20 ISO K-line and second vehicle speed output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.21 32-bit SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.22 Built-in self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
900719
NXP Semiconductors 2
1 Orderable parts
This section describes the part numbers available to be purchased along with their differences.
Table 1. Orderable part variations

VCCA output
Part number (1) Temperature (TA) Package CAN wake-up
voltage
SC900719AAF 1.25 V Yes
SC900719BAF 1.20 V Yes

–40 ° to 125 °C LQFP100-EP
SC900719CAF 1.30 V Yes
SC900719DAF 3.30 V Yes
Notes:
1. To order parts in tape and reel, add the R2 suffix to the part number.
900719
3 NXP Semiconductors
2 Internal block diagram
VPWR2
VPWR1
CP
Charge Pump Band
Gap 2 Supervision
VPRE_SUP
Pre-linear
VPRE_D
VPRE_G Regulator
VPRE_S Band Die Temperature
Gap 1 Warning
VINT_A Internal Regulators
VINT_D DOSV
GND_D2
5.0 V Linear DEBUG
Regulator Internal Functions
VCC5 IGN
RSTB
5.0 V Linear BIST

IREF
Regulator IREF_REDUNT
VCC5_EXT
3.3 V Linear 32-bit SPI 4

Regulator Interface SCLK, CSB, SI, SO
VCC3P3
2
WSxx_SUP
VCCA_SUP 1.2 V to 3.3 V Wheel Speed WSAI

Sensor Interface 4
VCCA_SW DC/DC Buck WSx_HS
VCCA Converter ² (x4Ch) 4

WSOx
PD_D Motor Pump Vehicle Speed

VSO1
PD_G
VBOOT Pre-driver with Output 1
PD_S
FRW_G
Booststrap Logic VSO_IN
with
L-Bist & K-Line Interface RXK
HD_D
HD_G A-Bist or
HD_S HS Pre-driver TXK
Vehicle Speed ISO_VSO2
Output 2
LSDx
Digital Valves 5.0 V Supply for VPRE_CAN
4 (x4Ch) 300 mΩ
LSDx CAN (x2Ch) 2
VCCx_CAN
HSDx (300 mΩ) & 2

RXDx
8 LSDx (200/300 mΩ) CAN High-speed 2
LSDx TXDx
Current Regulated
Interfaces 2
CANx_H
Valves
HSDx 2 (x2Ch) 2
(x8Ch) CANx_L
LS Warning Lamp
3
Pre-driver 2 WLDx
ADINx 10-bit ADC (x2Ch)
(x3Ch)
GND_A GND_P GND_D1
Figure 2. 900719 simplified internal block diagram
900719
3 Pin connections
3.1 Pinout diagram
IREF_REDUNT
VCCA_SUP
WS12_SUP
VPRE_SUP
WS34_SUP
VCC5_EXT
VCCA_SW
WS1_HS
WS2_HS
WS4_HS
WS3_HS
VPRE_G
GND_D1
GND_D1
VPRE_D
VPRE_S
VCC3P3
VINT_D
VPWR1
VINT_A
GND_A
GND_A
VCCA
VCC5
IREF
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
HD_S 1 75 VPWR2
CP 2 74 NC
HD_D 3 73 ADIN3
HD_G 4 72 ADIN2
PD_S 5 71 ADIN1
VBOOT 6 70 ISO_VSO2
PD_D 7 69 WLD2
FRW_G 8 68 WLD1
PD_G 9 67 VSO
GND_P 10 66 GND_P
LSD1 11 65 LSD12
HSD1 12 64 HSD2
LSD2 13 63 LSD11
HSD1 14 62 HSD2
LSD3 15 61 LSD10
HSD1 16 60 HSD2
LSD4 17 59 LSD9
HSD1 18 58 HSD2
LSD5 19 57 LSD8
NC 20 56 NC
LSD6 21 55 LSD7
GND_P 22 54 GND_P
RXK 23 53 NC
RSTB 24 52 IGN
BIST 25 51 NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
WSO1
WSO2
WSO3
WSO4
CAN1_l
RXD1
RXD2
GND_D2
CAN2_L
TXD1
TXD2
SO
WSAI
DOSV
DEBUG
SI
CAN2_H
VCC2_CAN
VPRE_CAN
VCC1_CAN
CAN1_H
VSO_IN
CSB
SCLK
TXK
Figure 3. 900719 pinout diagram
900719
3.2 Pin definitions
Table 2. 900719 pin definitions

Pin number Pin name Pin function Definition Note
1 HD_S A_Out Source feedback high-side FET for valve’s fail-safe switch
(2)
2 CP A_Out Tank capacitor for internal charge pump
3 HD_D A_Out Drain feedback high-side FET for valve’s fail-safe switch
4 HD_G A_Out Gate control high-side FET for valve’s fail-safe switch
5 PD_S A_Out Source feedback high-side FET for pump motor

6 VBOOT A_Out Bootstrap capacitor for pump motor (2)
7 PD_D A_Out Drain feedback high-side FET for pump motor
8 FRW_G A_Out Gate control low-side FET for active recirculation pump motor
9 PD_G A_Out Gate control high-side FET for pump motor
10 GND_P GND Power ground
11 LSD1 A_Out Low-side FET for digital valve
12, 14, 16, 18 HSD1 A_In High-side FET for left valves (3)
13 LSD2 A_Out Low-side FET for digital/current regulated valve

20, 51, 53, 56, 74 NC NC These pins are shorted to ground.

22 GND_P GND Power ground
23 RXK D_Out ISO K-line receiver
24 RSTB D_IO MCU reset (4)
25 BIST D_Out BIST monitoring output
26 SO D_Out SPI data to MCU
27 WSAI D_Out Type III sensor additional information
28 WSO1 D_Out Sensor output for RR (right rear)
29 WSO2 D_Out Sensor output for LR (left rear)
30 WSO3 D_Out Sensor output for RF (right front)

31 WSO4 D_Out Sensor output for LF (left front)
32 RXD1 D_Out CAN 1 receiver
33 RXD2 D_Out CAN 2 receiver
34 GND_D2 GND Digital ground 2 for DOSV voltage monitoring
35 DOSV A_In Digital output voltage supply
36 CAN2_L A_IO CAN 2 bus
37 CAN2_H A_IO CAN 2 bus
38 VCC2_CAN A_Out CAN 2 transceiver supply
39 VPRE_CAN A_In CAN transceivers pre-regulator supply
40 VCC1_CAN A_Out CAN 1 transceiver supply
900719
Table 2. 900719 pin definitions (continued)
41 CAN1_H A_IO CAN 1 bus
42 CAN1_L A_IO CAN 1 bus
43 TXD1 D_In CAN 1 transceiver
44 TXD2 D_In CAN 2 transceiver
45 VSO_IN D_In Vehicle speed input
46 DEBUG D-In Watchdog disable input
47 CSB D-In SPI chip select

48 SI D-In SPI data from MCU
49 SCLK D-In SPI clock
50 TXK D-In ISO K-line transceiver
52 IGN A_In Ignition
54, 66 GND_P GND Power ground

58, 60, 62, 64 HSD2 A_In High-side FET for right valves (3)

67 VSO A_Out Vehicle speed output 1

68 WLD1 A_Out Warning lamp pre-driver 1
69 WLD2 A_Out Warning lamp pre-driver 2
70 ISO_VSO2 A_IO ISO K-line or vehicle speed output 2
71 ADIN1 A_In ADC input

75 VPWR2 SUPPLY Power supply (5)
76 WS34_SUP A_In Supply for wheel speed sensors 3 and 4
77 WS3_HS A_In Sensor 3 high-side supply
79, 81 GND_D1 GND Digital ground

(2)
80 VINT_D A_Out Internal supply for digital core
(2)
82 VINT_A A_Out Internal supply for analog core
83 IREF_REDUNT A_Out Redundant current reference
84, 85 GND_A GND Analog ground
86 IREF A_Out Current reference
87 VCC5 A_Out 5.0 V supply
88 VCC3P3 A_Out 3.3 V supply
89 VCC5_EXT A_Out 5.0 V supply for external usage
900719
Table 2. 900719 pin definitions (continued)
90 VPRE_SUP A_In Current limitation for VPRE supply
91 VPRE_D A_In Drain feedback high-side FET for VPRE supply
92 VPRE_S A_Out Source feedback high-side FET for VPRE supply
93 VPRE_G A_Out Gate control high-side FET for VPRE supply
94 VCCA A_Out Selectable VCCA supply
95 VCCA_SW A_Out DC/DC converter switch
96 VCCA_SUP A_In DC/DC converter supply
99 WS12_SUP A_In Supply for wheel speed sensors 1 and 2
100 VPWR1 SUPPLY Power supply (5)
(6)
EP GND_P GND Power ground
Notes:
2. 220 nF X7R capacitor is used
3. 22 nF X7R capacitor is used per HSDx terminal (total max. 100 nF)
4. External pull-up resistor is connected to DOSV (> 3.3 kΩ for 3.3 V and > 4.7 kΩ for 5.0 V).
5. To be connected through a reverse diode
6. The exposed pad (EP) is connected to the die substrate.
900719
4 General product characteristics
4.1 Maximum ratings
Table 3. Maximum ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol Description (rating) Min. Max. Unit Notes
Supply
VPWR VPWR1, 2 –0.3 40 V
DOSV DOSV –0.3 7.0 V
GND_A GND_A –0.3 0.3 V

GND_Dx GND_D1, 2 –0.3 0.3 V
GND_P GND_P –0.3 0.3 V
Internal function
VINT_A VINT_VA –0.3 3.0 V
VINT_D VINT_D –0.3 3.0 V
IREF IREF –0.3 3.0 V
IREF_REDUNT IREF_REDUNT –0.3 3.0 V
Charge pump
–0.3 or
CP CP VPWR – VPWR + 15 V
0.3 V
High-side pre-driver for valves’s safe switch

(7)
HD_G HD_G –20 55 or VCP V
HD_S HD_S –0.3 40 V
HD_D HD_D –0.3 40 V
Motor pump pre-driver
55 V or (7)
PD_G PD_G –20 V
VBOOT
PD_S PD_S –20 40 V
PD_D PD_D –20 40 V
VBOOT VBOOT –20 PD_S + 15 V
FRW_G FRW_G –20 40 V
Reset/debug/IRQ/ignition
RSTB RSTB –0.3 7.0 V
DEBUG DEBUG –0.3 7.0 V
BIST BIST –0.3 7.0 V

IGN IGN –2.0 40 V
Notes:
7. 55 V in sleep mode, VCP in operation.
900719
Table 3. Maximum ratings (continued)
to the device.
K-line / VSO
ISO_VSO2 ISO_VSO2 –10 mA 40 V
RXK RXK –0.3 DOSV +0.3 V
TXK TXK –0.3 7.0 V
SPI
SO SO –0.3 DOSV +0.3 V
SI SI –0.3 7.0 V
CSB CSB –0.3 7.0 V

SCLK SCLK –0.3 7.0 V
Wheel speed sensor interface
WSOx WSO1, 2, 3, 4 –0.3 DOSV +0.3 V
WSAI WSAI –0.3 DOSV +0.3 V
WSxx_SUP WS12_SUP, WS34_SUP –0.3 40 V
WSx_HS WS1_HS, WS2_HS, WS3_HS, WS4_HS –0.3 40 V
VSO_IN VSO_IN –0.3 7.0 V
VSO VSO –10 mA 40 V
Valves low/high-side driver
LSDx LSD1, 6, 7, 12 –0.3 VCL_LSD V

LSDx LAD2, 3, 4, 5, 8, 9, 10, 11 –0.3 30 V
HSDx HSD1, 2 –0.3 30 V
Warning lamp pre-drivers
WLDx WLD1, 2 –10 mA 40 V
CAN interface
VPRE_CAN VPRE_CAN –0.3 40 V
VCCx_CAN VCC1_CAN, VCC2_CAN –0.3 7.0 V
RXDx RXD1, RXD2 –0.3 DOSV +0.3 V
TXDx TXD1, TXD2 –0.3 7.0 V
CANx_L CAN1_L, CAN2_L –27 40 V
CANx_H CAN1_H, CAN2_H –27 40 V
Analog to digital converter
ADINx ADIN1, 2, 3 –0.3 7.0 V
900719
to the device.
Power supply module

VCC3P3 VCC3P3 –0.3 5.0 V
VCC5 VCC5 –0.3 7.0 V
VCC5_EXE VCC5_EXE –2.0 40 V

VPRE_SUP VSUP_SUP –0.3 40 V
VPRE_D VPRE_D –0.3 40 V
VPRE_G VPRE_G –0.3 40 V
VPRE_S VPRE_S –0.3 40 V
VCCA_SUP VCCA_SUP –0.3 40 V
VCCA VCCA –0.3 5.0 V

VCCA_SW VCCA_SW –2.0 40 V
Current
LSDx LSDx current –5.0 (8) 5.0 (9) A
RSTB, SI, CSB,

DEBUG, SCLK,
Digital pin current in clamping mode –10 10 mA
VSO_IN, TxDx,
TxK, ADINx
ADINx Digital pin current in clamping mode –1.5 1.5 mA
Energy capability
(10)
LSD1, 6, 7, 12 LSD1,6,7,12 energy capability in clamping mode – 40 mJ
ESD protection
Human body model

• Local pins –2.0 2.0
(11)
ESD(HBM) • Global pins: VPWR, WSx_HS, VSO, IGN, WLDx, ISO, CANx_H, CANx_L, –6.0 6.0 kV
VCC5_EXT, WS12_SUP, WS34_SUP, HD_D, PD_D, LSDx, HSDx,
VCCA_SUP, VPRE_SUP and VPRE_D
Charged device model

(11)
ESD(CDM) • All pins –500 500 V
• Corner pins –750 750
ESD gun
Gun test (330 Ω/150 pF) on CANx_L, CANx_H, VCC5_EXT, WSx_HS, LSDx, (12)
VESD_GUN1 –8.0 8.0 kV
HSDx, IGN, WLDx, VBAT1/2
Unpowered ESD gun test (330 Ω/150 pF) on CANx_L, CANx_H, VCC5_EXT, (12)
VESD_GUN2 –15.0 15.0 kV
WSx_HS, LSDx, HSDx, IGN, WLDx, VBAT1/2
(12)
VESD_GUN3 Unpowered ESD gun test (2.0 kΩ/150 pF) on CANx_L CANx_H –8.0 8.0 kV
900719
to the device.
Unpowered ESD gun test (2.0 kΩ/150 pF) on VCC5_EXT, WSx_HS, LSDx, (12)
HSDx, IGN, WLDx, VBAT1/2
VESD_GUN5 Powered ESD gun test (2.0 kΩ/330 pF) on CANx_L CANx_H –8.0 8.0 kV (12)
Powered ESD gun test (2.0 kΩ/330 pF) on VCC5_EXT, WSx_HS, LSDx, HSDx, (12)
IGN, WLDx, VBAT1/2
(12)
VESD_GUN7 Unpowered ESD gun test (330 Ω/330 pF) on CANx_L CANx_H –8.0 8.0 kV
Powered ESD gun test (330 Ω/330 pF) on CANx_L CANx_H, VCC5_EXT, (12)
WSx_HS, HSDx, IGN, WLDx, VBAT1/2
Notes:
8. Transient current (≤ 5.0 ms)
9. Continuous current in on-state
10. With 20 mH inductive load at TJ = 125 °C in initial (LSD2, 3, 4, 5, 8, 9, 10, 11 have high-side FET freewheeling)
11. The disturbances are referred to GNDx for global pins
12. Based on IEC 61000-4-2 test setup and Figure 48 typical application schematic
4.2 Thermal characteristics
Table 4. Thermal ratings

Exceeding these ratings may cause a malfunction or permanent damage to the device.
Thermal ratings
Operating temperature
(13)
TJ • Continuous –40 150 °C
(14)
• Transient –40 195
TA Operational ambient temperature –40 125 °C

TSTG Storage temperature –65 150 °C
RΘJC (15)
Thermal resistance, junction to case (package exposed pad) – 2.0 °C/W
(16)
TPPRT Peak package reflow temperature during reflow – 260 °C
MSL Moisture sensitivity level – 3
Notes:
13. The total device lifetime at a junction temperature of 150 °C is guaranteed for 1000 hours.
14. Limited time 100 hours with 175 °C in the center of die and 195 °C in the center of valves drivers.
15. Junction-to-case at the bottom of the package is based on simulation without any interface resistance.
16. Lead soldering temperature limit is for 10 seconds maximum duration. Lead soldering can be done twice. Device must be delivered in dry pack.
900719
4.3 Operating conditions
This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted.
Table 5. Operating conditions

to the device.
Symbol Ratings Min. Max. Unit Notes
VPWR Functional operating supply voltage range (full performance) 6.0 20 V
VPWR_EXTENDED (17), (18)

Extended supply voltage range VPWR_SLEEP 40 V
SPI
fSPI SPI frequency range 0.5 10 MHz
VPWR supply current consumptions
IVPWR Operating mode 20 60 mA
IVPWR(SLEEP) Sleep mode, measured at VPWR = 12 V – 50 μA
Leakage currents for the functions connected to VPWR (19)

(20)
IWLDX(SLEEP) Warning lamp sleep mode, measured at 12 V – 10 μA
IVSO(SLEEP) Vehicle speed output, measured at 12 V – 10 μA

IPD_D(SLEEP) Pump motor sleep mode, measured at 12 V – 10 μA
IHD_D(SLEEP) Valve’s safe switch sleep mode, measured at 12 V – 10 μA

(21)
IWSXX_SUP(SLEEP) WSxx_SUP sleep mode, measured at 12 V – 5.0 μA
IISO_VSO2(SLEEP) ISO_VSO2 sleep mode, measured at 12 V – 10 μA
Notes:
17. Reduced performance: the device is functional, but the parameter is not guaranteed
18. Refer to power-down configurable section
19. Absolute leakage current can be limited with an external pull-up resistor.
20. 20 μA total for WLD1 and WLD2
21. 10 μA total for WS12_SUP and WS34_SUP
900719
4.4 Digital I/Os characteristics
Table 6. Thermal ratings

VPWR = 6.0 V to 20 V, DOSV = 3.0 V to 5.5 V, TJ = –40 °C to 150 °C, unless otherwise specified.
Symbol Ratings Min. Max. Unit Notes
Digital inputs
Input high voltage

VIH_x • RSTB, SI, CSB, DEBUG, SCLK, VSO_IN, TXDx, TXK, ADIN1, ADIN2, – 2.0 V
ADIN3
Input low voltage

VIL_x • RSTB, SI, CSB, DEBUG, SCLK, VSO_IN, TXDx, TXK, ADIN1, ADIN2, 0.8 – V
ADIN3
Input voltage threshold hysteresis

VHYS_x • RSTB, SI, CSB, DEBUG, SCLK, VSO_IN, TXDx, TXK, ADIN1, ADIN2, 100 – mV
ADIN3
Input pull-down current, with VOUTPUT = 0.8 V

IPD_x 5.0 25 μA
• VSO_IN, SI, SCLK
Input pull-up current, with VINPUT = 2.0 V

IPU_x 5.0 25 μA
• CSB, TXD, TXK
Input pull-down resistor

RPD_x 90 410 kΩ
• RSTB, IGN, DEBUG
Input pull-down resistor for ADINx (22)

RADIN_x 90 410 kΩ
• ADIN1, ADIN2, ADIN3
CIN Input capacitance for all digital inputs – 12 pF
Digital outputs
Output high voltage, with –1.0 mA

VOH_x 0.8 x DOSV – V
• SO, WSOx, WSAI, RXDx, RXK, BIST
Output low voltage, with –1.0 mA

VOL_x – 0.4 V
• SO, WSOx, WSAI, RXDx, RXK, BIST
ISO So tri-state leakage current –10 10 μA
VOL_RSTB RSTB low voltage, with 1.0 mA – 0.4 V
Notes:
22. No pull-down by default. The pull-down is enabled if ADINx bit = 0.
4.5 Valve characteristics
Table 7. Valve electrical characteristic

TA = 20 °C
Value
Solenoid for valves
Min. Typ. Max.
3.1 mΩ 3.5 Ω 5.6 Ω

Current regulated valve
1.0 mH 5.0 mH 10 mH
Digital valve 3.95 Ω 4.15 Ω 4.35 Ω
900719
5 General description
5.1 Block diagram
Motor Eight regulated valves

Safe FET
pump driver low-side & high-side
Four digital valves Four wheel Two vehicle

low-side with PWM speed sensors speed outputs
Regulators
Two warning
K-line VPRE, VCC5, VCC5_EXT,
lamp drivers
VCC3P3, VCCA. VCAN
Three channel 32-bit SPI interface Two CAN

L-BIST, A-BIST
ADC inputs with CRC interfaces
Supervision
Figure 4. Functional block diagram
5.2 Functional description

The 900719 is a fully integrated electronic stability controller designed for use in harsh automotive environments. Multiple linear LDO
regulators and a buck switching regulator are available. A 5.0 V regulator is also available to supply external devices. The 900719 has
eight current regulated valve drivers, four digital valve drivers, and a safe FET driver for solenoid control. In addition, the 900719 contains
four configurable wheel speed sensor interfaces and a half-bridge pre-driver for pump motor control. Alongside this main functionality, the
900719 has a warning lamp driver and a K-line transceiver. The 900719 contains an internal charge pump, allowing the high-side drivers
to use inexpensive N-channel MOSFETs. The digital I/O pins can be configured for both 5.0 V and 3.3 V levels for easy connection to any
microprocessor. The 900719 uses standard 32-bit SPI protocol for communication.The built-in enhanced high-speed CAN interface fulfills
the ISO11898-2 and -5 standards. Local and bus failure diagnostics, protection, and fail-safe operation modes are provided. The 900719,
includes enhanced safety features, fits for high safety integrity level applications.
900719
5.3 Features
Table 8. Features
Module Features/ main parameters
• High-side fail-safe FET driver

• Load leakage detection
• High-side driver HD_G pin ground short protection (No effect to charge pump)
High-side driver
• Overcurrent shutdown with programmable threshold and filter time
• Programmable gate turn-off current
• HSD overvoltage shutdown
• Pump motor pre-driver

• Controlled by SPI command (8 bits)
• Frequency (100 Hz to 16 kHz) and configurable frequency and duty cycle
• Active load dump protection
• Overcurrent shutdown with programmable threshold and filter time
Motor pump driver • Driver capability > 50 mA
• Protection circuit VBOOT to FET source 15 V clamp diode) integrated
• PD_G pin short-to-ground protection or overtemperature shutdown
• Frequency modulation for EMC noise reduction
• Modulation band ±7.5 % max. and selectable modulation speed 1/8 to 1/64
• Gate driver for an active free-wheeling external LS FET
• Low-side and high-side diver for current regulation control valve

• Low-side RDS(on) = 300 mΩ at TJ = 150 °C for LSD 2.5.8.11
• Low-side RDS(on) = 200 mΩ at TJ = 150 °C for LSD 3.4.9.10
• High-side RDS(on) =300 mΩ at TJ = 150 °C
• Open load and low-side FET drain short-to-ground detection in off-state
• VDS state monitoring
• Overcurrent shutdown
• Overtemperature shutdown
• Current regulation error flag
• Control range 50 mA to 2.25 A
Low-side and high-side solenoid • Selectable PI controller integrated
driver (8 x channels) • Regulated current accuracy for average current
• 0.05 A ≤ Target current ≤ 0.25 A : ±25 mA
• 0.25 A < Target current ≤ 0.3 A : ±8.0 %
• Target current = 0.35 A : ±6.0 %
• 0.4 A < Target current ≤ 2.25 A : ±5.0 %
• Delta battery voltage (9.0 V to 16 V) ±3.0 %
• Delta temperature of 40 °C for a battery fixed (included into 9.0 V to 16 V) ±2.0 %
• Response time: Typ.2.0 ms at transition 0.4 to 2.25 A, 2.25 A to 0.4 A (anti-windup)
• PWM frequency modulation for EMC noise reduction
• Frequency (2.0 Hz to 10 kHz) and programmable duty cycle by the SPI
• Switching delay between valves for emission noise reduction
• Automatic diagnostic sequence (< 1.0 ms)
• Low-side driver for digital control valve

• Low-side RDS(on) = 300 mΩ at TJ = 150 °C
• Low-side gate-drain active clamp = typ. 40 V
• Capability 40 mJ at TJ = 125 °C with 20 mH
• OpenLoad and short-to-ground detection in off-state
Low-side solenoid driver
(4 x channels) • Overcurrent shutdown
• PWM frequency modulation for EMC noise reduction
• Output PWM frequency of each channel is controlled by the SPI independently
• Frequency(2.0 kHz to 10 kHz) and duty resolution are setting by 8-bit SPI commands
• Switching delay between valves for emission noise reduction
• Automatic diagnostic sequence (< 1.0 ms)
900719
Table 8. Features (continued)
• Wheel speed sensor power supply (high-side)

• Decoding for three types of sensors
• Open load and short to battery detection
Wheel speed sensor interface
• Reverse current shutdown
(four channels)
• Overvoltage regulation
• Leakage current tracking
• Short between channels diagnostic
• Vehicle speed output 1

• Open load detection
Vehicle speed output • VDS state monitoring
• Warning lamp driver 1 and 2

Warning lamp driver
• Controlled by ADIN1/2 or SPI command
• K-line or vehicle speed output 2 selected by the SPI

K-line/ VSO
• 6.3 V pre-regulator with external N-channel MOSFET (accuracy ±5.0 %)
VPRE • Current limitation >720 mA
• Undervoltage, overvoltage detection
• Accuracy +3.0 %
• Current capability = 200 mA
• Current limitation > 300 mA
VCC3P3
• Soft start
• Overtemperature shutdown with automatic restart
• Accuracy +2.0 %
VCC5
• Soft start
• Accuracy ±3.0 %
VCC5_EXT • Undervoltage, overvoltage detection
• Soft start
• Short-to-battery protection
900719
Table 8. Features (continued)
• DC–DC converter
• Output voltage: 1.20 V, 1.25 V, 1.30 V, or 3.3 V (predefined at the factory)
• Accuracy +2.0 %
• Current limitation > 1.2 A
VCCA
• Switching frequency = 440 kHz
• Soft start
• Frequency modulation for EMC noise reduction
• CAN – ISO automotive-compliance / without external choke up to 1.0 Mbps

• EMC automotive-compliance
• ESD automotive-compliance
• Two 5.0 V regulator (VCC-CAN)
CAN • Soft start
(two channels) • Overtemperature shutdown
• Wake-up function
• 10-bit data
ADC • 7.0 μs time conversion time
• Three external input channels ( ADIN1, ADIN2, and ADIN3)
• 32-bit communication
• 16-bit data transfer and 8-bit CRC
SPI 32-bit interface
• Watchdog ( challenger/ timeout sequence)
• Maximum frequency = 10 MHz
• L-BIST (self-scan main logic)

L-BIST/ A-BIST • A-BIST (self-check comparator uv/ov of power supply module + comparator included into reset table)
• BIST status monitoring output
• VINT_x undervoltage (ASIC internal regulator)

• DOSV undervoltage (supply voltage from external)
• Watchdog fault
• ALU check counter overflow
• External reset fault
Supervision
• Regulator undervoltage, overvoltage detection
• Internal clock fault
• Die temperature warning
• SPI failure
• ADC voltage monitoring/SPI reading
900719
5.4 Modes of operation
The operating modes are:
• Sleep mode: All functions are disabled except for the CAN and IGN wake-up circuitries.
• Nominal mode: All functions are fully operational. If a fault is detected due to supervision features, the 900719 transits to safe mode.
• Safe mode: Some functions are turned off, e.g. safe HS MOSFET off.
VPWRx < VPWR_sleep

Anywhere OFF
VPWRx > VPWR_uv_rise
Sleep mode
IGN WU
or
CAN WU (Option) IGN < VING-OFF
&
Clear IGN_WU flag and CAN_WU flag
IGN < VING-OFF
&
Clear IGN_WU flag and CAN_WU flag
Error event
Nominal mode Safe mode
Error handling
Figure 5. Operating mode state diagram

The 900719 can be awakened by two external events, either by IGN (or an IGN pulse) or a CAN transmission:
• A valid CAN wake-up pattern
• An IGN signal (level sensitive) or a valid IGN pulse (tTURN_ON + tPULSE)
If the IGN pulse remains high beyond tPULSE, the 900719 transitions to Nominal mode.The nominal state is locked after the delay time of
the reset timer (tRSTB). CAN_WU and IGN_WU bits report the wake-up condition in the SPI (logic [1] reported). The 900719 can be forced
to sleep mode by clearing corresponding wake-up bits CAN_WU or IGN_WU. If a valid wake-up event occurs while the VPWR1 voltage
level is above a specified threshold, the regulators’ power-up sequences are initiated, as illustrated in Figure 6.
900719
VPRE
VCC5/VCC5_EXT/VCCx_CAN
VCCA/VCC3P3
cc5
ss_
ss_v
3 .3
vcc
vcc
VINT_A/VINT_D
3.3
ss_ tRSTB_off
tRSTB
tTURN_OFF
RSTB
(output)
Wake-up
tTURN_ON Power-down event
event
Nominal
Power-up Operation Power-down
Figure 6. Regulators’ power-up and power-down sequences
5.4.1 Regulator electrical characteristics

Table 9. Regulator electrical characteristics
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, - 40 °C ≤ TJ ≤ 150 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
Wake-up
RPDIGN IGN pull-down resistance 100 – 400 kΩ

VHYSTIGN IGN input hysteresis 0.3 0.5 – V
VIGN-OFF IGN input voltage off threshold 2.0 – – V
VIGN_ON IGN input voltage on threshold – – 4.0 V
tRSTB RSTB timer delay 40 45 50 ms
tRSTB_OFF RSTB off timer delay 14.4 18.2 22 μs
tTURN_ON Turn-on delay time – 2.5 – ms
tTURN_OFF Turn-off delay time – 2.0 – ms
tPULSE IGN pulse duration time 10 11 12 ms
900719
5.4.2 Configuration power-down
If battery voltage slowly decreases, eventually the voltage regulators shut off and the 900719 enters sleep mode. Two intermediate zones
are configurable via the SPI PWRDNCFG[1:0] bits, as presented below:
VPWR
VPWR_LV
VPWR_UV_FALL
VPWR_SLEEP
Time
1 2
Default Nominal Safe
Nominal Sleep
Selectable Safe Nominal
Figure 7. Configuration power-down sequence
Table 10. SPI command for power-down sequence

SPI command Zone 1 Zone 2 RSTB forced to low
00 Safe mode Safe mode Below VPWR_UV_FALL
01 (Default) Normal mode Safe mode Below VPWR_UV_FALL

PWRDNCFG[1:0]
10 Normal mode Safe mode Below VPWR_SLEEP
11 Normal mode Extended mode Below VPWR_SLEEP
5.4.2.1 Battery low-voltage and undervoltage detections

When VPWR1 and VPWR2 fall below the VPWR_LV FALL threshold, the corresponding SPI flag VPWR_LV is asserted. When VPWR1 falls
below the VPWR_UV threshold, the SPI flag VPWR_UV is asserted. If VPWR1 continues to drop below the VPWR_SLEEP threshold, power-on
reset causes and forces the device into Sleep mode.
5.4.2.1.1 Low-voltage, undervoltage electrical characteristics
Table 11. Low-voltage, undervoltage electrical characteristics

VPWRx Low-voltage
VPWR_LV Low-voltage detection threshold (falling edge) 6.75 7.0 7.25 V
VPWR_LV_HYS Low-voltage detection hysteresis 200 400 600 mV
VPWR1 undervoltage
VPWR_UV_RISE Undervoltage release threshold 6.1 6.3 6.5 V
VPWR_UV_FALL Undervoltage shutdown threshold 5.5 5.7 5.9 V
VPWR_UV_HYS Undervoltage hysteresis 300 600 900 mV
900719
Table 11. Low-voltage, undervoltage electrical characteristics (continued)
VPWRx sleep
VPWR_SLEEP Sleep mode detection threshold 3.0 3.6 4.2 V
Timing
tVPWR Undervoltage and low-voltage detection filter time 232 293 360 μs
5.4.3 Supervision
The 900719 includes global supervision features:
• Battery low-voltage and undervoltage detections (See Battery low-voltage and undervoltage detections)
• Battery overvoltage detection
• Die temperature warning
• Ground disconnect detection
5.4.3.1 Battery overvoltage detection

The 900719 has overvoltage detection on VPWR1 and VPWR2 respectively. If an overvoltage is detected, the corresponding VPWRX_OV
flag is set.
5.4.3.1.1 Overvoltage electrical characteristics
Table 12. Overvoltage electrical characteristics

Characteristics noted under conditions 6.0 V ≤ VPWRx ≤ 20 V, - 40 °C ≤ TJ ≤ 150 °C, unless otherwise noted. Typical values noted reflect
VPWRx overvoltage
VPWR_OV Overvoltage threshold 30 32 34 V
VPWR_HYS Overvoltage hysteresis 0.3 0.6 1.0 V
tVPWR Overvoltage detection filter time 232 293 360 μs
5.4.3.2 Die temperature warning

The 900719 has one temperature warning sensor located at center of the die to monitor the temperature of the chip. In case of a
temperature warning, outputs are not shutdown and the SPI-bit shows the actual status at accessing time. This thermal sensor is used to
report the die temperature in the A/D.
5.4.3.2.1 Temperature warning electrical characteristics
Table 13. Temperature warning electrical characteristics

Characteristics noted under conditions 6.0 V ≤ VPWRx ≤ 20 V, - 40 °C ≤ TJ ≤ 150 °C, unless otherwise noted. Typical values noted reflect
Overtemperature/temperature warning
TW Temperature warning detection threshold 160 170 180 °C
tTW Temperature warning detection filter time 232 293 360 μs
900719
5.4.3.3 Ground disconnect detection
The 900719 monitors the voltage between the GND_P and GND_D2 pin to detect ground disconnection. The FGND bit is set when the
GND_D2 ground pin versus the GND_P pin is higher than V_GL. If the ground shift is greater or totally disconnected, the MCU detects it
due to the SPI watchdog error.
5.4.3.3.1 Ground disconnect electrical characteristics
Table 14. Ground disconnect electrical characteristics

Characteristics noted under conditions 6.0 V ≤ VPWRx ≤ 20 V, –40 °C ≤ TJ ≤ 150 °C, unless otherwise noted. Typical values noted reflect
Overtemperature/temperature warning
V_GL Ground loss detection voltage threshold 100 200 300 mV
tGL Ground loss detection detection filter time 232 293 360 μs
5.4.3.4 Reset input/output pin

The RSTB pin behaves as an:
• Output terminal: the 900719 generates a permanent or pulse reset (tRSTB_REC) when the 900719 detects a fault, as presented in the
Table 16 truth table.
• Input terminal: the MCU forces a device reset if RSTB is low during at least tRSTB_EXT.
5.4.3.4.1 Reset electrical characteristics
Table 15. Reset electrical characteristics

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, – 40 °C ≤ TJ ≤ 150 °C, unless otherwise noted. Typical values noted reflect
Reset input
tRSTB_EXE External reset detection 1.0 – 4.0 μs
t_RST_MIN Minimum external reset time from MCU 8.0 10 – μs
Reset output
tRSTB_REC Reset recovery 36 45 54 ms
900719
5.4.3.5 Safe mode truth table
For safety reason, the specified events put the 900719 in safe mode as shown in the following table:
Table 16. Safe mode truth table

Wheel
SPI Valves Safe HS Motor WLDx CAN ISO Voltage
Event RSTB pin speed (29) (27)
registers control pump interfaces K-line regulators (26)
sensors
Normal mode
Nominal operation after wake-up

(30) High Normal Normal Normal Normal Normal On Normal Normal Normal
Low during
at leaset
Reset forced by MCU OFF Reset (28) OFF OFF OFF OFF Recessive OFF Normal
t_RST_MIN
(input)
Safe mode with default SPI setting
Clock failure (25) High OFF Reset(23) OFF OFF OFF OFF Recessive OFF No effect
(25) (23)
Charge pump failure High OFF Reset OFF OFF OFF OFF Recessive OFF No effect
(23)
LBIST running or failure High OFF Reset OFF OFF OFF OFF Recessive OFF No effect
VPWRx overvoltage (25) High No effect Reset (23) OFF OFF ON (24) No effect No effect No effect No effect
VPWRx low-voltage with

High No effect Reset (23) OFF OFF OFF No effect No effect No effect No effect
PWRDGCFG[1:0] = 00 (25)
VPWRx undervoltage with

Low OFF Reset (23) OFF OFF OFF OFF Recessive OFF OFF
PWRDGCFG[1:0] = 01 (25)
VPWRx undervoltage with

High OFF Reset (23) OFF OFF OFF OFF No effect OFF No effect
PWRDGCFG[1:0] = 10 (25)
Low during
Watchdog fault or ALU fault (25) No effect Reset (23) OFF OFF OFF OFF No effect No effect No effect
tRSTB_REC
VCC3P3 or VCC5 or VCCA

High No effect Reset (23) OFF OFF OFF OFF No effect No effect No effect
undervoltage (25)
Only VCC5_EXT
OFF. Automatic
VCC5_EXT undervoltage or (23)
High No effect Reset OFF OFF OFF OFF No effect No effect restart after
VCC5_EXT overtemperature (25) 10 ms in case of
OT
OFF with
VPRE or VCC3P3 or VCC5 or
Low OFF Reset (23) OFF OFF OFF OFF Recessive OFF automatic restart
VCCA overtemperature after 10 ms
VINT_x undervoltage Low OFF Reset (23) OFF OFF OFF OFF Recessive OFF OFF
Sleep mode
VPWR1 sleep voltage Low OFF Reset OFF OFF OFF OFF Recessive OFF OFF
Notes:
23. SPI registers forced to initial state except the flag events register which reports all cited faults and all the ‘no effect’ functions.
24. PD forced in on-state (during tLD_ACT) by the load dump feature (PD_D or HD_D voltage > PD_ov).
25. Fault detection can be disabled through SPI. In case of disable, no effect on the functions and the RSTB pin (i.e. RSTB stays High).
26. VPRE, VCCA, VCC5, VCC5_EXT, VCC3P3, VCC1_CAN, and VCC2_CAN voltage regulators.
27. WLDx low-side driver OFF means the warning lamps are ON.
28. SPI registers forced to initial state except for the EXT_RST bit.
29. Turn-off after tLSDx_HD_G.
30. Refer to each operation for normal operation.
900719
5.4.3.6 Configurable supervision features
The following supervision features can be managed by the corresponding SPI bit setting as described in Table 17:
Table 17. Supervision features

SPI disable bit name Setting Description SPI flag name
0 (default) Charge pump undervoltage causes SAFE mode and SPI Flag
CPFAILDIS CP_FAIL
1 Fault causes SPI flag only
0 (default) VCC3P3 undervoltage causes safe mode, and SPI flag

VCC3P3UVDIS VCC3P3_UV
0 (default) VCC5 undervoltage causes safe mode, and SPI flag

VCC5UVDIS VCC5_UV
VCC5_EXT undervoltage causes external VCC5EXT regulator shutdown (only) and

0 (default)
VCC5EXTUVDIS SPI flag is set VCC5EXT_UV
0 (default) CCA undervoltage causes safe mode, and SPI Flag is set
VCCAUVDIS VCCA_UV
0 (default) VPWRx overvoltage causes safe mode and SPI flag is set
VPWRxOVDIS VPWR1_OV
Current source enabled on VSO output when VSO is off. If open load is detected,
0 (default)
VSO_OP_DIS the SPI flag is set VSO_OP
1 Current source disabled; SPI flag disabled
Current source enabled on VSO2 output when VSO2 is off. If open load is
0 (default)
VSO2_OP_DIS detected, the SPI flag is set VSO2_OP
Current source enabled on WLDx output when WLDx is off. If open load is
0 (default)
WLDx_OP_DIS detected, the SPI flag is set WLDx_OP
1 Current source disabled; SPI Flag disabled
WSSx low-level sensor current is tracked. If ILOW > ILEAK_FLT SPI flag is set (SPI
0 (default) WxT1_LKG, WxT2_LKG,
WSx_TRK_DIS Flag only)
WxT3_LKG
1 Low-level sensor current tracking disabled; SPI flag disabled
Safety feature is tested during ABIST, if failure occurs, the *FAIL and *_SA bits
0 (default)
*_ADIS (31) will be set accordingly *FAIL, *_SA
1 Test is skipped, *FAIL and *_SA bits are cleared next time ABIST runs
0 (default) If PD_D or HD_D > PD_ov, turn on PMD and set PMD_LD flag
PMD_LDA_DIS PMD_LD
1 Fault causes SPI flag Only
0 (default) CAN transceiver active

CANxTxRxDIS CANxTxRxEN
1 Only VCCx_CAN active including UV/OV protections
0 (default) Clock monitoring logic are enabled

CLKMONDIS (32) CLK_FAIL
1 Clock monitoring logic disabled
0 (default) 14 MHz main/alt clock failure causes safe mode and SPI flag is set
CLKFAILDIS (32) CLK_FAIL
1 Fault causes SPI flag Only
Notes:
31. There are 16 bits in the SPI register map, one for each ABIST test.
32. If CLKMONDIS is set, the CLK_FAIL SPI bit disables, and therefore CLKFAILDIS bit is meaningless.
900719
5.4.4 Error handling
Table 18. Error handling
Type of error Detection condition Action SPI operation Restart condition (33)
VPRE_SUP disconnection Nominal mode SPI flag only (VPRE_SUP_DISC flag) Write 1
Shutdown all regulators (VPRE, VCCA,

Automatic power-up after
overtemperature with VCC3P3, VCC5, VCC5_EXT, and Reset due to power
All except sleep mode 10 ms timeout period and
hysteresis VCCx_CAN) SPI flag reported. up
TJ < otl_x
(VPRE_OT flag)
overcurrent ON SPI flag reported (VPRE_ILIM flag)
overvoltage All except sleep mode SPI flag only (VPRE_OV flag) Write 1
undervoltage All except sleep mode SPI flag only (VPRE_UV flag) Write 1
VCCA, VCC3P3 and VCC5 voltage regulators
Shutdown all regulators (VPRE, VCCA,

VCC3P3, VCC5, VCC5_EXT and Automatic power-up after
overtemperature with Reset due to power
All except sleep mode VCCx_CAN SPI flag reported. 10 ms timeout period and TJ
hysteresis up
(Vxxx_OT flag), Go to safe mode. See < otl_x
Table 16
overcurrent ON No action, no SPI flag
overvoltage All except sleep mode SPI flag only (Vxxx_OV flag) Write 1
undervoltage (can be disabled SPI flag (Vxxx_UV flag) Go to Safe
All except sleep mode Write 1
individualy) mode. See Table 16
VCC5_EXT voltage regulator

Shutdown VCC5EXT only. SPI flag Automatic power-up after
overtemperature with (VCC5EXT_OT flag). Go to Safe mode.
All except sleep mode 10 ms timeout period and TJ
hysteresis
See Table 16 < otl_x
overcurrent ON No action, no SPI flag
overvoltage All except sleep mode SPI flag only (VCC5EXT_OV flag) Write 1
Shutdown VCC5EXT only. SPI flag
undervoltage (can be disabled (VCC5EXT_UV flag). Go to safe mode.
All except sleep mode Write 1 Clear VCC5EXT_UV flag
individualy)
See Table 16
Pump motor pre-driver
PD_D disconnection All except sleep mode SPI flag only (PMD_PD _DISC flag) Write 1
Shutdown PD_G and SPI fault flag Turn-on again through the
overcurrent ON Write 1
(PMD_OC flag) SPI
Shutdown PD_G & FRW_G and SPI Turn-on again through the
overtemperature All except sleep mode Write 1
fault flag (PMD_OT) SPI
High-side pre-driver for valve’s safe switch
HD_D disconnection All except sleep mode SPI flag only (HSD_DISC flag) Write 1
Turn-on again through the

Shutdown HD_G. SPI fault flag.
overcurrent ON Write 1 SPI + SPI command required
(HSD_OC)
to renable the valves

overtemperature All except sleep mode Write 1 SPI + SPI command required
(HSD_OT)
HSD_EN rise-edge Ignore HSD_EN rise-edge command. Turn-on again through the
Load leakage Write 1
SPI bit SPI fault flag. (HSD_LEAK) SPI

HSDx overvoltage All except sleep mode Write 1 SPI + SPI command required
(HSD_OV)
900719
Table 18. Error handling (continued)
High-side pre-driver for valve’s safe switch (continued)
Automatic valves diagnostic.

OFF SPI flag (AVD_FLT) Write 1
(can be disabled)
Valve low-side switches
open load OFF SPI flag only (x_OP) Write 1
HSDx open detection OFF SPI flag only (HSD_OPEN_x) Write 1
LSDx drain to source

All except sleep mode SPI flag only. SPI flag only(x_VDS) Read diagnosis
monitoring
Shutdown the corresponding LSDx and Turn-on again through the

SPI fault flag. (x_OC) SPI
Shutdown the corresponding LSDx and

overtemperature All except sleep mode Write 1 Then operate normaly
SPI fault flag (LSDx_OT)
current regulation error (only
ON SPI flag only (x_CRER) Write 1
for current regulated valves)
Wheel speed sensor

1st step: WSx_OP_SH SPI flag
open load ON 2nd step shutdown the corresponding Write 1 No shutdown
WSx_HS with WSx_DIS=1 by MCU:
WSx_OPEN SPI flag
1st step: WSx_OP_SH SPI flag

Short-to-battery All except sleep mode 2nd step shutdown the corresponding Write 1 No shutdown
WSx_HS with WSx_DIS=1 by MCU:
WSx_SH2BAT flag
RETRY_DIS = 0: Automatic
Shutdown the corresponding WSx_HS retry every 16 ms
Reverse current ON Write 1
and SPI fault flag (WSx_REVCUR) RETRY_DIS = 1: Turn-on
again through the SPI
and SPI fault flag (WSx_OC) RETRY_DIS = 1: Turn-on
overtemperature All except sleep mode Write 1
and SPI fault flag (WSx_OT) RETRY_DIS = 1: Turn-on
Channel to channel short OFF SPI flag only (WSx_S2S_SH) Write 1
Channel leakage ON SPI flag only (WxT1_LEAK) Read diagnosis
Vehicle speed output
open load OFF SPI flag only (VSO_OPEN) Write 1

Drain-to-source monitoring All except sleep mode SPI flag only (VSO_VDS) Read diagnosis
VSO shutdown and SPI fault flag

overcurrent ON Write 1 Then operate normaly
(VSO_OC)
VSO shutdown. SPI fault flag

(VSO_OT)
Warning lamp pre-driver
open load OFF SPI flag only (WLDx_OP) Write 1

VDS state monitoring All except sleep mode SPI flag only (WLDx_VDS) Read diagnosis
WLD shutdown and SPI fault flag

(WLDx_OC)
900719
Warning Lamp Pre-driver (Continued)
WLD shutdown. SPI fault flag

(WLDx_OT)
ISO K-line or 2nd vehicle speed output
open load OFF SPI flag only (VSO2_OPEN) Write 1
Drain-to-source monitoring All except sleep mode SPI flag only (VSO2_VDS) Read diagnosis
ISO K-line shutdown and SPI fault flag

(ISOK_VSO2_OC)
ISO K-line shutdown and SPI fault flag

(ISOK_VSO2_OT)
CAN interfaces
Corresponding CAN driver disabled

overtemperature CAN driver (recessive mode) but receiver still Next recessive to dominant
All except sleep mode
with hysteresis active. SPI flag reported (CANx_OT TXD transition
flag)
Corresponding CAN driver disabled
(recessive mode) but receiver still
TXDx dominant CAN driver All except sleep mode Write 1
active. SPI flag reported
(CANx_TXD_PD flag)
Automatic power-up after

overtemperature VCCx_CAN Shutdown the Vccx_CAN regulator SPI
All except sleep mode 10 ms timeout period and TJ
with hysteresis flag reported (VCCxCANOT flag)
< otl_x
CAN voltage regulators with CANxTxRxDIS = 1

SPI flag only if the corresponding
undervoltage VCCx_CAN with CANxTxRxDIS = Write 1
regulator UV is disabled
1

SPI flag only if the corresponding
overvoltage VCCx_CAN with CANxTxRxDIS = Write 1
regulator OV is disabled
1
Supervision
SPI watchdog fault RSTB is high state See Table 16. SPI flag (WDFLT) Write 1 (34)
Safe mode and reset. See Table 16.

ALU check counter overflow RSTB is high state Write 1 (34)
(WD_OVRFLW and WD_ER_CNT[2:0])
VPWR1 undervoltage See Table 16. SPI flag only by Turn-on again through the
RSTB is high state Write 1
(can be disabled) PWRDNCFG=11 (VPWR1_UV) SPI
VPWRx low-voltage See Table 16. SPI flag only

RSTB is high state (VPWRx_LV) but Safe mode if Write 1
(can be diasabled) SPI
PWRDNCFG=00
VPWRx overvoltage
RSTB is high state See Table 16. SPI flag (VPWRx_OV) Write 1 Then operate normaly
(can be disabled)
PD_G turn on during tLDact; off with
Load dump (can be disabled) RSTB is high state normal condition with a certain filter Write 1
time. SPI flag (PMD_LD)
CP failure (can be disabled) All except sleep mode See Table 16. SPI flag (CP_FAIL) Write 1
Clock failure (can be disabled) RSTB is high state See Table 16. SPI flag (CLK_FAIL) Write 1
Die temperature warning RSTB is high state SPI flag only (DIE_TEMP_WARN) Write 1
SPI failure RSTB is high state See Table 16. SPI flag (FMSG) Write 1
GND_D supervision RSTB is high state SPI flag only (FGND) Write 1
900719
Supervision (Continued)
IREF failure RSTB is high state SPI flag only (IREF_FAIL) Write 1
Successfully re-
running the
A-BIST failure RSTB is high state SPI flag only (ABIST_FAIL)
corresponding
BIST test
Successfully re-
running the
L-BIST failure RSTB is high state See Table 16. SPI flag (LBIST_FAIL)
corresponding
BIST test
Notes:
33. Fault condition disappears.
34. After 900719 reset.
900719
6 Functional block description
6.1 Current references
6.1.1 Introduction
IREF reference current is used for valves’ low-side switches and IREF_REDUNT for valves’ high-side switches. In case of a false resistor
value at IREF (error > IREF_error_pos or error < IREF_error_neg), the IREF_FAIL flag is set. It is required to connect IREF and
IREF_REDUNT resistors to GND_A pin.
6.1.2 Current reference electrical characteristics

Table 19. Current reference electrical characteristics
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, –40 °C ≤ TJ ≤ 150 °C, unless otherwise noted. Typical values noted reflect
IREF and IREF_REDUNT
R_IREF External resistances –0.1 % 10 0.1 % kΩ
Maximum allowable differential current between IREF and

IREF_ALLOWABLE –10 0.0 +10 %
IREF_REDUNT
IREF_ERROR_POS Positive error detection between IREF and IREF_REDUNT 10 – 30 %

IREF_ERROR_NEG Negative error detection between IREF and IREF_REDUNT –30 – –10 %
6.2 Oscillator
6.2.1 Introduction
900719 contains a 14 MHz clock, which generates all the system clock and multiple filter times. The clock error is detected by the clock
monitoring feature.
6.2.1.1 Clock monitoring

The 900719 monitors the clock frequency constantly. A fault is detected if the frequency is more than ±35 % of 14 MHz typ. If a fault is
detected, a SPI flag is reported (CLK_FAIL). The clock monitoring process restarts only after the clock monitoring flag (CLK_FAIL) is
cleared by a SPI write 1.
6.2.1.2 Frequency modulation

This function is controlled by the FM_OSC_EN and FM_OSC_AMP bits.The SPI command (FM_OSC_EN) enables the frequency
modulated oscillator by a two deviation frequency to spread the oscillator’s energy over a wide frequency band. Two types of deviation
frequencies are selected by the SPI command:
• When FM_OSC_AMP = 0, there are four steps up in frequency (frequency step: f_mod1 / 4) and four steps down in frequency
• When FM_OSC_AMP = 1, there are eight steps up in frequency (frequency step: f_mod2 / 8) and eight steps down in frequency
This spreading decreases the peak electromagnetic radiation level and improves electromagnetic compatibility (EMC) performance. By
default, the frequency modulation is disabled.
900719
frequency
t_mod
fOSC + fmodx
fOSC + fmodx/4
time
fOSC
fOSC - fmodx
Figure 8. Frequency modulation description (FM_OSC_AMP = 0)
6.2.2 Oscillator electrical characteristics

Table 20. Oscillator electrical characteristics
Oscillator
f_OSC Main oscillator frequency –7.0 % 14 +7.0 % MHz
f_MOD1 Frequency modulation band 1 –30 % 350 +30 % kHz
f_MOD2 Frequency modulation band 2 –30 % 700 +30 % kHz

t_MOD Frequency modulation speed –30 % 9.09 +30 % μs
6.3 Charge pump
6.3.1 Introduction
The charge pump generates a voltage of a typical 12 V above the supply VPWR1. The charge pump voltage is intended for internal use
only. No additional load is connected to the CP pin. The charge pump requires an external 20 V X7R capacitor for energy storage and to
cover transients. The voltage difference between CP and VPWR can be read by the SPI (ADC data). Moreover, the CP_FAIL SPI flag
error is reported, in case (VCP – VPWR1) < cp_uv. The CP_FAIL detection is disabled due to the CPFAILDIS SPI bit.The charge pump
frequency is modulated due to the FM_CP_EN and FM_CP_AMP SPI bits.
900719
6.3.2 Charge pump electrical characteristics
Table 21. Charge pump electrical characteristics
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. (37)
C_CP Charge pump external capacitor – 220 – nF
VPWR1
V_CP Charge pump voltage, referred to ground VPWR1+12 VPWR1+15 V
+VCP_UV
VCP_UV Carge pump undervoltage threshold 4.5 5.0 5.5 V
VCP_UV_F Charge pump undervoltage detection filter time 14.1 18.2 22 μs
f_CP Charge pump frequency 7.0 9.0 11 MHz
f_MOD1 Frequency modulation band 1 –30 % 225 +30 % kHz (35)
f_MOD2 Frequency modulation band 2 –30 % 450 +30 % kHz (36)
t_MOD Frequency modulation speed –30 % 9.09 +30 % μs
Notes:
35. FM_CP_EN = 1 & FM_CP_AMP bit = 0
36. FM_CP_EN = 1 & FM_CP_AMP bit = 1
37. The parameter is guaranteed in extended VPWR voltage range from 5.3 V to 6.0 V. VPRE_S has to be more than 5.2 V when VPWR is 5.3 V.
6.4 Pre-linear voltage regulator VPRE
6.4.1 Introduction
VPRE is a linear regulator with an external ballast N-channel FET providing a typical 6.3 V. This regulator supplies five linear voltage
regulators integrated in the 900719, as shown in Figure 9.
VPWR1
External
Pre-linear VPRE connection
Regulator with external
N-channel FET
6.3 V typical VPRE_S VPRE_CAN
Linear 5.0 V Linear 5.0 V Linear 3.3 V Linear 5.0 V Linear 5.0 V
Regulator Regulator Regulator Regulator Regulator
VCC5 VCC5_EXT VCC3P3 VCC1_CAN VCC2_CAN
Figure 9. Simplified block diagram of the VPRE power supply

This voltage regulator has a current limitation with an external shunt resistor connected between VPRE_SUP and VPRE_D, a thermal
shutdown protection localized on the gate driver, an R-pull-down at off, and a soft start, which limits its rising slope at the regulator power-
on sequence, as illustrated in Figure 10:
900719
VBAT1
VPRE disconnect
detection VPRE_SUP
Current Limitation VPRE_D

VPRE_G
Gate driver with 10n
VPRE_S
soft start
Overtemperature 220n
detection
Under and
Overvoltage
Capable to sustain
detection 40 V short-circuit
Linear voltage regulators
GND_A
Figure 10. VPRE architecture

If a VPRE_SUP pin disconnection occurs, the 900719 reports the fault with a VPRE_SUP_DISC flag. If an external ballast drain-to-source
short-circuit occurs, the inner linear voltage regulators (VCC5, VCC5_EXT, VCC3P3 and VCCx_CAN) are not damaged up to the
VPRE_MAX voltage. In Sleep mode, the FET gate-to-source is pulled down through non-internal circuitry.
6.4.2 VPRE electrical characteristics

Table 22. VPRE electrical characteristics
Characteristics noted under conditions 6.0 V ≤ VPWRx ≤ 20 V, – 40 °C ≤ TJ ≤ 150 °C, unless otherwise noted. Typical values noted reflect
Voltage and current

VPRE Voltage accuracy, 7.0 V ≤ VPWR ≤ 20 V 5.985 6.3 6.615 V
VPRE_EXTENDED Voltage accuracy, 6.0 V ≤ VPWR ≤ 7.0 V 5.8 6.0 6.6 V
IVPRE Current capability – – 610 mA

ILIM_VPRE Current limitation 720 900 1120 mA
VPRE_MAX Max VPRE_S voltage without damage – – 40 V
IVPRE_OFF VPRE_S pull-down current in sleep mode 4.0 9.0 14 mA
Undervoltage and overvoltage detection
VUV_VPRE Undervoltage threshold 4.683 4.93 5.177 V
VOV_VPRE Overvoltage threshold 6.84 7.2 7.56 V
tUV_VPRE_F Undervoltage detection filter time 57.6 72.8 88 μs
tOV_VPRE_F Overvoltage detection filter time 57.6 72.8 88 μs
Overtemperature detection
TOTH_VPRE Overtemperature shutdown threshold 195 210 225 °C
TOTL_VPRE Overtemperature release threshold 180 195 210 °C
TOT_HYS_VPRE Overtemperature hysteresis – 15 – °C
tOT_VPRE_F Overtemperature detection filter time 14.4 18.2 22 μs
tRT-TSD Restart time after thermal shutdown 8.0 10 12 ms
900719
Table 22. VPRE electrical characteristics (continued)
VPRE_SUP disconnect detection
VPRE_SUP_DOWN VPRE_SUP pull-down 21 34 47 μA
VPREF_SUP_DIS VPRE_SUP disconnect detection threshold (falling edge) 1.6 2.25 3.2 V
VPRER_SUP_DIS VPRE_SUP disconnect detection threshold (rising edge) 1.7 2.4 3.3 V
VPRE_SUP_DIS_
VPRE_SUP disconnect detection threshold hysteresis 35 160 350 mV
HYS
VPRE_SUP_DIS_F VPRE_SUP disconnect detection filter time 14.4 18.2 22 μs
Power-up and power-down sequence
ss_vpre Soft start 5.0 – 30 mV/μs
6.5 DC/DC buck converter VCCA
6.5.1 Introduction
VCCA is a DC/DC buck converter providing a selectable typical voltage from 1.2 V to 3.3 V.
VCCA_SUP
DC/DC Buck
Converter
Voltage value depends
on the part number
VCCA
Figure 11. Simplified block diagram of VCCA power supply
Table 23. VCCA voltage value selection

Part number VCCA voltage VCCA_VSEL[1:0] bits reporting
SC900719AAF/R2 1.25 V 00 (default)
SC900719BAF/R2 1.20 V 01
SC900719CAF/R2 1.30 V 10
SC900719DAF/R2 3.3 V 11
The VCCA regulator integrates the high-side switching FET, supplied by the VPWR pin, which drives the external inductor. The DC/DC
buck converter is a current mode buck (step-down), PWM switching regulator that contains a high current capability up to 800 mA, and
all control, logic, and protection functions. A configurable frequency modulation allows switching noises when this feature is activated
through the SPI (FM_VCCA_EN, FM_VCCA_MP[1:0], and FM_VCCA_MB[3:0] SPI bits).
It is possible to disable the undervoltage fault protection by the VCCAUVDIS SPI bit. A current limitation cycle-by-cycle is implemented to
avoid uncontrolled power dissipation (duty cycle control), and limits the current below the current limitation. This voltage regulator also
has a thermal shutdown protection implemented in the internal high-side FET. VCCA voltage can be identified by the VCCA_VSEL[1:0]
bits. See Table 23.
900719
6.5.2 VCCA electrical characteristics
Table 24. VCCA electrical characteristics
Voltage and current
Voltage accuracy selectable with part

• B part 1.17 1.2 1.22
VACCURACY_VCCA • A part 1.22 1.25 1.27 V
• C part 1.27 1.3 1.32
• D part 3.236 3.3 3.364
INOMINAL_VCCA Current capability – – 800 mA
Current peak limitation

IPEAK_VCCA • 6.0 V ≤ VPWR ≤ 20 V 1.2 1.5 1.9 A
• 5.3 V ≤ VPWR < 6.0 V 1.2 1.5 2.2
Undervoltage
• B part 1.12 1.145 1.17
VUV_VCCA • A part 1.17 1.195 1.22 V
• C part 1.22 1.245 1.27
• D part 3.1 3.168 3.236
Overvoltage
• B part 1.22 1.245 1.27
VOV_VCCA • A part 1.27 1.295 1.32 V
• C part 1.32 1.345 1.37
• D part 3.364 3.432 3.5
tUV_VCCA_F Undervoltage filter time 232 293 360 μs
tOV_VCCA_F Overvoltage filter time 232 293 360 μs
TOTH_VCCA Ovetemperature shutdown threshold 195 210 225 °C
TOTL_VCCA Overtemperature release threshold 180 195 210 °C

TOT_HYS_VCCA Overtemperature hysteresis – 15 – °C
tOT_VPCCA_F Overtemperature filtering 14.4 18.2 22 μs
Frequency modulation
tSF_VCCA Switching frequency –10 % 440 +10 % kHz
00 = no modulation (default)
FM_VCCA_MB 01 = ±3.15 % / 1 step (38)
2 SPI bits for frequency modulation band
[1:0] 10 = ±6.3 % / 2 step
11 = ±12.6 % / 3 step
00 = 8
01 = 16 (38)
FM_VCCA_MP 2 SPI bits for frequency modulation period
10 = 32 (default)
11 = 64
Power up, power down sequence
Soft start
VSS_VCCA 2.0 – 30 mV/μs
• 6.0 V ≤ VPWR ≤ 20 V
900719
Table 24. VCCA electrical characteristics (continued)
Transient rejection (39)
Line regulation 7.0 V ≤ VPWR ≤ 20 V

LNRVCCA A, B, C version – – 2.0 %
D version – – 3.0
Load regulation from 250 mA to Max.(IVCCA)

LDR_vcca – – 5.0 %
• 6.0 V ≤ VPWR ≤ 20 V
Notes:
38. Frequency modulation active if FM_VCCA_EN bit = 1
39. Transient rejection errors are related to the momentary output voltage level at the time when the transient was applied. Less transient rejection
performance is achieved if COUT is reduced.
6.6 3.3 V linear regulator VCC3P3
6.6.1 Introduction
VCC3P3 is a linear regulator providing a typical 3.3 V. This regulator is supplied by the VPRE pin and an external capacitor for filtering
and stability. It is possible to disable the undervoltage fault protection by the SPI command (VCC3P3UVDIS bit).
6.6.2 VCC3P3 electrical characteristics

Table 25. VCC3P3 electrical characteristics
Voltage and current
VVCC3.3 Voltage accuracy 3.2 3.3 3.39 V
IVCC3.3 Current capability – – 200 mA
ILIM_VCC3.3 Current limitation 300 400 550 mA
VUV_VCC3.3 Undervoltage threshold (can be disabled) 3.0 3.1 3.2 V
VOV_VCC3.3 Overvoltage threshold (can be disabled) 3.39 3.5 3.6 V
tUV_VCC3.3_F Undervoltage detection filter time 232 293 360 μs
tOV_VCC3.3_F Overvoltage detection filter time 232 293 360 μs
TOTH_VCC3.3 Overtemperature shutdown threshold 195 210 225 °C
TOTL_VCC3.3 Overtemperature release threshold 180 195 210 °C
TOT_HYS_VCC3.3 Overtemperature hysteresis – 15 – °C
tOT_VCC3.3_F Overtemperature filtering 14.4 18.2 22 μs
900719
Table 25. VCC3P3 electrical characteristics (continued)
Power up and power down sequence

ROFF_VCC3.3 Pull down resistor – – 60 Ω
Soft start
VSS_VCC3.3 5.0 – 30 mV/μs
• 6.0 V ≤ VPWR ≤ 20 V
Transient rejection
LNRVCC3.3 Line regulation 7.0 V ≤ VPWR ≤ 20 V – – 0.5 %
Load regulation from 0 to Max. (I_vcc3.3)

LDRVCC3.3 – – 2.5 %
• 6.0 V ≤ VPWR ≤ 20 V
Input ripple rejection ratio

PSSRRVCC3.3 60 – – dB
• 6.0 V ≤ VPWR ≤ 20 V
Notes:
6.7 5.0 V linear regulator VCC5
6.7.1 Introduction
VCC5 is a linear regulator providing a typical 5.0 V. This regulator is supplied by VPRE and an external capacitor for filtering and stability.
It is possible to disable the undervoltage fault protection by the SPI command (VCC5UVDIS bit).
6.7.2 VCC5 electrical characteristics

Table 26. VCC5 electrical characteristics
Voltage and current
Voltage accuracy
VVCC5 • 6.0 V ≤ VPWR ≤ 20 V 4.9 5.0 5.1 V
• 5.3 V ≤ VPWR < 6.0 V (I_VCC5 < 100 mA) 4.85 5.0 5.1
IVCC5 Current capability – – 200 mA
ILIM_VCC5 Current limitation 300 400 550 mA
VUV_VCC5 Undervoltage threshold (can be disabled) 4.5 4.675 4.85 V
VOV_VCC5 Overvoltage threshold (can be disabled) 5.15 5.325 5.5 V
tUV_VCC5_F Undervoltage detection filter time 57.6 72.8 88 μs
tOV_VCC5_F Overvoltage detection filter time 57.6 72.8 88 μs
900719
Table 26. VCC5 electrical characteristics (continued)
TOTH_VCC5 Overtemperature shutdown threshold 195 210 225 °C
TOTL_VCC5 Overtemperature release threshold 180 195 210 °C
TOT_HYS_VCC5 Overtemperature hysteresis – 15 – °C
tOT_VCC5_F Overtemperature filtering 14.4 18.2 22 μs
Power up and power down sequence
ROFF_VCC5 Pull-down resistor – – 60 Ω
Soft start
VSS_VCC5 5.0 – 30 mV/μs
• 6.0 V ≤ VPWR ≤ 20 V
Transient rejection
LNRVCC5 Line regulation 7.0 V ≤ VPWR ≤ 20 V – – 0.5 %
Load regulation from 0 to Max. (IVCC3.3)

LDRVCC5 – – 2.0 %
• 6.0 V ≤ VPWR ≤ 20 V
Input ripple rejection ratio

PSSRVCC5 60 – – dB
• 6.0 V ≤ VPWR ≤ 20 V
Notes:
6.8 5.0 V external linear regulator VCC5_EXT
6.8.1 Introduction
VCC5_EXT is a linear regulator providing a typical 5.0 V. This regulator is supplied by VPRE and an external capacitor for filtering and
stability. It is possible to disable the undervoltage fault protection by the SPI command (VCC5_EXTUVDIS bit). Undervoltage is ignored
for the defined masking time (tUV_VCC5_EXT_M) when VCC5 is enabled. If the undervoltage is detected, only VCC5_EXT is shutdown. The
regulator turns on again when the VCC5EXT_UV flag is cleared. The VCC5_EXT pin sustains a 40 V short-circuit without reverse current.
If VCC5_EXT is higher than VPRE, the regulator is shutdown and avoids the reverse current flowing into VPRE. It will be possible to disable
VCC5_EXT output by SPI command (VCC5EXTDIS bit).
6.8.2 VCC5_EXT electrical characteristics

Table 27. VCC5_EXT electrical characteristics
Voltage and current
VCC5_EXT Voltage accuracy 6.0 V ≤ VPWR ≤ 20 V 4.85 5.0 5.15 V
VREL_VCC5_EXT (44)
Relative error versus VCC5 –2.0 – 2.0 %
IVCC5_EXT Current capability – – 100 mA
ILIM_VCC5_EXT Current limitation 150 250 350 mA
900719
Table 27. VCC5_EXT electrical characteristics (continued)

VUV_VCC5_EXT Undervoltage threshold (can be disabled) 4.5 4.675 4.85 V
VOV_VCC5_EXT Overvoltage threshold (can be disabled) 5.15 5.325 5.5 V
tUV_VCC5_EXT_F Undervoltage detection filter time 57.6 72.8 88 μs
tOV_VCC5_EXT_F Overvoltage detection filter time 57.6 72.8 88 μs
tUV_VCC5_EXT_M Undervoltage detection mask time after startup 100 128 154 ms
TOTH_VCC5_EXT Overtemperature shutdown threshold 195 210 225 °C
TOTL_VCC5_EXT Overtemperature release threshold 180 195 210 °C
TOT_HYS_VCC5_EXT Overtemperature hysteresis – 15 – °C
tOT_VCC5_EXT_F Overtemperature filtering 28.8 36.4 44 μs

(43)
VSS_VCC5_EXT Soft start 80 – 160 mV/μs
Transient rejection
LNRVCC5_EXT Line regulation 7.0 V ≤ VPWR ≤ 20 V – – 0.5 %
LDRVCC5_EXT Load regulation from 0 to Max. (IVCC3.3) – – 2.0 %

PSSRVCC5_EXT Input ripple rejection ratio 60 – – dB
Notes:
43. No pull-down resistor inside the 900719
44. (VCC5_EXT – VCC5) / VCC5 * 100
6.9 Dual 5.0 V linear regulators VCCx_CAN
6.9.1 Introduction
VCCx_CAN is a dual linear regulators providing a typical 5.0 V for each CAN physical layer. This regulator is supplied by VPRE_CAN
(connected to VPRE externally). VCCx_CAN voltage regulators can be also used in standalone without the CAN transceiver operation.
The undervoltage and overvoltage fault protection is active when the corresponding CAN transceiver is disabled by the SPI command
(CANxTxRxDIS bit = 1).
6.9.2 VCCx_CAN electrical characteristics

Table 28. VCCx_CAN electrical characteristics
Voltage and current
VVCC_CAN Voltage accuracy 5.5 V ≤ VPWR ≤ 20 V 4.5 5.0 5.5 V

IVCC_CAN Current capability – – 50 mA
ILIM_VCC_CAN Current limitation 70 90 110 mA
900719
Table 28. VCCx_CAN electrical characteristics (continued)
VUV_VCC_CAN Undervoltage threshold (can be disabled) 4.0 – 4.5 V
VOV_VCC_CAN Overvoltage threshold (can be disabled) 5.5 – 6.5 V
tUV_VCC_CAN_F Undervoltage detection filter time 28.8 36.4 44 μs
tOV_VCC_CAN_F Overvoltage detection filter time 28.8 36.4 44 μs
TOTH_VCC_CAN Overtemperature shutdown threshold 195 210 225 °C
TOTL_VCC_CAN Overtemperature release threshold 180 195 210 °C
TOT_HYS_VCC_
Overtemperature hysteresis – 15 – °C
CAN
tOT_VCC_CAN_F Overtemperature filtering 14.4 18.2 22 μs
VSS_VCC_CAN Soft start 6.0 V ≤ VPWR ≤ 7.0 V 35 – 140 mV/μs

ROFF_VCC_CAN Pull-down resistor 0.7 1.0 1.3 kΩ
Transient rejection
LNRVCC_CAN Line regulation 7.0 V ≤ VPWR ≤ 20 V – – 0.5 %
LDRVCC_CAN Load regulation from 0 to Max. (IVCC3.3) 6.0 V ≤ VPWR ≤ 7.0 V – – 2.0 %
PSSRVCC_CAN Input ripple rejection ratio 6.0 V ≤ VPWR ≤ 7.0 V 60 – – dB
Notes:
6.10 Internal voltage regulators VINT_A and VINT_D
6.10.1 introduction
VINT_A and VINT_D are linear regulators for internal power supply. An external capacitor is needed for filtering and stability. If an
undervoltage fault is detected, the 900719 is forced to sleep mode. VINT_A and VINT_D are not used as an external power supply.
6.10.2 VINT_A and VINT_D electrical characteristics
Table 29. VINT_A and VINT_D electrical characteristics

Voltage and current
VINT_A Internal analog voltage 2.35 2.5 2.7 V
VINT_D Internal digital voltage 2.35 2.5 2.7 V
Undervoltage
VINT_UV Undervoltage reset threshold 2.0 2.175 2.35 V
900719
Table 29. VINT_A and VINT_D electrical characteristics (continued)
tVINT Undervoltage detection filter time – – 2.0 μs
ROFF_VINT R-pull-down_off 90 – 400 Ω
Notes:
6.11 DOSV digital output supply voltage
6.11.1 Introduction
The DOSV pin is dedicated to supply the 900719’s digital output buffers (SO, WSOx, WSAI, RXDx, and RXK), either at 5.0 V or 3.3 V, by
externally connecting the VCC5 or VCC3P3 pins, as in Figure 12.
DOSV
100 k
Logic Digital Outputs
GND_D2
Figure 12. Digital output buffer supply

This pin is protected against short-circuits to ground and an open condition. In these cases, the SPI SO reports 0000’hex. DOSV has
undervoltage detection. As long as DOSV is in an undervoltage condition, CAN interfaces are in recessive mode and ISOK is off. In a
DOSV short-circuit to ground, the undervoltage of the regulator supplying the voltage for DOSV (VCC5 or VCC3P3) reports the fault. In a
DOSV open condition, this pin is pulled down by virtue of RDOWN_DOSV.
6.11.2 DOSV electrical characteristics

Table 30. DOSV electrical characteristics
DOSV
RDOWN_DOSV Pull-down resistor 25 50 75 kΩ
VUVR_DOSV Undervoltage threshold rising 2.0 – 2.6 V
VUVF_DOSV Undervoltage threshold falling 1.8 – 2.4 V
VUV_DOSV_HYS Undervoltage threshold hysteresis 80 – 300 mV
tUV_DOSV_F Undervoltage detection filter time 28.8 36.4 44 μs
900719
6.12 Dual CAN interfaces (CAN1 and CAN2)
6.12.1 Introduction
The circuit includes two high-speed CAN interfaces up to 1.0 Mbps communication baud rate. An additional transient dynamic
characteristic is specified in order to adapt a higher communication rate up to 2.0 Mbps. Once ISO11898-2 is released, these parameters
might be updated according to the requirement. A wake-up circuit is implemented only on CAN1. Figure 13 illustrates a high level diagram
of the CAN interface:
VCCx_CAN
TXDx
R_in
CANx_H
Buffer CANx_L
R_in
DOSV Differential
receiver
RXDx
CAN1_H
Wake-up
Wake-up receiver
CAN1_L
CAN1 only
GND_A
Figure 13. CAN interface block diagram

Each CAN interface is biased by a dedicated 5.0 V regulator, called VCCX_CAN.
During the regulators power-up sequence, the CAN bus remains in a recessive state, and no parasitic dominant pulse is visible on the
CAN bus. The RXDx signal level depends on DOSV voltage (3.3 V or 5.0 V).
6.12.2 CAN operating modes

Two different operating modes are selectable through the SPI:
• CAN normal mode (CANx_MODE bit = 1, default value) with half of the VCCx_CAN voltage biasing: the CAN interface allows
transmission and reception of a CAN message from the bus to the CAN protocol controller located inside the MCU, and from the
CAN protocol controller to the bus.
• CAN low-power mode (CANx_MODE bit = 0): transmission or reception of message from/to the bus is impossible.
During CAN low-power mode:
• CAN1_H and CAN1_L terminals are monitored for wake-up events. The input switch resistances, called RIN, is grounded
• CAN2_H and CAN2_L terminals behave high-ohmic (floating / Hi-Z)
900719
6.12.3 CAN wake-up (CAN1 Only)
A wake-up circuitry is implemented to detect CAN traffic in CAN low-power mode. This mechanism is disabled while the device is in normal
mode. The device wake-up detection is based on pattern detection. The pattern consists in the detection of three consecutive events. The
three events are a dominant level, followed by a recessive level, then a second dominant level. Each dominant or recessive level is filtered
and should be longer than tWUFL1 or tWUFL2. The three events occurs within a maximum time window, parameter tWUTO, otherwise the
wake is ignored. When the pattern is detected, the wake-up event is latched.
Recessive level
Dominant level Dominant level Dominant level
CAN
Bus
T_wufl1 T_wufl2 T_wufl2 T_tog T_tog T_tog
3rd event
1st event 2nd event
T_tog
Figure 14. CAN wake-up pattern
Recessive level
Dominant level Dominant level
CAN
Bus
T_wufl1 T_wufl2 T_wufl1
1st event 2nd event 1st event
RxD
T_wuto
T_wuto expire
Figure 15. CAN tWUTO
6.12.4 TXDx failure detection

The TXDx permanent dominant detection is implemented to detect if the TXDx pin is dominant for a time longer that tX_DOM. The tX_DOM
value defines the maximum possible number of consecutive dominant bits at the lowest baud rate (CAN protocol dependant). When TXDx
permanent dominant is detected, the CAN driver disables and the fault is reported in the CANx_TXD_PD SPI bit. It allows the rest of the
network and node to operate (release the bus from dominant state). The CAN receiver continues to operate. After the TXDx permanent
dominant failure is detected and the CAN driver turned OFF, the CAN driver can be re-enabled when TXDx transitions from recessive to
the dominant state and SPI writes 1.
6.12.5 Overtemperature detection

An overtemperature detection is implemented, with overtemperature the parameter TOTRISE_CANX. When the temperature reaches
TOTRISE_CANX, the CAN driver is disabled (CANH and CANL driver turned OFF) and the fault is reported to the corresponding CANx_OT
SPI bit. The CAN receiver continues to operate. When the temperature falls below TOTFALL_CANX, the CAN driver is enabled again
automatically, at the next recessive to dominant TXD transition.
6.12.6 CAN bus failure protection

The 900719 integrates CANx_L/CANx_H current limitation, to prevent excessive current during short-circuits to ground or to battery. In
case of a short-circuit, the CAN driver and receiver are not disabled, as long as overtemperature is reached.
900719
6.12.7 Inductive short-circuit
The device sustains inductive short-circuits on CANx_H (to ground) and CANx_L (to battery). The inductance is composed of the wire
harness (length 20 meters, to develop additional inductance of 20 μH). The short-circuit could be applied to a fixed DC voltage of 40 V
and –27 V. During the short-circuit test, the device is in CAN normal mode, with a square signal applied on TXDx. The failure criteria is
‘no damage’ to the device.
6.12.8 CAN electrical characteristics

Table 31. CAN electrical characteristics
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, – 40°C ≤ TJ ≤ 150°C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
CAN voltage operation
VPWER_CAN Functional operating supply voltage (VPWR) 5.5 – 20 V
CAN wake-up
tWUFL1 Wake-up filter 0.5 – 5.0 μs
tWUFL2 Wake-up filter 0.08 – 1.0 μs

tWUTO Pattern wake-up timeout 250 – 1000 μs
CAN interface leakage
IH_LEAK_UNPWR,
CANx_H CANx_L leakage in unpowered mode – – 10 μA
IL_LEAK_UNPWR
IH_LEAK, IL_LEAK CANx_H, CANx_L leakage current in recessive mode –1.0 – 4.0 mA
Transceiver dynamic characteristics
tLOOP Loop time TXD to RXD – – 255 ns
tDTX-BUS(R-D),
Delay Time from TXD to Bus DOM/REC 37.5 75 150 ns
tDTX-BUS(D-R)
tDBUS-RX(R-D),
Delay time from bus DOM/REC to RXD 37.5 75 150 ns
tDBUS-RX(D-R)
tFALL-H, tFALL-L, tRISE:20 % to 80 %

– – 50 ns
tRISE-H, tRISE-L tFALL:20 % to 80 %
CIN CANX-L CANx-L input capacitance – 20 – pF
CIN CNX-H CANx-H input capacitance – 20 – pF

tBIT_BUS Transmitted recessive bit width at tBIT (TXD) = 500 ns 435 – 530 ns (47)
tBIT_RX Received recessive bit width at tBIT (TXD) = 500 ns 400 – 550 ns (47)
(48)
tREC Receiver timing symmetry at tBIT (TXD) = 500 ns –65 – 40 ns
TXD digital input
tX_DOM TXD dominant timeout 2.5 – 16 ms
CANx_H, CANx_L
Differential receiver threshold voltage, recessive edge

VDIFFX_R 0.5 – – V
• VDIFFX = VCANX-H – VCANX-L
VDIFFX_D Differential receiver threshold voltage, dominant edge – – 0.9 V
VDIFF COM MODE Differential input comparator common mode range –12 – 12 V
Differential receiver threshold voltage, recessive edge

VDIFFX_STB_R 0.4 – – V
• VDIFFX = VCANX-H – VCANX-L
VDIFFX_STB-D DIfferential receiver threshold voltage, dominant edge – – 1.15 V
900719
Table 31. CAN electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, – 40°C ≤ TJ ≤ 150°C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
CANx_H, CANx_L (continued)

VCANX-L DOM CANx_L dominant voltage 0.5 – 2.25 V
VCANX-H DOM CANx_H dominant voltage 2.75 – 4.5 V
V(H-L) DOM CAN differential voltage in dominant state 1.5 2.0 3.0 V
CANx_H current limitation/capability

ICANX-H DRIVE 40 – 100 mA
• –27 V < CANX_H < 1.5 V
CANx_H, CANx_L (continued)
CANx_L current limitation/capability

ICANX-L DRIVE • 3.5 V < CANX_L ≤ 16 V 40 – 115 mA
• 3.5 V < CANX_L < 40 V 40 – 130
VCANX-L REC CANx_L recessive voltage 2.0 2.5 3.0 V
VCANX_H REC CANx_H recessive voltage 2.0 2.5 3.0 V

V(H-L) REC CAN differential voltage in recessive state –500 – 50 mV
VIN DIFF Differential input threshold 0.5 – 0.9 V
RINX_L CANx_L input resistance 5.0 – 50 kΩ
RINX-H CANx_H input resistance 5.0 – 50 kΩ

RINX-DIFF CANx differential input resistance 10 – 100 kΩ
TOTRISE_CANX Driver overtemperature switch off threshold 195 210 225 °C
TOTFALL_CANX Driver overtemperature release threshold 180 195 210 °C

TOTHYST_CANX Driver overtemperature hysteresis – 10 – °C
tOT_CANX_F Driver overtemperature filtering 14.4 18.2 22 μs
Notes:
47. RLOAD = 60 Ω, CLOAD (between CANx_H and CANx_L) = 100 pF. C at RXDx = 15 pF
48. tREC = tBIT_RX – tBIT_BUS
6.13 Pump motor pre-driver with active re-circulation
6.13.1 Introduction
The pump motor is controlled up to 16 kHz through the SPI:
• activation: PMD_EN bit. When PMD_EN is 0, both high-side and low-side gate drivers are off.
• PWM frequency: F_PMD[4:0] bits
• PWM duty cycle: PMD_DC[7:0] bits
The high-side FET pre-driver is composed of bootstrap circuitry, as well as a small charge pump structure, to operate 100 % duty. The
PWM duty cycle error between the SPI configuration and the output is below 1.0 % from 10 % to 90 %, from 8.0 V to 20 V, as illustrated
in Figure 16.
900719
Output Duty Cycle
Input
10 % 90 % Duty Cycle
Figure 16. Pump motor drive PWM duty cycle range
Below 10 % and above 90 %, the MCU compensates to address the expected PWM output duty cycle. The bootstrap capacitor is charged
(tBOOT_DELAY) before the high-side FET pre-driver operation. This time is included in tRSTB time. The typical high-side FET is
IPB80N04S2-04 (max 4.0 mΩ on-state resistance at 25 °C with 40 V capability) or IPB100N04S2-04 (max 2.0 mΩ on-state resistance
with 40 V capability). The freewheeling current path can be done through a diode or an external N-channel low-side FET. By default, the
freewheeling current path is done by a diode. The SPI PMD_ACT bit is set to control the external low-side FET in opposite to the high-
side FET. The typical low-side FET is IPD30N06S4L-23 (max 13 mΩ on-state resistance at 25 °C with 55 V capability). Some embedded
protection avoids vertical current conduction in half-bridge topology.
An additional N-channel low-side FET can be also used in series to cutoff the current in reverse battery.
Load dump
Charge
protection
pump
Supply disconnect VBAT2
detection
PD_D
Current Limitation PD_S
between high-side and low-side
50
Logic avoiding cross-talk
50
Gate driver PD_G 470k
VBOOT 50
Bootstrap
FRW_G 220n
Over-temperature
M
470k
detection
Gate driver for VBAT2

external low-side
10k
GND_P
Figure 17. Pump motor-driver description

The VBOOT – PD_S voltage is fixed up to a typical 15 V by the 900719. 15 V zener clamping circuitry can be added respectively between
the PD_G and PD_D pins, and between the gate and source of the low-side FET, to protect against transient events. The maximum
allowable ground shift between the ECU and the motor depends on the VTH of low-side MOSFET. The PD_G and FWR_G pins are pulled
down in sleep mode through a dedicated external passive circuitry (470 kΩ resistor).
6.13.2 Frequency modulation

The PWM frequency modulation band and speed are activated by the FM_PMD_EN bit and defined by the following SPI bits:
• Four bits for the frequency modulation band (FM_PMD_MB[3:0]): number of frequency steps
• Two bits for the frequency modulation period (FM_PMD_MP[1:0]): number of PWM period between frequency steps
900719
6.13.3 Overcurrent protection
The pump pre-driver protects the external N-channel power FET on PD_G in overcurrent conditions. The drain-to-source voltage of the
FET on PD_G is checked continuously when the pump driver is switched on. If the measured drain-to-source voltage exceeds the
selectable overcurrent voltage threshold (PMD_OC_SEL[2:0]), the output of the overcurrent comparator reports a fault. If the output of the
comparator is active longer than the defined filter time (tPD_OC), the output PD_G is switched off and the PMD_OC OP SPI bit is set to
logic [1]. Overcurrent detection circuitry has a selectable masking time (mtPD_OC) after the 1st edge of turn-on, reporting the fault and
avoiding a transient time malfunction.
PumpControl
Pump control ON OFF
tim e
PWM Signal
PWM signal Duty-cyle = FF’hex Duty-cyle = 7F’hex
ti me
mtPD_oc
Overcurrent
Over-current
protection
Protection Disabled Enabled
time
Figure 18. Overcurrent and HS FET open detection

The masking time and filter time of pump driver are controllable by the SPI bit.
• 1 SPI bit (PMD_OC_MASK) for MtPD_OC
• 2 SPI bits (PMD_OC_TIME[1:0]) for tPD_OC
After switching off the power FET with an overcurrent condition, the power FET can be turned back to ‘normal state’ only by a SPI write 1
to the PMD_OC bit and a turn-on command (PM_EN bit). The overcurrent function can be disabled by writing 1 to PMD_OC_DIS.

When the temperature of both gate pre-drivers (high-side or low-side) is above the overtemperature threshold (OTPMD) for the defined
filter time (tOT_PMD), both drivers are switched off and a SPI fault bit is set (PMD_OT). When both high-side and low-side FETs are off, the
energy from the motor drains through the body diode of the low-side FET. The driver can be turned back to ‘normal state’ by a write 1 to
PMD_OT bit and then a turn-on command (PM_EN bit).
6.13.5 Load dump protection

in case of a load dump, the pump motor turns on to absorb the energy stored. if a Load Dump occurs (PD_D or HD_D voltage > PD_ov)
on the pin PD_D for a time period longer than tPD_OV, PD_G is activated to turn-on the motor, except if an overtemperature and overcurrent
fault occurs concurently. PD_G stays ON during tLD_ACT after HD_D goes below the PD_ov threshold. When VPWR goes to the
undervoltage condition during tLD_ACT, PD_G turns off and the ‘tLD-ACT’ counter is set to the end value. The load dump function is disabled
by the SPI command (PMD_LDA_DIS bit), but the flag is displayed by the PMD_LD bit through the SPI.
PD_ov
HD_D
tPD_OV tPD_OV
PD_G tLD_ACT
Figure 19. Pump motor load dump protection
900719
Table 32. Pump motor driver operation
Operation mode PMD_OT PMD_OC PMD_LD pmd_act PMD_EN PD_G FRW_G Restart conditions
0 0 0 X 0 OFF OFF
Normal mode 0 0 0 0 1 PWM OFF

–
0 0 0 1 1 PWM PWM_b
During load dump 0 0 1 X Forced to 0 100 % ON OFF
After load dump 0 0 1 X Forced to 0 OFF OFF PMD_EN = 1

Overcurrent 0 1 X X Forced to 0 OFF OFF Clear OC flag and PMD_EN = 1
Overtemperature 1 0 X X Forced to 0 OFF OFF Clear OT flag and PMD_EN = 1
6.13.6 PD_D disconnect detection

If a PD_D pin disconnection occurs, the 900719 SPI reports a PMD_PDD_DISC fault after T1. A 470 kΩ resistor must be populated
between PD_G and PD_S to passively turn-off the FET.
6.13.7 ECU ground disconnection

If an ECU ground disconnection occurs (motor ground still connected), the 900719 is self protected. The N-channel power FET on PD_G
turns off, due to a VPWRx undervoltage detection. A 15 V gate-to-source clamp circuitry on the N-channel low-side FET is added to protect
it in case of an ECU ground disconnection, for VBAT > 20 V.
6.13.8 Pump motor pre-driver electrical characteristics

Table 33. Pump motor pre-driver electrical characteristics
PD_G
PD_G switch-on voltage at 5.0 kHz PWM

• 5.5 V < VPWR < 6.0 V VPWR +4.0 – VPWR +15
VPD_ON_5K • 6.0 V ≤ VPWR < 8.0 V VPWR +5.0 – VPWR +15 V
• 8.0 V ≤ VPWR < 11 V VPWR +7.0 – VPWR +15
• 11 V ≤ VPWR < 20 V VPWR +10 – VPWR +15
PD_G switch-on voltage at 10 kHz PWM

• 5.5 V < VPWR < 7.0 V –
VPWR +4.5 VPWR +15
VPD_ON_10K – V
• 7.0 V ≤ VPWR < 12 V VPWR +6.0 VPWR +15
–
• 12 V ≤ VPWR < 20 V VPWR +10 VPWR +15
–
VGS_OFF PD_G switch-off voltage – – 0.8 V
IDC_PD Driver capability 50 – – mA

(49)
IPDG_OFF Turn-off current in sleep mode 0.4 0.8 1.6 mA
PD_S
ILEAK_PD_S Leakage current in sleep mode – – 1.0 mA
PD_D
ILEAK_PD_D Leakage current in sleep mode – – 10 μA
900719
Table 33. Pump motor pre-driver electrical characteristics (continued)
Overcurrent shutdown
Programmable overcurrent detection
PMD_OC_SEL[2:0] bits
• 000 –15 % 0.69 +15 %
• 001 (default) –15 % 0.79 +15 %
• 010 –15 % 0.89 +15 %
VPD_OC V
• 011 –15 % 0.99 +15 %
• 100 –15 % 1.08 +15 %
• 101 –15 % 1.18 +15 %
• 110 –15 % 1.28 +15 %
• 111 –15 % 1.38 +15 %
Programmable overcurrent detection filter time

PMD-OC_TIME[1:0]
• 00 7.2 9.1 11
tPD_OC μs
• 01(default) 14.4 18.2 22
• 10 9.6 12.1 14.7
• 11 464 586 720
Overcurrent detection masking time after turn on

tMTPD-OC • PMD_OC_MASK bit = 0 7.2 9.1 11 μs
• PMD_OC_MASK bit = 1 – 1.1 – ms
Allowed duty cycle

• 0.1 kHz 0.062 – 99.934
• 0.2 kHz 0.124 – 99.877
• 0.3 kHz 0.185 – 99.815
• 0.4 kHz 0.247 – 99.753
• 0.5 kHz 0.309 – 99.691
• 0.6 kHz 0.371 – 99.630
• 0.7 kHz 0.432 – 99.568
• 0.8 kHz 0.494 – 99.506
• 0.9 kHz 0.556 – 99.444
• 1.0 kHz 0.618 – 99.383
• 2.0 kHz 1.235 – 98.765
• 3.0 kHz 1.853 – 98.148
Duty_range %
• 4.0 kHz 2.470 – 97.530
• 5.0 kHz 3.088 – 96.913
• 6.0 kHz 3.705 – 96.295
• 7.0 kHz 4.323 – 95.678
• 8.0 kHz 4.940 – 95.060
• 9.0 kHz 5.558 – 94.443
• 10 kHz 6.175 – 93.825
• 11 kHz 6.793 – 93.208
• 12 kHz 7.410 – 92.590
• 13 kHz 8.028 – 91.973
• 14 kHz 8.645 – 91.355
• 15 kHz 9.263 – 90.738
• 16 kHz 9.880 – 90.120
Overtemperature shutdown
TOT_PMD Overtemperature shutdown threshold 180 195 210 °C

tOT_PMD Overtemperature detection filter time 14.4 18.2 22 μs
900719
Load dump protection
VPD_OV PD_D or HD_D overvoltage threshold 27.5 29.5 31.5 V
tPD_OV PD-D or HD_D overvoltage detection filter time 57.6 72.8 88 μs
tLD_ACT Load dump activation time 520 600 700 ms
VBOOT charge
tBOOT_DELAY Bootstrap start time – 20 30 ms
PWM controlled by the SPI
Output PWM frequency

F_PMD[4:0] bits
• 00000 0.1
• 00001 0.2
• 00010 0.3
• 00011 0.4
• 00100 0.5
• 00101 0.6
• 00110 0.7
• 00111 0.8
• 01000 0.9
• 01001 1.0
• 01010 2.0
fPMD • 01011 –15 % 3.0 +15 % kHz
• 01100 4.0
• 01101 5.0
• 01110 6.0
• 01111 7.0
• 10000 8.0
• 10001 9.0
• 10010 10
• 10011 11
• 10100 12
• 10101 13
• 10110 14
• 10111 15
• 11000 16
PWM duty cycle programming
PMD_DC[7:0] bits
• 0000 0000 – 0 –
• 0000 0001 – 0 –
DUTY_PMD %
• 0000 0010 – 1/256 –
• … – … –
• 1111 1110 – 254/256 –
• 1111 1111 – 100 –
900719
Frequency modulation
0001 = ±0.5 %/1 step
FM_PMD_ (50)
Four SPI bits for frequency modulation band 0010 = ±1.0 %/2 step
MB[3:0]
…
1111 = ±7.5 %/15 step
00 = 8 cycle
FM_PMD_ 01 = 16 cycle (50)
Two SPI bits for frequency modulation period
MP[1:0] 10 = 32 cycle (default)
11 = 64 cycle
Active freewheeling path
IPD_G Driver capability 50 – – mA
VGS_FRW_ON FRW_G switch-on voltage – Vpwr 13 V

VGS_FRW_OFF FRW_G switch-off voltage – – 0.8 V
IFRW_G_OFF Turn-off current in sleep mode 0.4 0.8 1.6 mA
PD_D disconnect detection
RPD_D_DOWN PD_D passive pull-down 150 300 600 kΩ
VPD_D_DIS PD_D voltage threshold 1.6 2.25 3.2 V
VPD_D_DIS_HYS PD_D voltage threshold hysteresis – 160 – mV

VPD_D_DIS_F PD_D disconnect detection filter time 14.4 18.2 22 μs
Notes:
49. Typical 2.0 mA and maximum 4.0 mA for PD_G=40 V
50. If the PMD’s PWM is controlled by SPI (FM_PMD_EN=1), the frequency modulation is active on the first PWM cycle.
900719
6.14 High-side pre-driver for valve’s safe switch
6.14.1 Introduction
The high-side pre-driver is intended to control the safe switch for the overall solenoid path. The HD_G pin is controlled by the SPI
command (HSD_EN bit). An external diode or a FET is needed, as presented in Figure 20 for reverse protection.
VBAT1
Over-current 470k
Charge protection
pump
Supply disconnect
detection
HD_D
Over-temperature
100
Logic detection
Gate driver with HD_G 100
soft start
470k
HD_S
Load Leakage
100
GND_A
Low-side switches for

Valves Control
Figure 20. Safe high-side for valves with reverse battery protection
The HD_G pin is pulled down in sleep mode through a dedicated external passive circuitry (470 kΩ resistor and diode). In cases of safe
switch overcurrent, overtemperature fault detection, or an HSDx overvoltage detection, the FET is switched off automatically. A rewrite
operation (x_EN bit) is required to re-enable the drivers.
6.14.2 Overcurrent protection

The high-side pre-driver protects the external N-channel power FET on HD_G from an overcurrent condition. The typical high-side FET
is IPD30N06S4L-23 (max. 13 mΩ on-state resistance at 25 °C with 55 V capability). The drain-to-source voltage of the external FET on
HD_G is checked to see if the high-side driver is switched on. The output of the overcurrent comparator reports a fault if the measured
drain-to-source voltage exceeds the selectable overcurrent voltage threshold (HSD_OC_SEL[2:0]). If the output of the comparator is
active longer than the selectable filter time (tHD_OC, selected due to HSD_OC_TIME[1:0]), the output HD_G is switched off and the SPI
HSD_OC bit is set to logic [1]. Overcurrent detection faults have a masking time (MtHD_OC, selected due to HSD_OC_MASK bit) from the
turn-on signal against a malfunction on transient time. In case of a fault (overcurrent or overtemperature), the power FET is turned off in
fast mode (HSD_SR= 1). After switching off the power FET on HD_G by an overcurrent condition, the power FET can be turned back to
a ‘normal state’ only by a SPI write 1 to the HSD_OC bit, then a turn-on by the SPI command (HSD_EN bit).

When the temperature of gate pre-driver is above the overtemperature threshold (OTHS) for the defined filter time (tOT_HS), the driver is
switched off and the HSD_OT SPI fault bit is set. The driver can be turned back to a ‘normal state’ only by a write 1 to HSD_OT, then a
turn-on command (HSD_EN bit).
6.14.4 HD_S load leakage detection

Each time HD_G is turned on, the IHD_LC current is sourced out of the HD_S pin for the time tHD_LC, to check the external leakage current
on the node in the application. The LSDs are turned on after tHD_LC. The high-side switch on HD_G is turned on if the measured voltage
is over the detection threshold (VHD_LC). If this test fails, HD_G does not turn-on and the HSD_LEAK fault flag is set to high. The external
FET can be turned back to ‘normal state’ only by a SPI write 1 to the HSD_LEAK bit, then a turn on by SPI command (HSD_EN bit). When
the external FET is switched in off-state, the gate capacitance of FET is discharged a selectable constant current, due to the SPI HSD_SR
bit.
900719
6.14.5 HD_D disconnect detection
If a HD_D pin disconnection occurs for a dedicated filter time (tVHD_D_DIS_F), the HSD_DISC bit is set high.
6.14.6 High-side pre-driver electrical characteristics

Table 34. High-side pre-driver electrical characteristic
HD_G
HD_G Switch-on Voltage

• 5.3 V< VPWR < 6.0V VPWR +4.0 – VPWR +15
VHD_ON • 6.0 V ≤ VPWR < 8.0 V VPWR +5.0 – VPWR +15 V
• 8.0 V ≤ VPWR < 11 V VPWR +7.0 – VPWR +15
• 11 V ≤ VPWR < 20 V VPWR +10 – VPWR +15
HD_G switch-off voltage

VHD_OFF – – 0.8 V
• 6.0 V ≤ VPWR < 20 V
Turn-on time
tHD_ON – – 1.4 ms
• 6.0 V ≤ VPWR < 20 V
Turn-on current
IHD_ON 300 600 800 μA
• 6.0 V ≤ VPWR < 20 V
Turn-off current slow

IHD_OFF_SLOW 70 100 200 μA
• 6.0 V ≤ VPWR < 20 V
Turn-off current fast

IHD_OFF_FAST 1.0 3.0 6.0 mA
• 6.0 V ≤ VPWR < 20 V
Delay time of HD_G shutdown after LSD shutdown due to supply fault
tLSDX_HD_G or reset condition 1.0 1.5 2.0 ms
• 6.0 V ≤ VPWR < 20 V
Turn-off current in sleep mode (51)

IHD_OFF 0.4 0.8 1.6 mA
• 6.0 V ≤ VPWR < 20 V
RHD_REV Negative voltage resistance of HD_G 18 – – MΩ
HD_S
ILEAK_HD_S Leakage current – – 50 μA
HD_D
ILEAK_HD_D Leakage current – – 10 μA
Overcurrent detection
Programmable overcurrent detection

HSD_OC_SEL[2:0] bits
• 000 –15 % 0.69 +15 %
• 001 (default) –15 % 0.79 +15 %
• 010 –15 % 0.89 +15 %
VHD_OC V
• 011 –15 % 0.99 +15 %
• 100 –15 % 1.08 +15 %
• 101 –15 % 1.18 +15 %
• 110 –15 % 1.28 +15 %
• 111 –15 % 1.38 +15 %
900719
Table 34. High-side pre-driver electrical characteristic (continued)
Programmable overcurrent detection filter time

HSD-OC_TIME[1:0]
• 00 14.4 18.2 22
tHD_OC μs
• 01(default) 116 147 180
• 10 232 293 360
• 11 464 586 720
Overcurrent detection masking time after turn ON
tMTHD-OC HSD_OC_MASK bit = 0 1.3 1.5 1.7 ms
HSD_OC_MASK bit = 1 2.6 3.0 3.4 ms
TOTH_HS Overtemperature shutdown threshold 195 210 225 °C
TOTL_HS Overtemperature release threshold 170 185 200 °C
tOT_HS Overtemperature detection filter time 14.4 18.2 22 μs
Load leakage current detection
IHD_LC HD_S source current 2.0 3.0 4.0 mA

VHD_LC Leakage voltage threshold 1.6 2.0 2.4 V
tHD_LC Load leakage current detection duration 464 586 720 μs
tHD_LC_FIT Load leakage current detection filter time 232 293 360 μs
HD-D disconnect detection
IHD_D_DOWN HD_D pull-down current 50 100 200 μA
VHD_D_DIS HD_D voltage threshold 1.6 2.25 3.2 V
VHD_D_DIS_HYS HD_D voltage threshold hysteresis – 160 – mV
tHD_D_DIS_F HD_D disconnect detection filter time 14.1 18.2 22 μs
Notes:
51. VCC5 = DOSV = 0 V; HD_G = 2.0 V; HD_D = PD_D = VPWR = 14 V
6.15 Low-side switches for valves control
6.15.1 Introduction
The 900719 is designed to drive digital or current regulated valves. All 12 channels are composed of low-side FETs with an open-drain
output, a pre-driver circuit, a diagnostic circuitry, and a current regulator, depending on the type of valves.
6.15.2 Digital valves

Channels LSD1, 6, 7, and 12 are four digital (also called ‘PWM’) low-side switches, with a self recirculation integrated, due to gate-drain
clamp circuitry. The output transistor is equipped with an active clamp limiting LSDx voltage to VCL_LSD or VCL_LSD2. During turn-off, the
inductive load forces the increasing output voltage until the active voltage clamps, such as when the power FET turns on again.
900719
Safe Switch
Drain-to-source
Monitoring
Open load detection

Logic
Overcurrent
4 LSDx
shutdown
Gate Control
SPI
Overtemperature
shutdown
(x4ch)
GND_P
Figure 21. Low-side switches for digital valves
6.15.3 Current regulated valves

Channels LSD 2, 3, 4, 5, 8, 9, 10, and 11 are eight low-side switches and eight high-side switches, for the recirculation and with a current
regulation function. The regulated current range is between ICR_MIN and 2.25 A. The recirculation is accomplished via the integrated high-
side circuitry. The output transistor is also equipped with an active clamp limiting LSDx voltage to VCL_LSD3 to absorb fast transient
disturbances.
Safe Switch
2
Safe Overvoltage HSDx
switch detection
control
Gate Control
Drain-to-source
Monitoring
Logic Open load detection
Overcurrent
8 LSDx
shutdown
Gate Control
SPI
Overtemperature
shutdown
(x8ch)
GND_P
Figure 22. Low-side/high-side switches for current regulated valves
These high-side switches have a common drain, called HSD1 or HSD2 (one per side), as illustrated in Figure 23:
900719
Safe Switch
HSD1 HSD2
LSD2 LSD11
LSD3 LSD10
LSD4 LSD9
LSD5 LSD8
GND_P GND_P
Figure 23. Current regulated valves
Each HSDx pin connects internally to four pins. This freewheeling circuitry is active until the inductor current becomes zero. Each valve
driver is controlled by the SPI control registers when the corresponding x_EN bit is set to a logic [1]. The valves could switched with a
fixed PWM duty cycle when the x_FDC bit is set to 1 and controlled to regulate the current when the x_FDC bit is set to 0.
6.15.4 PWM control

The PWM duty cycle is set independently by 10 SPI bits (x_DC[9:0] or x_I[9:0]). The PWM duty cycle setting is categorized in five
operation ranges, clamped off, low saturation, programmable zone, high saturation, and clamped on. The operation range varies with
switching frequencies as shown in Table 35.
Table 35. PWM control duty cycle settings

Zone 2.0 kHz 2.6 kHz 3.2 kHz 3.8 kHz 4.4 kHz 5.0 kHz 5.6 kHz 6.2 kHz 6.8 kHz 7.4 kHz 8.0 kHz 8.6 kHz 9.2 kHz 10 kHz
Clamped OFF (0
0–2 0–2 0–3 0–3 0–4 0–5 0–5 0–6 0–6 0–7 0–8 0–8 0–9 0–10
%)
Low Saturation 3–4 3–5 4–6 4–8 5–9 6–10 6–11 7–13 7–14 8–15 9–16 9–18 10–19 11–21
Programmable 10– 11– 12–

5–1015 6–1013 7–1011 9–1008 14–998 15–996 16–993 17–991 19–988 20–986 22–983
Zone 1005 1003 1000
1016– 1014– 1012– 1009– 1006– 1004– 1001– 999– 997– 994– 992– 989– 987– 984–
High Saturation
1020 1018 1017 1016 1015 1014 1012 1011 1010 1009 1008 1007 1005 1004
Clamped ON (100 1021– 1019– 1018– 1017– 1016– 1015– 1013– 1012– 1011– 1010– 1009– 1008– 1006– 1005–
%) 1023 1023 1023 1023 1023 1023 1023 1023 1023 1023 1023 1023 1023 1023
In PWM, the common output frequency of channels is controlled from 2.0 to 10 kHz, by LF_PWM[3:0] SPI bits. The sequence/interleaved
phase shift between the channels is implemented to minimize switching noise of the solenoid coil. The valves switching sequence is
predefined as follows: LSD1, LSD6, LSD7, LSD12, LSD3, LSD4, LSD9, LSD10, LSD2, LSD11, LSD5, and LSD8. The delay between each
valve’s activation is selectable with the TDEL_V_DIS bit (tDELAY_VALVES or zero). The LSD1 output is used as reference.
Period=1/LF_PWM
LSD1(reference) Duty Cyle
tDELAY_VALVES tDELAY_VALVES
LSD6 (delayed)
Figure 24. Switching delay between valves (tDEL_V_DIS = 0)
900719
During valve operation, the output duty cycle adjusts at the end of the PWM period, in case of a SPI setting change. The VLV_SYNC_SEL
is a read/write SPI bit controlling the valves switching.
• Set to logic [0]: the duty cycle/current change occurs on the next PWM period after the SPI write command to the duty cycle/current
register
• Set to logic [1]: the duty cycle/current changes are postponed until the next PWM cycle after writing ‘1’ to the individual enable bit of
the valve updating the PWM/current of (which is already ‘1’). If the user wants to change all of the duty cycle/currents at once, all 12
of the valve enable bits can be re-written to 1 at the same time, since they are in the same SPI register.
6.15.5 Frequency modulation

PWM frequency modulation is activated with the FM_LSD_EN bit. The band and speed is defined by six SPI bits.
• Four bits for the frequency modulation band (FM_LSD_MB[3:0]): the number of frequency steps
• Two bits for the frequency modulation period (FM_LSD_MP[1:0]): the number of PWM periods between frequency steps
frequency
Frequency change after Fmp<1:0> periods
f0+0.5 %.f0
f0 = LF_PWM
The number of frequency
steps depends on
Fmb<3:0> bits
f0-1.0 %.f0
Figure 25. Frequency modulation description (2 Steps)
6.15.6 Current regulation control

The regulated current is set independently by 10 SPI bits (x_I[9:0]).
• 00’hex: 0
• 01’hex: 2.2 mA
• 3FF’hex:2.25 A
The sequence/interleaved phase shift between the channels is similar between PWM and current regulation. Figure 26 shows the
simplified current regulation loop.
HSDx
SPI
Current Value
Setting
Current
LSDx - PI-controler
Measurement + Digital Processing
(digital convertion)
PWM Duty Cycle

Control
Figure 26. Simplified current regulated loop for LSDx

Digital PI-controller with the transfer function is programmed via the SPI.
Transfer function = KI / (z–1) + KP
900719
Integrator feedback register I charac bits (x_KI[3:0] bits) define the regulation behavior per channel. The default value is 1/8. Integrator
feedback register P charac bits (x_KP[3:0] bits) define the regulation behavior per channel. The default value is 1. A high controller
feedback value accelerates the regulator feedback and provides a faster settling of the regulated current after disturbances like a battery
voltage surge. If the measured current does not reach the expected value (ICR_DELTA) after tCR_ERR, the x_CRER bit is set high. The
management of the PI-controller saturation is controllable with the ICLAMP SPI bit. The ICLAMP bit is a read/write SPI bit controlling the
PI filter integrator clamp level. It is necessary to clamp the integrator level for anti-windup on the current regulated valves.
• Bit = 0: integrator limit is 0x03FF
• Bit = 1: integrator limit is 0x07FF
6.15.7 Protection and diagnostics

The 900719 is self-protected against overcurrent and overtemperature at each output. These stages are diagnosed individually (that is,
open load detection) and fault per channel (that is, overcurrent and overtemperature) is reported by the SPI. The 900719 includes an
enhanced automatic valves diagnostic, called AVD.
6.15.7.1 LSDx valve open detection

This diagnostic only operates in the off-state of the low-side switch with x_EN bit set to logic [1]. This feature is available for each valve
driver. The open condition is reported in the SPI (x_OP bits), when the LSDx output voltage is below OPLSD (due to the pull-down current
source, called ISINK_LSD) for the defined filter time (tOP_LSD). In this case, the SPI error flag bit is set. This feature allows detecting a short-
to-ground in the off-state as well. The open condition of the current regulated valve driver may not be detected when the duty cycle of the
low-side FET is 0%, because the high-side FET is fully on.
6.15.7.2 HSDx active freewheeling diode open detection (for current regulated valves
only)
This function only operates during automatic valve diagnostic patterns. The open condition is reported in the SPI when the HSDx output
is below the VOPHSD (due to the pull-up current source, called ISOURCE_HSD) for the tOP_HSD filter time.
• HSD_OPEN_L bit corresponds to HSD1 pin disconnection
• HSD_OPEN_R bit corresponds to HSD2 pin disconnection
6.15.7.3 LSDx drain-to-source voltage reporting

This feature uses the valve open detection circuitry, and operates in on-states and off-states of the low-side switch. The drain-to-source
monitoring gives the real time state of LSDx drain voltage vs OPLSD voltage. The signal is filtered (tVDS_LSDX) and sent through the SPI.
If the LSDx voltage is higher than OPLSD with a filter time (tVDS_LSDX), the x_VDS bit is set to ‘1’ without effecting the LSDx FET.
6.15.7.4 LSDx overcurrent detection

This feature only operates in the on-state of the low-side switch. When the current is above the overcurrent threshold (OCLSD) for the
defined filter time (tOC_LSD), the driver is switched off and a SPI fault bit is set (x_OC bit). The driver can be turned back to the ‘Normal
state’ by a SPI write “1” to the x_OC bit and then turn-on command (x_EN bit).
6.15.7.5 Overtemperature detection

A thermal sensor is localized to each low-side switch. This feature operates in on-states and off-states of the low-side switch. It protects
the high-side for the current regulated valve. When the temperature is above the overtemperature threshold for the defined filter time, the
driver is switched off and a SPI fault bit is set (x_OT bit). The driver can be turned back to a ‘Normal state’ when the temperature returns
to the normal state and then a SPI write ‘1’ to the x_OT bit and a turn-on command (x_EN bit).
6.15.7.6 Overvoltage detection

This feature operates in on-states and off-states of the low-side switch. The fail-safe high-side driver is turned off immediately (tOV_HSD)
if the HSDx pin voltage (one per side) is higher than the OVHSD threshold and a SPI fault bit is set (HSD_OV bit). The fail-safe high-side
driver can be turned back to the ‘normal state’ by a SPI write ‘1’ to the HSD_OV bit and a turn-on command (x_EN bit). Concurrently, the
LSDx low-side switches controlling the valves are turned off, and the HSDx high-side switches controlling the current regulated valves are
turned on to drain the valve’s energy.
900719
6.15.7.7 Automatic valve diagnostic
Before valve operations, the MCU can request an automatic valve diagnostic through the SPI. The automatic valve diagnostic checks:
• HSDx open conditions
• LSDx Open load or shorted to ground
• LSDx shorted to battery
• Load leakage of safe switches
• Overcurrent of safe switches
This sequence duration is faster than 1.0 ms. The automatic valve diagnostic is controlled by the SPI, as shown in Table 36.
Table 36. AVD SPI setting

SPI bits Action
0 (default) Automatic valve diagnostic runs before the operation of 1st valve
AVD
1 Automatic valve diagnostic runs by AVD on-demand
AVD_on_demand 0 (default) No action

(valid for AVD=1) 1 Run after the rising edge of CSB signal
If an automatic valve diagnostic failure occurs:

• AVD_FLT bit is set high
• The valves are not activated
The MCU forces the valves activation with ADV = 1 and AVD_on_demand = 0. The on-demand automatic valve diagnostic is ignored if at
least one valve is in operation. The automatic valve diagnostic is re-enabled if all the valves are off. The automatic valve diagnostic
performs only once (at the first valve enable), even if other valves are turned on after the first. The decoupling capacitor on the HSDx pin
does not exceed 100 nF.
6.15.7.8 Automatic valve short diagnostic

Before valve operations, the MCU can request an automatic valve short diagnostic through the SPI. The automatic valve diagnostic
checks:
• Valve coil short
• Valve coil short together
The automatic valve short diagnostic is controlled by the SPI, as shown in Table 37. Before the sequence, MCU has to turn on the high-
side pre-driver, turn off all LSD, and clear all flag related to valve driver. This sequence duration is less than 1.0 ms. During the diagnostic,
V2V_STAT bit is set to high.
Table 37. AVSD SPI setting

SPI bits Action
0 (default) No action
V2V_RUN
1 Run valve short diagnostic
If an automatic valve short diagnostic failure occurs:

• OC flag is set if the valve is shorted
• OP flag is set if the valve is short together
900719
6.15.8 HSD, LSD electrical characteristics
Table 38. HSD, LSD electrical characteristics
Valve output switching (54)
tDELAY_VALVES LSDx delay time between valve activation 6.1 7.7 9.3 μs
LSDx turn-on and turn-off delay time for digital valves

tDELAY_DIGITAL – 4.5 9.0 μs
• 6.0 V ≤ VPWR ≤ 20 V
tDELAY_CR LSDx turn-on and turn-off delay time for current regulated valves – 2.0 5.0 μs
LSDx rising time for digital valves

tR_DIGITAL 0.5 4.5 9.0 μs
• 6.0 V ≤ VPWR ≤ 20 V
LSDx falling time for digital valves

tF_DIGITAL 0.5 2.0 9.0 μs
• 6.0 V ≤ VPWR ≤ 20 V
LSDx rising and falling times for current regulated valves

tRF_CR 0.25 1.0 4.0 A/μs
• 6.0 V ≤ VPWR ≤ 20 V
Digital valve output (LSD1, 6, 7, 12)
LSDx on-state resistance

RON_LSD – – 300 mΩ
• 5.3 V ≤ VPWR ≤ 20 V
ILEAK_LSD Drain leakage current – – 10 μA
VCL_LSD Active clamp voltage 35 40 45 V
VCL_LSD2 Active clamp voltage HSDx + 15 HSDx + 18 HSDx + 21 V
Current regulated valve output (LSD2, 5, 8, 11)

• 5.3 V ≤ VPWR ≤ 20 V
HSDx on-state resistance

RON_HSD – – 300 mΩ
• 5.3 V ≤ VPWR ≤ 20 V
VCL_LSD3 Active clamp voltage 31 35 39 V
Current regulated valve output (LSD3, 4, 9, 10)

• 5.3 V ≤ VPWR ≤ 20 V
HSDx on-state resistance

RON_HSD – – 300 mΩ
• 5.3 V ≤ VPWR ≤ 20 V
900719
Fault detection
Overcurrent detection threshold current

• TJ =- 40 °C 6.0
IOC_LSD 8.5 11 A
• TJ = 25 °C 5.0
• TJ = 150 °C 5.0
tOC_LSD Overcurrent detection filter time 3.6 4.5 5.5 μs
LSDx open detection
VOP_LSD Open load detection voltage threshold 1.6 2.0 2.4 V

ISINK_LSD LSDx sink current 15 30 60 μA
tOP_LSD Open load detection filter time 14.4 18.2 22 μs
HSDx overvoltage detection (left and right)
VOV-HSD Overvoltage detection threshold 30.2 32 33.8 V
tOV_HSD Overvoltage turn-off time 0.5 – 1.5 μs
HSDx open detection
VOP_HSD Open load detection voltage threshold 1.6 2.0 2.4 V
ISOURCE_HSD HSDx source current 2.0 5.0 10 mA

tOP_HSD Open load detection filter time 43.2 54.6 66 μs
IDOWN_HSD HSDx pull-down current source active during AVD 20 35 50 mA
LSDx drain-to-source voltage reporting
tVDS_LSDX VDS state filter time 14.4 18.2 22 μs
TOTH_LSD Overtemperature shutdown threshold 195 210 225 °C
TOTL_LSD Overtemperature release 180 195 210 °C

tOT_LSD Overtemperature detection filter time 14.4 18.2 22 μs
900719
PWM control (all valves)
Duty cycle programming (10 bits)

x_DC[9:0] or x_I[9:0] bits
• 00 0000 0000 – 0 –
DUTY_VLV • … – – – %
• 10 0000 0000 – 50 –
• … – – –
• 11 1111 1111 – 100 –
Output PWM frequency for LSDx (4 bits)

LF_PWM[3:0] bits
• 0000 2.0
• 0001 2.6
• 0010 3.2
• 0011 3.8
• 0100 4.4
• 0101 5.0
• 0110 5.6
fLF_PWM –15 % +15 % kHz
• 0111 6.2
• 1000 6.8
• 1001 7.4
• 1010 8.0
• 1011 8.6
• 1100 9.2
• 1101 9.8
• 1110 10
• 1111 10
0001 = ±0.5 %/1 step
FM_LSD_MB[3:0] Four SPI bits for frequency modulation band 0010 = ±1.0 %/2 step (53))
…
1111 = ±7.5 %/15 step
00 = 8 cycle
01 = 16 cycle (53)
FM_LSD_MP[1:0] Two SPI bits for frequency modulation period
10 = 32 cycle (default)
11 = 64 cycle
900719
Current regulation
Target current programming (10 bits)
x_I[9:0] bits
• 00 0000 0000 – 0 – mA
ICR
• 00 0000 0001 – 2.2 – mA
• … – – –
• 11 1111 1111 – 2.25 – A
lCR_MIN Minimum regulation current 50 – – mA
Maximum regulation deviation (including ADC error)

• 50 mA ≤ ITARGET < 250 mA – – 25 mA
• at 250 mA –8.0 – 8.0 %
ICR_TC_DELTA
• at 300 mA –8.0 – 8.0 %
• at 350 mA –6.0 – 6.0 %
• 400 mA ≤ ITARGET < 2.25 A –5.0 – 5.0 %
Delta average current versus delay battery voltage (55)

ICR_BAT –3 – 3 %
• 9.0 V ≤ ITARGET ≤ 16 V
Delta average current versus delta temperature of 40 °C for a battery (55)

ICR_TEMP –2 – +2 %
fixed (valid for 9.0 V ≤ ITARGET ≤ 16 V)
Current regulation error

ICR_DELTA • I ≤ 250 mA – 30 – mA
• 250 mA ≤ I ≤ 2.25 A – 12.5 – %
tCR_ERR Current regulation error detection filter item 10.8 12 13.2 ms
Response time at transition 0.4 A to 2.25 A

tR_CR_R – 1.5 – ms
• 6.0 V ≤ VPWR ≤ 20 V
Response time at transition 2.25 A to 0.4 A

tR_CR_F – 2.0 – ms
• 6.0 V ≤ VPWR ≤ 20 V
P charac
• 0111 Factor of P-characteristic = 1.2188
P • 1000 Factor of P-characteristic = 1.0000
• 0000(default) Factor of P-characteristic = 1.0000
900719
Current regulation (continued)
I charac
• 001 Factor of I-characteristic = 0.2500
I • 100 Factor of I-characteristic = 0.3125
• 000(default) Factor of I-characteristic = 0.1250
Notes:
53. Frequency modulation active if FM_LSD_EN bit = 1.
54. 9.0 < VPWR < 16.5 V
55. R40480 delta versus temperature and R40481 delta versus voltage are already included in R40479 total error. Even with the temperature and
voltage variation, the final regulated current accuracy stays within R40479 specified limits.
6.16 Wheel speed sensor interfaces
6.16.1 Introduction
The purpose of this interface is to supply the sensor and receive its output signal simultaneously (current). The 900719 provides four
protected back-to-back high-side switches tied to high-voltage through the WSxx_SUP pin, which can be switched on/off individually via
the SPI (WSx_DIS bits). In nominal mode, all the back-to-back high-side switches are turned on. After WSx_DIS is set to 0, input current
signal is masked for 55 μs if WS_OCF = 0 and 110 μs if WS_OCF = 1. During this period, corresponding WSO oputput is low. The
WSx_ON bit reports the status of each back-to-back high-side switch. WSxx_SUP pins can be supplied by a VPRE voltage or directly by
the battery through a diode (or directly connected to VPWRx pin). Two high-side switches are connected between WS12_SUP, and
respectively WS1_HS and WS2_HS. Two high-side switches are connected between WS34_SUP, and respectively WS3_HS and
WS4_HS.
WS12_SUP
WS34_SUP
Overvoltage Other channels

regulation
Current threshold
22n dectection
Open load / short to

battery detection
Current Overcurrent
Monitoring shutdown
Logic WSAI
Gate Control 4
WSOx
Overtemperature
shutdown
SPI
Short-circuit
between channels
WS1_HS
Hall 22n (x4ch)
Sensor
GND_A
Figure 27. Wheel speed sensor interface block diagram
900719
The status of each switch is reported to the MCU by the SPI. The wheel speed conditioning converts a signal given by an active sensor
into a signal suitable for an MCU digital input. The input signal of an active sensor is a rectangular signal with variable pulse width, and
output currents of two levels (7.0/14 mA) or three levels (7.0/14/28 mA), nominal. The supported sensor types are standard active 2-level
wheel speed sensors (7.0/14 mA), smart active 2-level wheel speed sensors (7.0/14 mA), and VDA type 3-level wheel speed sensors (7.0/
14/28 mA).
6.16.2 Open load and short-to-battery detection

A sensor open load/short-to-battery condition (WSx_HS pin) is detected in the on-state when the current is below the threshold (IWS_OPEN)
for the defined filter time (tWS_OPEN). The corresponding WSx_OP_SH bit is set. To distinguish the fault (open load or short-to-battery),
the MCU turns the switch off using the WSx_DIS bit and waits for the defined filter timer(tWS_SHORT). In the case of an open load, the
WSx_OPEN bit is asserted. If a short-to-battery occurs, the WSx_SH2BAT bit is asserted and the WSx_DIS bit is set. The 900719 can
report sensor-to-sensor faults (WSx_S2S_SH bit), which must be ignored by the MCU.
6.16.3 Reverse current protection

A back-to-back FET is implemented to cutoff the reflow path between WSx_HS versus WSx_SUP, and a SPI fault bit is set
(WSx_REVCUR bits).
6.16.4 Overcurrent detection

When the current is above the overcurrent threshold for the defined filter time, the driver is switched off, and the corresponding WSx_OC
and WSx_DISx bits are set. The high-side driver can be turned back to the ‘normal state’ by a write 1 to the corresponding WSx_OC bit,
and then a turn-on by the SPI command. The overcurrent filter time is selectable for all the wheel speed sensor outputs by the SPI
(WS_OCF bit).

When the temperature is above the overtemperature threshold for the defined filter time, the corresponding driver is switched off, and the
corresponding WSx_OT and WSx_DISx bits are set. The high-side driver can be turned back to the ‘normal state’ by a SPI write 1 to the
corresponding WSx_OT bit, and then a turn-on by the SPI.
6.16.6 Automatic retry mode

In order to reduce SPI traffic, the automatic retry mode is implemented on reverse current, overcurrent, and overtemperature fault
protection. When RETRY_DIS is set to 0, the automatic retry mode activates and the WSS switch turns on in 16 ms. If the fault condition
still remains, the 900719 detects the fault after the corresponding filter time and turns off the WSS switch. If RETRY_DIS is set to 1, the
automatic retry mode is disabled.
6.16.7 Overvoltage regulation

When VPWR is higher than its normal voltage, the WSx_HS module supplies the regulated voltage range for the external wheel speed
sensor power input (WSx_HS).
6.16.8 Short-circuit between 2 WSx_HS channels

This type of fault at the ECU level is diagnosed via the MCU on-demand, by setting the WSx_SD_RUN[1:0] SPI bits, as described in
Table 39. One time of the short-circuit test takes approximately 7.0 ms.
Table 39. Short-circuit diagnostic SPI command setting

SPI bit Value Description
00 Not requested. No change, ‘10’ result still stored
WS1_SD_RUN[1:0]
WS2_SD_RUN[1:0] 01 Default value
WS3_SD_RUN[1:0] 10 Run test, WSx_SD_RUN bit back to 01 automatically
WS4_SD_RUN[1:0]
11 Not requested. No change, ‘10’ result still stored
900719
The WSx_SD_STAT bit is a status flag, which is set to a low during the short-circuit test. The WSx_S2S_SH flag reports a fault, but does
not turn off the sensor.
Table 40. Short-circuit condition flag

SPI bit Value Description
WS1_S2S_SH 0 Pass (No Short)
WS2_S2S_SH
WS3_S2S_SH 1 Fail (Short)
WS4_S2S_SH
6.16.9 WSx_HS electrical characteristics

Table 41. WSx_HS electrical characteristics
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 5.8 V ≤ WSx_SUP ≤ 20 V, – 40 °C ≤ TJ ≤ 150 °C, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Back-to-back high-side
RON-WS On-state resistance 15 22 28 Ω
ILEAK_WS Leakage current in off-state – – 2.5 μA
tWS_R/T_WS_F Rise/fall time – – 10 μs
Open, Short-to-battery detection or sensor-to-sensor short-circuit
IWS_OPEN Sensor error detection threshold 4.025 4.9 5.7 mA

tWS_OPEN Sensor error detection filter time 464 586 720 μs
tWS_SHORT Sensor open or short to battery detection delay filter time 5.7 7.0 7.8 ms
IWS_REV Reverse current detection threshold –16 – –4.0 mA

tWS_REV Reverse current detection filter time 14.4 18.2 22 μs
Overcurrent detection
IWS_OC Overcurrent shut-down threshold 40 60 90 mA
tMSK_WS_OC Overcurrent WSx_HS masking time 14.4 18.2 22 μs
tWS_OC1 Overcurrent shutdown filter time1 (WS_OCF = 1) 14.4 18.2 22 μs
tWS_OC2 Overcurrent shutdown filter time2 (WS_OCF = 2) 57.6 72.8 88 μs
Overtemperature shut-down (57), (58)
TOTH_WSXHS Overtemperature shutdown threshold 195 210 225 °C

TOTL_WSXHS Overtemperature release 170 185 200 °C
tOT_WSXHS Overtemperature detection filter time 14.4 18.2 22 μs
Sensor overvoltage regulation
VWS-OV Voltage limitation 16 18 20 V
Notes:
57. One thermal sensor per WS module (WS12_SUP and WS34_SUP)
58. The parameter is tested at VCC5 = 5.0 V.
900719
6.16.10 Input signal conditioning description
The wheel speed information is provided on four dedicated pins (one for each wheel). The 900719 can adapt three types of wheel speed
sensors:
• Standard sensor (Type I)
• Pass-through mode for PWM-encoded sensors (Type II)
• Pulse encoded sensors (Type III)
The sensor type is selected by the dedicated bit (WSxCFG).
Table 42. Wheel sensor type SPI command setting

SPI command Wheel sensor type WSOx VSO
‘0X’ I WSI10_x Inverse WSOx
WSxCFG[1:0] ‘10’ II WSI10_x rise edge Inverse WSOx
‘11’ III WSI20_x rise edge Inverse WSOx
In those modes, the 900719 sends decoding data and the MCU can also decode.
Internal Sensor
Speed Signal
14 mA
Type I
7mA
14 mA
Type II
7mA
28 mA
Ty pe III 14 mA
7mA
Figure 28. Pulse description for three wheel speed sensor types
6.16.11 Tracking leakage current

Input thresholds A and B can be modified by increasing the wheel speed sensor leakage current. The leakage current tracking module
measures the current of low level inputs (ILOW) and the input thresholds tracks the increment of ILOW. It can help to compensate abnormal
leakage from the sensor to battery (min. value of ILEAK_FLT) or to ground (max value of ILEAK_FLT). The leakage filter time specified
previously (tLEAK_FIT) and SPI flag detection apply only after the leakage compensation has reached its maximum compensation range.
The rate at which the compensation range changes is determined by how the sensor leakage increases (or decreases) over time. It would
typically take three seconds to go through all the increased compensation steps if the leakage condition was set to increase continuously.
Leakage current tracking on each channel can be disabled by each dedicated bit (WSx_TRK_DIS).
900719
6.16.12 Wheel sensor additional information output WSAI
WSAI pin transfers an additional information pulse to the MCU, which is selected by the SPI command (WSAI_S{1:0] bits).
Table 43. WSAI output SPI setting command

SPI command Description
‘00’ WSI10_1 input is selected for WSAI (default)
‘01’ WSI10_2 input is selected for WSAI
WSAI_S[1:0]
Figure 29 shows the output signals for each speed sensor type.
Figure 29. Output signal for each wheel speed sensor type
6.16.13 Input signal conditioning electrical characteristics

Table 44. Input signal conditioning electrical characteristics
Signal current detection
ITH_A Input threshold A 8.75 10.25 11.75 mA

ITH_B Input threshold B 17 20 23 mA
ILEAK_FIT Leakage current compensation range –1.5 – 6.5 mA
tLEAK_FIT Fault leakage detection filter time 232 293 360 μs
900719
6.16.14 Counter description
The wheel speed counter module is composed of four inputs from the current threshold detection, multiplexed by a 2-bit SPI command
(WS_CNT_S[1:0] bits) and one 8-bit counter.
Table 45. Counter SPI command setting

‘00’ WSO1 is selected for counting (default)
‘01’ WSO2 is selected for counting

WS_CNT_S[1:0]
When the WS_CNT_RST bit is set high, the counter resets (WS_COUNTER [7:0] set to ‘0’) during two internal clock cycles, after the
WS_CNT_RST bit is high and the WS_OVF bit is set to a logic [0]. The WS_OVF bit is set to a logic [1] when the counter is in overflow.
When the WS_CNT_RST bit is set low, it has no effect on the counter. When the WS_CNT_EN bit is set high, the counter starts counting,
based on the signal from the multiplexer output after an internal clock cycle. The counter stops counting when the WS_CNT_EN bit goes
low and keeps the last value.
Table 46. Counter control SPI command setting

WS_CNT_RST WS_CNT_EN Description
0 0 Counter stopped. keep previous value (default)
0 1 Counter running start with previous value (continue to run if WS_CNT_EN bit was already 1 before)
1 0 Counter reset at CSB rising edge and stopped at 0 value
1 1 Counter reset at CSB rising edge and start to run started from 0 value
6.16.15 WSAI electrical characteristics

Table 47. WSAI electrical characteristics
Wheel speed counter
fOP Maximum input frequency DC 20 kHz
Digital filter for WSI10, WSI20
Rising/falling edge detection filter time (59)

tF_WS • WS_DF = 0 0.0 0.0 0.0 μs
• WS_DF = 1 14 18 22 μs
Notes:
59. Type I, II and III; no effect on duty cycle of input
6.16.16 Sensor decoding description

The 900719 provides decoding functions for type II and type III wheel speed information. Each duty cycle of the type II sensor and
Manchester code of Type III sensor represents wheel direction and some fault mode for each wheel. This information is decoded by the
900719 and transferred to the MCU via SPI data.
6.16.17 Type II sensor

Each zero crossing of the magnetic signal triggers an output pulse for the type II wheel speed sensor. In addition to the speed signal, the
following information is provided by varying the length of the output pulses), as shown in Figure 30.
900719
Magnetic
Signal
Pulse
Lengt
h t_H
Output
Signal
t_L
Figure 30. Signal from the magnetic sensor

The default condition bits WxT2_DATA[4:0], WxT2_STOP, WxT2_FAIL, and WxT2_NOTLEGAL, are ‘1’. The message goes to default
after every reading of the SPI. Decoding information is transferred to the MCU by an 8-bit bstream of the SPI, as shown in Table 48.
Table 48. Decoding information
WxT2_NOTELEGAL bit
WxT2_STOP bit
WxT2_FAIL bit
Event Pulse length WxT2_DATA[4:0] Bits
Failure signal tH < tTH1 0 0 0 0 0 0 0 0

LR (airgap limit) tTH1 < tH < tTH2 1 0 0 0 0 0 0 0
DR-L (rotation direction left) tTH2 < tH < tTH3 0 1 0 0 0 0 0 0
DR-R (rotation direction right) tTH3 < tH < tTH4 0 0 1 0 0 0 0 0

DR-L and EL (rotation direction left and bad bandgap) tTH4 < tH < tTH5 0 0 0 1 0 0 0 0
DR-R and EL (rotation direction right and bad bandgap) tTH5 < tH < tTH6 0 0 0 0 1 0 0 0
Stop (standing wheel) tTH6 < tH < tTH7 0 0 0 0 0 1 0 0

Sensor failure tH > tTH7 0 0 0 0 0 0 1 0
Information not legal tL < tTH8 0 0 0 0 0 0 0 1
Table 49. Type II timing threshold level

Limit value
Parameter Symbol Unit Condition
Min. Typ. Max.
Timing
Threshold level 1 tTH1 27 32 37 μs
900719
Table 49. Type II timing threshold level (continued)
Limit value
Parameter Symbol Unit Condition
Min. Typ. Max.
Timing (continued)
6.16.18 Type III sensor

For type III wheel speed sensor, the speed is transferred as cyclic pulses, and the additional information is transferred between the speed
pulses with the help of a serial data log. The speed pulse is introduced by an initial bit, which beforehand sets the defined current level to
ILOW. The speed pulse has the current level IHIGH and not required to be located at the position of the terminal change. It is transferred as
a rectangular pulse with level IHIGH over the entire pulse duration and not subject to Manchester coding as the other log bits. The
WxT3_DATA <8:0> bits are designated as the data log and their purpose is to transfer the additional information via the speed pulse, as
presented in Figure 31.
Speed
pulse
I_high(4 X I-low) Data log bits
0 1 2 3 4 5 6 7 8
I_mid(2 X I-low)
I_low(7mA)
Initial bit
North South Terminal North

Terminal Terminal
Figure 31. Speed pulse and data bit description

The data log must be implemented with a Manchester code, whereby binary values are output by flanks, which are located in the middle
in the corresponding time interval. The number of the log bits when at a standstill and at normal speed is defined on 9 (bit 0 to 8) and
reported in WxT3_DATA[8:0] bits. BIT8 is located in LSB. More or less than 9 bits are not ignored and reported in the
WxT3_NOTLEGAL[2:0] bits.
• If it has only 1 good bit, it cannot report 8 missing bits in WxT3_NOTLEGAL[2:0], because the WxT3_NOTLEGAL[2:0] can only store
7 bits. The code sends a ‘CODE_ERROR’ fault instead.
• If there are more than 9 good bits, the code saves the 9 bits sent, but it does not keep counting extra bits. It returns to the initial state
to look for a good start patterns, as it does for all transactions.
6.16.18.1 Nominal speed condition

This begins with an initial bit occupying ILOW for tP/2. The pulse has IHIGH magnitude for tP duration. Each serial bit is coded as shown in
Figure 32.
900719
Speed pulse
Data log 1 1 0 1 1 0 1 0 1
tp/2 tp tp/2 tp tp tp tp tp tp tp tp tp
bit0 bit1 bi t2 bit3 bit4 bit5 bit6 bit7 Parit y

Sensor output
Current
Ini tial bit Speed pulse
Figure 32. Normal speed sensor feedback
6.16.18.2 High speed condition

The initial bit ILOW proceeds the speed pulse for at least tP/2. The serial data log is shortened at high speeds, because the time to the next
speed pulse is shorter than the log cycle. The data bits at the back are therefore ‘cut off’. In each speed range, the maximum possible
number of bits of additional information must be transferred.
Speed pulse
Data log 1 1 0 1 1 0
t_mc
tp /2 tp tp /2 tp tp tp tp tp tp _if
bit0 bit1 bit2 bit3 bit4 bit5

Sensor output
Current
Initial bit Speed pulse
Figure 33. High speed sensor feedback

If there is no edge during inter-frame timing of high speed (tMC_IF), all data bit of the current frame are not valid and the WxT3_CERROR
flag sets to a high.
6.16.18.2.1 Stand still condition

If the sensor does not detect an increment within tSTOP, the data log is transmitted again after a period of tSTOP. This cyclical procedure
is also called the ‘standstill log’.
900719
Speed pulse
t_s top
Data log 1 1 0 1 1 0 1 0 1
tp/2 tp tp/2 t p tp tp tp tp tp tp tp tp
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Parity

Sensor output
Current
Initial bit Speed pulse
Figure 34. Sensor feedback during stand still conditions
6.16.18.3 Manchester decoding

Manchester decoding results transfer to the MCU by a 9-bit stream of the SPI. The following 3 bits indicate the number of not legal bits in
high speed mode. Manchester decoding is reported in the corresponding WxT3_CERROR bit, if no edge is detected in the detection
window. If an code error is detected, Manchester decoding results keep the previous data and a code error bit goes to ‘1’. The code error
flag is reset by a SPI read. All 12 bits are ‘1’ is the default condition, and the message transitions to default after every reading of the SPI.
Table 50 displays the start and stop condition for Manchester decoding.
Table 50. Start and stop condition for manchester

Condition Decoding start Decoding stop
Normal speed 10 mA pulse with tP (AND) 20 mA pulse with tP Receive 9 bits (OR) rising edge of 20 mA pulse
High speed 10 mA pulse with tP (AND) 20 mA pulse with tP Rising edge of 20 mA pulse
Stand still 10 mA pulse with tP Receive 9 bits
Decoding can be restarted after the release of the decoding stop condition. After receiving the start point condition, the 900719 starts
decoding. If the pulse width of the start pulse is longer than tP_MAX or shorter than tP_MIN, decoding is not started. If no message is received
before ‘tSTOP’, the 900719 detects a timeout error.
6.16.19 Type III sensor electrical characteristics

Table 51. Type III sensor electrical characteristics
Timing
tP Pulse width for speed pulse –20 % 50 +20 % μs
tP Pulse width for data pulse –20 % 50 +20 % μs
tP/2 Bit time for data bits –20 % 25 +20 % μs
tSTOP Timeout error without data –20 % 240 +20 % ms
tP_MIN Short start pulse detection 30 35 40 μs
tP_MAX Long start pulse detection 60 75 90 μs
tMC_IF Max. inter-frame timing for high speed condition 2.0 2.3 2.7 ms
900719
6.17 Vehicle speed output VSO
6.17.1 Introduction
VSO is an open drain low-side driver, sending vehicle speed output signals from the VSO_IN (digital input pin) or WSOx. It is selected by
the dedicated SPI VSO_SEL bit. The WSOx output pin is selected by the dedicated VSO_S[1:0] bits.
Table 52. VSO output SPI command setting

0 (default) VSO is controlled by selectable WSOx output from wheel speed sensor interface
VSO_SEL
1 VSO is controlled by VSO_IN input
00 (default) WSO0 reporting

01 WSO1 reporting
VSO_S[1:0]
10 WSO2 reporting
11 WSO3 reporting
Drain-to-source V BAT1
Monitoring
SPI
Open Load
detection 10k
Logic
W heel Speed Overcurrent VSO
Sensor Interface shutdown
W SO1 Gate Control

W SO2 Filter time
Overtemperature
MUX
(tF_VSO)
W SO3 shutdown
MUX
W SO4
VSO _IN GND_P

Figure 35. VSO block diagram
6.17.2 Open load detection

An open condition is detected when the VSO output is below the VOP_VSO threshold for the defined filter time (tOP_VSO), and the fault bit
is set (VSO_OPEN bit). The pull-down current source (ISINK_VSO) is disabled by the VSO_OP_DIS bit. This function is only operating
during the off-state.
6.17.3 Drain-to-source monitoring

The drain-to-source state monitoring gives real time state of the VSO drain voltage vs the OP_vso voltage. This signal is filtered and sent
through the SPI (VSO_VDS bit). If the drain-to-source voltage is higher than OP_vso with a filter time (T1), the VSO_VDS bit is set to ‘1’
without effecting the VSO FET.

When the current is above the overcurrent threshold (OC_VSO) for the defined filter time (tOC_VSO), the driver is switched off and the
dedicated SPI fault bit is set (VSO_OC bit). The driver can be turned back to the ‘normal state’ by writing 1 to the VSO_OC bit, following
the previous SPI configuration command. VSO follows WSOx or VSO_IN from previous SPI command (VSO_SEL configuration bit).

When the temperature is above the OTVSO overtemperature threshold for the defined tOT_VSO filter time, the driver switches off and the
dedicated VSO_OT SPI bit is set. The driver can be turned back to the ‘normal state’ when the temperature returns to the normal state.
VSO follows WSOx or VSO_IN with the previous SPI configuration command (VSO_SEL configuration bit).
900719
6.17.6 VSO electrical characteristics
Table 53. VSO electrical characteristics
Power output
RON_VSO On-state resistance (TJ = 150 °C) – 10 20 Ω
ILEAK_VSO Drain leakage current in off-state – – 10 μA
IDC_VSO DC current capability – – 20 mA
INEG_VSO Maximum negative current for 5.0 ms without damage 10 – – mA
Timing
tF_VSO Rising/falling edge detection filter time 14 18 22 μs
fVSO Transmission frequency – – 10 kHz
tD-ON_VSO/
Turn on/off delay time – – 1.0 μs
tD_OFF_VSO
Open load detection
VOP_VSO Open load detection voltage threshold 1.6 2.0 2.4 V
Sink current
ISINK_VSO 30 50 70 μA
• VSO = 2.0 V during off state
tOP_VSO Open load detection filter time 232 293 360 μs
Drain-to-source monitoring
tVDS_VSO VDS state filter time 14.4 18.2 22 μs
IOC_VSO Overcurrent shutdown threshold current 50 100 150 mA

tOC_VSO Overcurrent shutdown filter time 14.4 18.2 22 μs
TOT_VSO Overtemperature detection threshold 180 195 210 °C
tOT_VSO Overtemperature detection filter time 14.4 18.2 22 μs
6.18 Dual warning lamp pre-drivers WLDx
6.18.1 Introduction
Two warning lamp pre-drivers are implemented. The warning lamp pre-drivers consist of a power FET with an open drain output. The
warning lamp pre-driver is driven either by a SPI command or ADIN1/2. WLD1 and WLD2 are controlled respectively by the corresponding
default state SPI bit. When the ADINx_EN SPI register bit is a logic [1], the ADINx input is dedicated to be used by the ADC and the
WLDx_ON SPI register bit controls the warning lamp WLDx pin. When the ADINx_EN SPI register bit is a logic [0], the ADINx input controls
the warning lamp WLDx pin and is not usable by the ADC. When the ADINx ADC input is selected to control the warning lamp, a high level
on the ADINx input asserts the WDLx output of the warning lamp low. When the WLDx_ON SPI register is selected to control the warning
lamp, a logic [1] in the WLDx_ON SPI register asserts the WDLx output of the warning lamp low. The warning lamp pre-driver is composed
of an output transistor, a pre-driver circuit, and a diagnostic circuitry, are shown in Figure 36.
900719
V BAT1
Drain-to-source
Monitoring
(x2ch)
Open load detection 10 k 10 k 10 k

Logic
Overcurrent WLDx
SPI shutdown
SPI
Gate control
MUX
Overtemperature
shutdown
ADINx GND_P
Figure 36. Warning lamp pre-driver block diagram

The gate pre-driver is responsible for applying the necessary voltage on the output transistor gate to minimize on-state resistance of the
output switch.

The open condition is detected when the WLDx output is below the OPWLD threshold for the defined filter time (tOP_WLD), and the
dedicated WLDx_OP fault bit is set. The pull-down current source (ISINK_WLD) is disabled by the WLDx_OP_DIS bit. This function only
operates during off-state. A permanent open load fault may be reported with the bipolar circuitry described in Figure 41.

Drain-to-source state monitoring gives real time WLDx drain voltage vs OP_wld voltage. This signal is filtered and sent through the
dedicated WLDx_VDS SPI bit. If the VDS voltage is higher than the OPWLD threshold with a tVDS_WLD filter time, the WLDx_VDS bit is set
to ‘1’.

When the current is above the overcurrent threshold (OPWLD) for the defined filter time (tOC_WLD), the driver is switched off and the
WLDx_OC SPI fault bit is set. The driver can be turned back to the ‘normal state’ by a SPI write ‘1’ to the WLDx_OC bit and follows the
previous SPI configuration command.

When the temperature is above the overtemperature threshold OPWLD for the defined filter time tOT_WLD, the driver switches off and the
dedicated WLDx_OT SPI fault bit is set. The driver can be turned back to the ‘normal state’ when the temperature returns to the normal
state and the SPI writes ‘1’ in WLDx_OT bit, then follows the previous SPI configuration command.
900719
6.18.6 WLDx electrical characteristics
Table 54. WLDx electrical characteristics
Power output
RON_WLD On-state resistance (TJ = 150 °C) – 4.0 8.0 Ω
ILEAK_WLD Drain leakage current in off-state – – 10 μA
IDC_WLD DC current capability – – 50 mA
INEG_WLD Maximum negative current for 5.0 ms without damage 10 – – mA
Timing
tD-ON_WLD/
Turn on/off delay time for WLD – – 2.0 μs
tD_OFF_WLD
Open load detection
VOP_WLD Open load detection voltage threshold 1.6 2.0 2.4 V

Sink current
ISINK_WLD 30 50 70 μA
• WLDx = 2.0 V during off state
tOP_WLD Open load detection filter time 232 293 360 μs
tVDS_WLD VDS state filter time 14.1 18.2 22 μs
IOC_WLD Overcurrent shutdown threshold current 60 100 150 mA
tOC_WLD Overcurrent shutdown filter time 14.1 18.2 22 μs
TOT_WLD Overtemperature detection threshold 180 195 210 °C
tOT_WLD Overtemperature detection filter time 14.1 18.2 22 μs
6.19 Analog to digital converter
6.19.1 Introduction
10-bit ADC is referenced to the VCC5 voltage. It is used to read the following voltages:
• Three analog input pins, called ADINx
• Internal voltage supplies
• Average die temperature, which is used by the temperature warning detection circuit (TEMP)
Software engineering can monitor the 900719 internal supply voltage in real time with an ADC SPI reading and can use the fail-safe
function. If these ADC results are not within a certain range, the MCU can reset the 900719. The cyclic conversion sequence is described
in Table 55.
900719
Table 55. Cyclic conversion sequence
Parameters A/D reporting Comment
ADIN1 Input pin voltage

VINT_A Supply voltage for internal ASIC analog function
VINT_D Supply voltage for internal ASIC digital function

VCP Charge pump voltage VCP – VPWR1
VGS_PD Motor pump pre-driver voltage PD_G – PD_S
VGS_HD High-side pre-driver voltage HD_G – HD_S

VCC3P3 VCC3P3 linear regulator voltage
VCC5 VCC5 linear regulator voltage
VCC5_ext VCC5_ext linear regulator voltage

VCC1_CAN 5V-can linear regulator voltage
VCC2_CAN 5V-can linear regulator voltage
VCCA DC/DC converter voltage

VPRE VPRE linear regulator voltage
DOSV DOSV voltage
Die temperature Voltage reflecting the temperature
The ADIN1 and ADIN2 inputs are also used for the warning lamp1/2. The ADIN1/2_en bit of the SPI command is 1, to control the warning
lamp by wld_on bit.
6.19.2 ADIN electrical characteristics

Table 56. ADIN electrical characteristics
ADC
ADC_ERR Total error –6.0 – +6.0 LSB
tCONV Conversion time – 7.0 10 μs
tRFT Refresh time – 180 220 μs
ADINx
IADI_LK Input leakage current –2.0 – +2.0 μA
CADI_CAP Input capacitance – – 30 pF
Internal voltage monitoring (60)
VAD_VINT_A VINT_A monitoring voltage ratio –6.0 % 1.0 +6.0 %
VAD_VINT_D VINT_D monitoring voltage ratio –6.0 % 1.0 +6.0 %

VAD_VCP VCP monitoring voltage ratio –6.0 % 0.2 +6.0 %
VAD_VGS_PD VGS_PD monitoring voltage ratio –6.0 % 0.257 +6.0 %
VAD_VGS_HS VGS_HS monitoring voltage ratio –6.0 % 0.257 +6.0 %
900719
Table 56. ADIN electrical characteristics
Internal voltage monitoring (60)

VCCA monitoring voltage ratio
0.873
• B part
0.837
VAD_VCCA • A part –6.0 % +6.0 %
0.805
• C part
0.315
• D part
VAD_VCC3.3 VCC3P3 monitoring voltage ratio –6.0 % 0.68 +6.0 %
VAD_VCC5 VCC5 monitoring voltage ratio –6.0 % 0.5 +6.0 %

VAD_VCC1_CAN VCC5_EXE monitoring voltage ratio –6.0 % 0.5 +6.0 %
VAD_VCC2_CAN VCC1_CAN monitoring voltage ratio –6.0 % 0.5 +6.0 %
VAD_VPRE VCC2_CAN monitoring voltage ratio –6.0 % 0.5 +6.0 %

VAD_DOSV VPRE monitoring voltage ratio –6.0 % 0.5 +6.0 %
Temperature monitoring
TAD_TEMP Die temperature –20 % – +20 % °C (61)
Notes:
60. ADC resoluation is defined by VCC5 / 1023. The voltage of each parameter is calculated by Resolution x ADC data. Above VCC5, the ADC value
is 3F’hex and below GND 00’hex.
61. T(C) = 368.9 –101.7 x VAD_DEV_TEMP
6.20 ISO K-line and second vehicle speed output
6.20.1 Introduction
K-line module can be used for the following applications:
• ISO K-line interface (bi-direction half-duplex communication interfacing in automotive diagnostic applications)
• Vehicle speed output
Table 57. K-line/VSO2 SPI command setting

0 K-line active (default)
KLINE_DIS
1 VSO2 active
The second VSO reporting comes from the WSOx digital input pins or from the TxK input pin, as presented in Table 58:
Table 58. VSO2 output SPI command setting

0 VSO2 is controlled by WSOx
VSO2_SEL
1 VSO2 is controlled by TxK
00 WSO0 reporting
01 WSO1 reporting
VSO2_S[1:0]
10 WSO2 reporting
11 WSO3 reporting
The WSOx output pin is selected by the VSO2_S[1:0] bits. The ISO K-line driver is composed of an output transistor, a pre-driver circuit,
and diagnostic circuitry, as shown in Figure 37.
900719
Receiver
RxK V BAT2 or V CC5
Drain-to-source or V CC3P3
M onitoring
W heel Speed Logic
SPI
Open Load
Sensor Interface detection 10k
Overcurrent ISO_VSO2
W SO1 shutdown
W SO2 Filter time
MUX
(tF_VSO)
Gate Control
MUX
W SO3
W SO4
Overtem perature
shutdown
TxK GND_P
Figure 37. ISO K-line block diagram

The low-side driver is designed to meet the ‘diagnostic systems ISO9141’ specification. The K-line bus driver's output is fully protected
against bus shorts. The ISO K-line pin is protected against shorts to battery, and the ISO K-line drives up to 10 nF of parasitic capacitance
with a 510 Ω pull-up resister. The MCU ignores the RxK signal reporting in VSO mode.

The driver is switched off and the dedicated ISOK_VSO2_OC SPI bit is set. The driver can be turned back to the ‘normal state’ by a SPI
write 1 to ISOK_VSO2_OC, followed by the previous SPI configuration command.

When the temperature is above the overtemperature threshold (TOTISOK) for the defined filter time (tOT_ISOK), the driver switches off and
the dedicated ISOK_VSO2_OT SPI fault bit is set. The driver can be returned to the ‘normal state’ when the temperature returns to normal.
The SPI then a writes 1 to ISOK_VSO2_OT bit, followed by the previous SPI configuration command.

An open condition is detected when the ISO_VSO2 output is below the threshold (VOPISOK) for the defined filter time (tOP_ISOK) and the
SPI VSO2_OP bit is set to 1. The pull-down current source (ISINK_ISOK) is disabled by the VSO2_OP_DIS bit. This function only operates
during the off-state.

The drain-to-source voltage monitoring gives real time SPI ISOK_VSO2 drain voltage vs the VOPISOK voltage. This signal is filtered and
sent through the dedicated VSO2_VDS SPI bit. If the VDS voltage is higher than VOPISOK with a filter time (T1), VSO2_VDS is set to 1.
900719
6.20.6 ISOK electrical characteristics
Table 59. ISOK electrical characteristics
Power input/output
VIL_ISOK ISO-K input voltage threshold 0.4*VPWR – 0.7*VPWR V

RON_ISOK On-state resistance (TJ = 150 °C) – 8.0 14 Ω
IDC_ISOK DC current capability – – 50 mA
ILEAK_ISOK Drain leakage current in off-state – – 10 μA
INEG_ISOK Maximum negative current for 5.0 ms without damage 10 – – mA
Timings
ISO propagation delay
tPD_ISOK TxK high to TxK low and TxK low to TxK high – – 2.0 μs
RISO = 500 Ω, CISO = 500 pF
RxK propagation delay

tPD_RX ISOK high to ISOK low and ISOK low to ISOK high – – 450 ns
RISO = 500 Ω, CISO = 500 pF
Open load detection
VOP_ISOK Open load detection voltage threshold 1.6 2.0 2.4 V
Sink current
ISINK_ISOK 30 50 70 μA
IISO_VSO2 = 2.0 V during off state
tOP_ISOK Open load detection filter time 232 293 360 μs
tVDS_ISOK VDS state filter time 14.4 18.2 22 μs
IOC_ISOK Overcurrent shutdown threshold current 60 100 150 mA

tOC_ISOK Overcurrent shutdown filter time 14.4 18.2 22 μs
TOT_ISOK Overtemperature detection threshold 180 195 210 °C
tOT_ISOK Overtemperature detection filter time 14.4 18.2 22 μs
900719
6.21 32-bit SPI interface
6.21.1 Introduction
The serial peripheral interface (SPI) has the following features:
• Full duplex, 4-wire synchronous communication
• Slave mode operation only
• Fixed SCLK polarity and phase requirements
• Fixed 32-bit command word
• SCLK operation up to 10 MHz
SPI communication attributes are shown in Figure 38.
tLEAD
tXFER DELAY
CSB
1/fSCLK
tWH tWL
SCLK Don’t care Don’t

care
1
tSU tH1 tSU2 tH2
Bit n*31 Bit n*30 Bit n*29 Bit 0

SI Don’t care ( MSB) ( MSB) Bit1 (LSB ) Don’ t care
tSO(EN) tVALID tSO(DIS)
Bit n*31
Bit1 Bit 0 Don’t
SO ( MSB) Bit n*30 Bit n*29 (LSB ) care
Figure 38. SPI dynamic diagram

The SPI command is composed of 32 SCLK cycles. When receiving data, the MOSI line is latched on the rising edge of each SCLK pulse.
The number of clock cycles occurring on the SCLK pin while the CSB pin is asserted low must be 32. The serial output data is available
on the rising edge of SCLK, and transitions on the falling edge of SCLK. The content of MISO reported by the 900719 depends on the
previous selected register address.
900719
Figure 39. 900719 SPI reporting
On the first SPI communication after reset, the CHIPID register is sent on the MISO. If the number of clock pulses within CSB low is not
32 or if there is a CRC check error, the current SPI write command is ignored and the FMSG bit is set to logic [1]. On the next SPI
command, MISO data reports a SPI transaction error by setting the Err bit to 1.
6.21.2 Watchdog
The 900719 implements a selectable windowed watchdog (T_WD_SEL[2:0] bits) using a ‘challenger’ to ensure a question/answer with
the MCU. The challenger is continuously triggered by the MCU in the open watchdog window, to prevent an error indication from being
generated by the 900719. The watchdog purpose is to ensure both the 900719 and the MCU are ‘alive’ to continue safe operation of the
ESC system:
1. Time (window) ensures both the MCU and the 900719 clocks are running
2. Calculation ensures both the MCU ALU and the 900719 logic are working (not hung up)
3. SPI ensures MCU/900719 communication is OK
Prior to the watchdog timer expiring, the processor should compute the correct 16-bit ALU value and write it to the MCU result (WDMR)
register. This event defines the end of the first watchdog timeout window (and the start of the second). When the WDMR SPI write
command occurs, the 900719 resets the timer, compute the ALU result, and update the 900719 result (WDAR) register. The MCU may
read the WDAR register and compare the 900719 result and the MCU result. Therefore, the MCU can ensure the 900719 is still OK. If no
watchdog reset is generated as a result of the 900719 comparison of WDMR and WDAR, the watchdog timer is reset. The MCU may re-
initialize the LFSR register at any time, and the new SEED used for the next computation. If the seed is not written, the previous LFSR
result is used to generate the next pseudo-random number. Any writes of 16’hFFFF to the seed register is ignored.
900719
900719 MCU
SEED[15:0] SEED Generator
Linear Feedback Linear Feedback
32-bis SPI
Shift Register Shift Register
ALU (Hardware/
ALU (Hardware)
Software)
900719 Result
MCU Result MR[15:0]
AR[15:0]
Compare Result Compare Result

(900719 & MCU) (900719 & MCU)
Fault / Interrupt
ERROR Counter
Handling
Figure 40. 900719 and MCU flow diagram
6.21.3 Watchdog functional mode

By default, when the chip is powered up normally (not in test mode), the watchdog starts automatically after RSTB is released. The MCU
should initialize the LFSR by writing a 16-bit value to the seed register. The initial ALU input is the seed value. For subsequent operations,
each previous16-bit LFSR output loads into the linear feedback shift register (LFSR) and an exclusive-Or logic operation is done as
described in Figure 41. The LFSR output changes for every watchdog calculation.
Figure 41. Linear feedback shift register (LFSR) description

The ALU operation is described in Figure 42.
[15:0] [15:0]
Figure 42. Linear feedback shift register (LSFR) description
900719
A selectable time window is required for each SPI read/write of MR[15:0]/AR[15:0] SPI words. The watchdog window time is changed by
T_WD_SEL[2:0] bits.The timer for the watchdog window is not reset by the watchdog window time change. New window time is set before
the timer reaches the new window time. If this timer expires, the RSTB pin is asserted immediately to reset MCU and the WDFLT SPI bit
is asserted.
MCU Calculation Compare Calculation Compare
MOSI Seed MR1 MR2
MISO AR1 AR2
900719 Calculation Compare Calculation Compare
Time window
Figure 43. MR and AD dynamic diagram
WD_ER_CNT is a 3-bit counter to track the number of MR/AR mismatches. For every mismatch, the count is incremented and for every
match, the count is decremented. If the count gets to 5, the RSTB pin is asserted to reset the MCU and the ALU_OVRFLW SPI flag is set.
6.21.4 Watchdog fault mode

If either watchdog fault occurs while in functional mode, the appropriate SPI flag is set and the RSTB pin is asserted. The SPI map is reset.
In addition, the watchdog is reset any time the 900719 pulls the RSTB pin low, and also any time the MCU pulls the RSTB pin low.
6.21.5 Watchdog disable mode

The watchdog function is disabled by hardware configuration or a SPI command by the following procedure:
Hardware configuration
• Apply 3.3 V on the DEBUG pin when the 900719 is awakened.
SPI command
1. The WD_DIS bit must be set to logic [1]
2. The watchdog random number must be read in WD_RN[7:0] bits (WDRN)
3. The MCU computes the 16-bit ALU, result using a 16-bit seed value = WDRN:WDRN
4. The MCU writes the 16-bit ALU result from step 3 to the WDMR register.
The MCU is able to check if the sequence is correct using the WD_DIS bit read back (= 1). The watchdog random number normally always
reads ‘0’. In this way, the MCU/firmware does not know it is there. Only after the WD_DIS bit is set is this parameter a non-zero.
The watchdog function is reactivated by the following procedure.
1. Set the WD_DIS bit to logic [0]
2. Set the seed value in WDSEED[15:0]
3. Write the 16-bit ALU result to the WDMR register
4. Continue the watchdog operation
Note: Step 1 to 3 should be completed while watchdog window is open.
900719
6.21.6 SPI integrity check
The 900719 checks all incoming frames for the correct CRC. If the CRC is invalid, the data is discarded (no data is stored internally) and
the CRC error flag is set in the SPI. Both the 900719 and the SPI master checks the CRC of their received data by processing all 32 SPI
bits.
C0 C1 C2 C3 C4 C5 C6 C7
Input
Data
T T T T T T T T
2 3 4 5 6 7 8
1*1 1*X 1*X 1*X 0*X 1*X 0*X 0*X 1*X
Figure 44. CRC description

The command and response CRC is fixed at 8-bits in length. The CRC is calculated using the polynomial x8 + x5 + x3 + x2 + x +1
(100101111) with a seed value of binary ‘11111111’. If the end value in the CRC register is equal to zero, the message was received
correctly. If the CRC register contains anything other than zero, there was a receive error and the data should not saved or used. Both
the 900719 and the SPI master calculate the TX CRC over bits [31:8], and append the eight bit CRC value as bits [7:0], thus completing
the 32-bit SPI message to be sent. Due to integrity checks, it is not possible to use the 900719 in a daisy chain configuration with other
SPI ports on other chips in the system.
6.21.7 SPI mapping

The SPI message contains the following fields:
• R/W bit for MOSI (0: Read, 1: Write) and error bit for MISO (1 if an error occurred during the previous SPI transfer)
• A[6:0] address of register (The address for MISO is the address from the last SPI transaction, and is zero after a reset.)
• D[15:0] data of register
• CRC[7:0] CRC content
bit31 bit30 bit29 Bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
MOSI W/R A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
D7 D6 D5 D4 D3 D2 D1 D0 CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0
Figure 45. SI SPI description
bit31 bit30 bit29 Bit28 bit27 bit26 bit25 bit24 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16
MISO Err A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
D7 D6 D5 D4 D3 D2 D1 D0 CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0
Figure 46. SO SPI description

The MOSI and MISO mapping register is described in Table 61. Each SPI bit operates as shown in Table 60.
Table 60. SPI bit operation

Code Type Description
R/W Read / Write Bit cleared with SPI reset
R Read only Real time (monitor no clear)

RLR Read only Latched,set/reset with read
RLW Read only Latched,clear with write '1'
R/W/M Read / Write / Modify Bit cleared with SPI reset
900719
6.21.8 Register address table
Table 61. Register mapping
Address
Register Description Table ref
A6 A5 A4 A3 A2 A1 A0 Hex
CHIPID 0 0 0 0 0 0 0 00 Chip information Table 62
SVCFG_BIST 0 0 0 0 0 0 1 01 Supervision config Table 64
VCCA_CLCK 0 0 0 0 0 1 0 02 VCCA frequency modulation parameters Table 66
WSCFG1 0 0 0 0 0 1 1 03 Wheel speed sensor 1/2/3/4 config1 Table 68
WSCFG2 0 0 0 0 1 0 0 04 Wheel speed sensor 1/2/3/4 config2 Table 70
VLVCLK 0 0 0 0 1 0 1 05 Valve clock frequency modulation and AVD config Table 72
LSD3/4K 0 0 0 0 1 1 0 06 LSD3 and LSD4 KP/KI settings Table 74
HSDCFG 0 0 0 1 0 1 0 0A High-side driver configuration Table 79
PMDCLK 0 0 0 1 0 1 1 0B Pump motor driver clock parameters Table 81
CAN_CFG 0 0 0 1 1 0 0 0C CAN1 and CAN2 configuration register Table 83
ABISTFAIL 0 0 0 1 1 0 1 0D ABIST fault information Table 85
STUCKAT 0 0 0 1 1 1 0 0E ABIST STUCK-AT information Table 87
ABIST_DIS 0 0 0 1 1 1 1 0F ABIST disable config Table 89
WS_COUNT 0 0 1 0 0 0 0 10 Wheel speed counter Table 91
WS_S2S 0 0 1 0 0 0 1 11 Wheel speed sensor to senor short test Table 93
VLVEN 0 0 1 0 0 1 0 12 Enable for 12 valves, safe FET, and pump motor driver Table 95
LSD1DC 0 0 1 0 0 1 1 13 Duty cycle for PWM – LSD1 Table 97
LSD3I 0 0 1 0 1 1 1 17 Current setting for LSD3 Table 102
LSD10I 0 0 1 1 0 1 0 1A Current setting for LSD10 Table 106
LSD2I 0 0 1 1 0 1 1 1B Current setting for LSD2 Table 107
LSD11I 0 0 1 1 1 0 0 1C Current setting for LSD11 Table 108
LSD5I 0 0 1 1 1 0 1 1D Current setting for LSD5 Table 109
LSD8I 0 0 1 1 1 1 0 1E Current setting for LSD8 Table 110
PMDCFG 0 0 1 1 1 1 1 1F Pump motor driver configuration Table 111
WDCFG 0 1 0 0 0 0 0 20 Watchdog configuration Table 113
WDSEED 0 1 0 0 0 0 1 21 Watchdog seed Table 115
WDMR 0 1 0 0 0 1 0 22 Watchdog MCU result Table 117
WDAR 0 1 0 0 0 1 1 23 Watchdog ASIC result Table 119
ADIN1 0 1 0 0 1 0 0 24 ADC value of ADIN1 Table 121
900719
Table 61. Register mapping (continued)
Address
Register Description Table ref
A6 A5 A4 A3 A2 A1 A0 Hex
AD_VGS_HS 0 1 0 0 1 1 1 27 ADC value of VGS_HS Table 127
AD_DOSV 0 1 0 1 0 0 0 28 ADC value of DOSV Table 129
AD_VINTA 0 1 0 1 0 0 1 29 ADC value of VINT_A Table 131
AD_VINTD 0 1 0 1 0 1 0 2A ADC value of VINT_D Table 133
AD_VCP 0 1 0 1 0 1 1 2B ADC value of VCP Table 135
AD_VGS_PD 0 1 0 1 1 0 0 2C ADC value of VGS_PD Table 137
AD_VCC3P3 0 1 0 1 1 0 1 2D ADC value of VCC3P3 Table 139
AD_VCC5 0 1 0 1 1 1 0 2E ADC value of VCC5 Table 141
AD_VCC5EXT 0 1 0 1 1 1 1 2F ADC value of VCC5_EXT Table 143
AD_CAN1 0 1 1 0 0 0 0 30 ADC value of VCC_CAN1 Table 145
AD_CAN2 0 1 1 0 0 0 1 31 ADC value of VCC_CAN2 Table 147
AD_VPRE 0 1 1 0 0 1 0 32 ADC value of VPRE Table 149
AD_VCCA 0 1 1 0 0 1 1 33 ADC value of VCCA Table 151
AD_DIETMP 0 1 1 0 1 0 0 34 ADC value of die temperature Table 153
INT1 0 1 1 0 1 0 1 35 Interrupt register Table 155
LSD1/6/7/12F 0 1 1 0 1 1 0 36 LSD1, LSD6, LSD7 and LSD12 error flags Table 157
LSD3/4/9/10F 0 1 1 0 1 1 1 37 LSD3, LSD4, LSD9, LSD10 error flags Table 159
LSD2/ 5/8/11F 0 1 1 1 0 0 0 38 LSD2, LSD5, LSD8, LSD11 error flags Table 161
VLV_PMDF 0 1 1 1 0 0 1 39 Safe FET HSD and pump motor driver error flags Table 162
SVFLT 0 1 1 1 0 1 0 3A Supervision faults Table 164
VREG_FLG 0 1 1 1 0 1 1 3B Voltage regulator error flags Table 166
WSS12FLT 0 1 1 1 1 0 0 3C Wheel speed sensor 1/2 fault Table 168
WSS34FLT 0 1 1 1 1 0 1 3D Wheel speed sensor 3/4 fault Table 170
WSI1_T2 0 1 1 1 1 1 0 3E Wheel speed sensor 1 Type2 data Table 171
WSI2_T2 0 1 1 1 1 1 1 3F Wheel speed sensor 2 Type2 data Table 173
WSI3_T2 1 0 0 0 0 0 0 40 Wheel speed sensor 3 Type2 data Table 174
WSI4_T2 1 0 0 0 0 0 1 41 Wheel speed sensor 4Type2 data Table 175
WSI4_T3 1 0 0 0 1 0 1 45 Wheel speed sensor 4Type3 data Table 180
CAN_FLG 1 0 0 0 1 1 0 46 CAN1 and CAN2 error flags Table 181
WLD12 1 0 0 0 1 1 1 47 WLD configuration and error flags Table 183
ISOKVSO12 1 0 0 1 0 0 0 48 VSO configuration and error flags Table 185
VLV_VDS 1 0 0 1 0 0 1 49 Valve VDS monitoring Table 187
900719
6.21.9 Details of register mapping
6.21.9.1 Message #00 - CHIPID

Table 62. SPI command register
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VCCA_VSEL
Function FIN[1:0] FAB[1:0] MAJ_REV[2:0] MIN_REV[2:0]
[1:0]
0 0 0 0
Element R R R R R R R R R R R R
Default X X X X X X X X X X X X
Table 63. Description and configuration of the bits

Field Bit Description
00 VCCA = 1.25 V
VCCA_VSEL 01 VCCA = 1.20 V

[1:0] 10 VCCA = 1.30 V
11 VCCA = 3.30 V
FIN[1:0] xx Chip ID information
MAJ_REV[2:0] xx Chip ID information
MIN_REV[2:0] xx Chip ID information
6.21.9.2 Message #01 - SVCFG_BIST

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VCC5E PMD_ CLKFAI VPWR2 VPWR1 VCCAU VCC5E VCC5U VCC3P3 CPFAIL
Function OC_DI ABIST_RUN[1:0] LBIST_RUN[1:0] PWRDNCFG[1:0] LDIS OVDIS OVDIS VDIS XTUVDI VDIS UVDIS DIS
XTDIS S S
Element R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0

0 VCC5_EXToutput enable
VCC5EXTDIS
1 VCC5_EXToutput disable
0 PMD overcurrent detection enable
PMD_OC_DIS
1 PMD overcurrent detection disable
00 Ignored
01 Default
ABIST_RUN[1:0]
10 ABIST RUN
11 Ignored
00 Ignored
01 Default
LBIST_RUN[1:0]
10 LBIST RUN
11 Ignored
900719
Table 65. Description and configuration of the bits (continued)
00 LV and UV condition: zone 1 = safe mode, zone 2 = safe mode
01 LV and UV condition: zone 1 = normal mode, zone 2 = safe mode
PWRDNCFG[1:0]
10 LV and UV condition: zone 1 = normal mode, zone 2 = safe mode
11 LV and UV condition: zone 1 = normal mode, zone 2 = extended mode
0 14 MHz main/alt clock failure causes safe-mode and SPI flag is set
CLKFAILDIS
0 VPWR2 overvoltage causes safe mode and the SPI flag is set
VPWR2OVDIS
0 VPWR1 overvoltage causes safe mode and the SPI flag is set
VPWR1OVDIS
0 VCCA undervoltage causes safe mode, and the SPI flag is set
VCCAUVDIS
0 VCC5_EXT undervoltage causes external vcc5ext regulator shutdown (only) and the SPI flag is set
VCC5EXTUVDIS
0 VCC5 undervoltage causes safe mode, and SPI flag
VCC5UVDIS
0 VCC3P3 undervoltage causes safe mode, and SPI flag
VCC3P3UVDIS
0 Charge Pump undervoltage causes safe mode and SPI flag
CPFAILDIS
6.21.9.3 Message #02 - VCCA-CLCK

Function – – – – – – FM_CP_ FM_CP_ FM_OSC FM_OSC CLKMO FM_VCCA_MB[1:0] FM_VCCA_MP[1:0] FM_VCC

AMP EN _AMP _EN NDIS A_EN
Element – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default – – – – – – 0 0 0 0 0 0 0 1 0 0

0 CP frequency modulation band 1: Typ. 350 kHz
FM_CP_AMP
1 CP frequency modulation band 2: Typ. 700 kHz
0 CP frequency modulation disabled
FM_CP_EN
1 CP frequency modulation enable
0 Main clock frequency modulation band 1: Typ. 350 kHz
FM_OSC_AMP
1 Main clock frequency modulation band 2: Typ. 700 kHz
0 CP frequency modulation disabled
FM_OSC_EN
1 CP frequency modulation enable
900719
0 14 MHz main/alt clocks and clock monitoring logic are enabled
CLKMONDIS
1 14 MHz alt clock and clock monitoring logic disabled
00 VCCA frequency modulation band: no modulation
01 VCCA frequency modulation band: ± 3.15 % / 1 step
FM_VCCA_MB[1:0]
10 VCCA frequency modulation band: ± 6.30 % / 2 step
11 VCCA frequency modulation band: ±12.6 % / 3 step
00 VCCA frequency modulation period: 8
FM_VCCA_MP[1:0]
0 VCCA frequency modulation disable
FM_VCCA_EN
1 VCCA frequency modulation enable
6.21.9.4 Message #03 - WSCFG1

Function WS4_DI
S
WS4_T
RK_DIS WS4CFG[1:0] WS3_DI WS3_T
S RK_DIS WS3CFG[1:0] WS2_DI WS2_T
S RK_DIS WS2CFG[1:0] WS1_DI WS1_T
S RK_DIS WS1CFG[1:0]
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 Wheel speed sensor power supply channel 4 enable
WS4_DIS
1 Wheel speed sensor power supply channel 4 disable
0 Leakage current tracking on channel 4 enable
WS4_TRK_DIS
1 Leakage current tracking on channel 4 disable
00 Wheel speed sensor channel 4 Type I
WS4CFG[1:0]
10 Wheel speed sensor channel 4 Type II
11 Wheel speed sensor channel 4 Type III
WS3_DIS
WS3_TRK_DIS
WS3CFG[1:0]
900719
WS2_DIS
WS2_TRK_DIS
WS2CFG[1:0]
WS1_DIS
WS1_TRK_DIS
WS1CFG[1:0]
6.21.9.5 Message #04 - WSCFG2

Function – –
RETR VSO_S[1:0] VSO2_S[1:0] WS_OT WS_DF WS_OC WSAI_S[1:0] WS_CN WS_CN WS_CNT_S[1:0]
Y_DIS _DIS F T_EN T_RST
Element – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default – – 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 WSS automatic retry mode enable
RETRY_DIS
1 WSS automatic retry mode disable
00 WSO0 reporting
01 WSO1 reporting
VSO_S[1:0]
10 WSO2 reporting
11 WSO3 reporting
00 WSO0 reporting
01 WSO1 reporting
VSO2_S[1:0]
10 WSO2 reporting
11 WSO3 reporting
0 WSS overtemperature shutdown enable
WS_OT_DIS
1 WSS overtemperature shutdown disable
900719
0 WSS rising/falling edge detection filter time = 0 μs
WS_DF
1 WSS rising/falling edge detection filter time = 18 μs
0 WSS overcurrent shutdown filter time = T1
WS_OCF
1 WSS overcurrent shutdown filter time = 4*T1
00 WSI10_1 input is selected for WSAI
WSAI_S[1:0]
0 Wheel speed counter disable
WS_CNT_EN
1 Wheel speed counter enable
0 Wheel speed counter does not reset
WS_CNT_RST
1 Wheel speed counter reset
00 WSO1 is selected for counting
WS_CNT_S[1:0]
6.21.9.6 Message #05 - VLVCLK

TDEL_V AVD_O VLV_SY FM_LSD
Function ICLAMP _DIS D AVD NC_SEL LF_PWM[3:0] FM_LSD_MB[3:0] FM_LSD_MP[1:0] _EN
Default 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0

0 The PI filter integrator clamp limit is 0x03FF
ICLAMP
1 The PI filter integrator clamp limit is 0x07FF
0 The delay between each valve’s activation enable
TDEL_V_DIS
1 The delay between each valve’s activation is 0
0 No active
AVD_OD
1 AVD on demand, active after the rising edge of CSB signal
0 Automatic valve diagnostic enabled before the operation of 1st valve
AVD
1 Automatic valve diagnostic on-demand
0 Valve duty/current changes at the next PWM period
VLV_SYNC_SEL
1 Valve duty/current changes when corresponding x_EN bit is set to 1
LF_PWM[3:0] – Output PWM frequency for LSDx setting
FM_LSD_MB[3:0] – Frequency modulation band setting
900719
00 Frequency modulation period = 8
FM_LSD_MP[1:0]
0 Frequency modulation disable
FM_LSD_EN
6.21.9.7 Message #06 - LSD3/4K

Function – – LSD4_KI[2:0] LSD4_KP[3:0] LSD3_KI[2:0] LSD3_KP[3:0]
Default – – 0 0 0 0 0 0 0 0 0 0 0 0 0 0

001 Factor of I-characteristic = 0.2500
X_KI[2:0]
900719
0111 Factor of P-characteristic = 1.2188
X_KP[3:0]
6.21.9.8 Message #07 - LSD9/10K

Default – – 0 0 0 0 0 0 0 0 0 0 0 0 0 0
See Table 75 for bit description and configuration.
6.21.9.9 Message #08 - LSD2/11K

Default – – 0 0 0 0 0 0 0 0 0 0 0 0 0 0
900719
6.21.9.10 Message #09 - LSD5/8K
Default – – 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.21.9.11 Message #0A - HSDCFG

HSD_O
Function – – – – – – – – V2V_RU C_MAS HSD_OC_TIME[1: HSD_OC_SEL[2:0] HSD_S
N 0] R
K
Element – – – – – – – – R/W R/W R/W R/W R/W R/W R/W R/W
Default – – – – – – – – 0 0 0 1 0 0 1 0

0 Overcurrent detection is not masked
HSD_OC_MASK
1 Overcurrent detection fault is masked
0 No action
V2V_RUN
1 Run automatic valve short diagnostic
00 Programmable overcurrent detection filter Time = 18.2 ms
01 Programmable overcurrent detection filter Time = 147 ms
HSD_OC_TIME[1:0]
000 Overcurrent detection VDS = 0.69 V
HSD_OC_SEL[2:0]
0 Turn-off current 100 μA
HSD_SR
1 Turn-off current 2.0 mA
900719
6.21.9.12 Message #0B - PMDCLK
Function – – – – F_PMD[4:0] FM_PMD_MB[3:0] FM_PMD_MP[1:0] FM_PM

D_EN
Element – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default – – – – 1 1 0 0 0 0 0 0 0 1 0 0

F_PMD[4:0] x Output PWM frequency setting for pump driver
FM_PMD_MB[3:0] x Frequency modulation band setting for pump driver
FM_PMD_MP[1:0]
FM_PMD_EN
1 Frequency modulation enable
6.21.9.13 Message #0C - CAN_CFG

CAN2T CAN2_ CAN1T CAN1_
Function – – – – – – – – – – – XRXDI MODE XRXDI MODE
S S
Element – – – – – – – – – – – – R/W R/W R/W R/W
Default – – – – – – – – – – – – 0 1 0 1

0 CAN2 transceiver active
CAN2TXRXDIS
1 Only VCC2_CAN active including UV/OV protections
0 CAN2 low-power mode
CAN2_MODE
1 CAN2 normal mode
0 CAN1 transceiver active
CAN1TXRXDIS
1 Only VCC1_CAN active including UV/OV protections
0 CAN1 low-power mode
CAN1_MODE
1 CAN1 normal mode
900719
6.21.9.14 Message #0D - ABISTFAIL
VCC5E VCC5V VCCAV RSTBFA CPUVF VCC5E
VCCAU XUVFAI VCC5U VCC3U PD_DO HD_DO VPWR2 VPWR1 VPWR1 VPWR2 VPWR1
Function XOTFAI CC3OT PREOT
L FAIL FAIL IL AIL VFAIL L VFAIL VFAIL VFAIL VFAIL OVFAIL OVFAIL UVFAIL LVFAIL LVFAIL
Element R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 No fault
VCC5EXOTFAIL
1 ABIST failed on VCC5_EXT OT detection check
0 No fault
VCC5VCC3OTFAIL
1 ABIST failed on VCC5 or VCC3P3 OT detection check
0 No fault
VCCAVPREOTFAIL
1 ABIST failed on VCCA or VPRE OT detection check
0 No fault
RSTBFAIL
1 ABIST failed on RSTB detection check
0 No fault
CPUVFAIL
1 ABIST failed on charge pump UV detection check
0 No fault
VCCAUVFAIL
1 ABIST failed on VCCA UV detection check
0 No fault
VCC5EXUVFAIL
1 ABIST failed on VCC5_EXE UV detection check
0 No fault
VCC5UVFAIL
1 ABIST failed on VCC5 UV detection check
0 No fault
VCC3UVFAIL
1 ABIST failed on VCC3P3 UV detection check
0 No fault
PD_DOVFAIL
1 ABIST failed on PD_D OV detection check
0 No fault
HD_DOVFAIL
1 ABIST failed on HD_D OV detection check
0 No fault
VPWR2OVFAIL
1 ABIST failed on VPWR2 OV detection check
0 No fault
VPWR1OVFAIL
1 ABIST failed on VPWR1 OV detection check
0 No fault
VPWR1UVFAIL
1 ABIST failed on VPWR1 UV detection check
0 No fault
VPWR2LVFAIL
1 ABIST failed on VPWR2 LV detection check
900719
0 No fault
VPWR1LVFAIL
1 ABIST failed on VPWR1 LV detection check
6.21.9.15 Message #0E - STUCKAT

VCC5E VCC5V VCCAV RSTB_S CPUV_ VCCAU VCC5E VCC5U VCC3U PD_DO HD_DO VPWR2 VPWR1 VPWR1 VPWR2 VPWR1
Function XOT_SA CC3OT_ PREOT A SA V_SA XUV_SA V_SA V_SA V_SA V_SA OV_SA OV_SA UV_SA LV_SA LV_SA
SA _SA
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 The comparator is stuck at low
VCC5EXOT_SA
1 The comparator is stuck at high
VCC5VCC3OT_SA
VCCAVPREOT_SA
RSTB_SA
CPUV_SA
VCCAUV_SA
VCC5EXUV_SA
VCC5UV_SA
VCC3UV_SA
PD_DOV_SA
HD_DOV_SA
VPWR2OV_SA
VPWR1OV_SA
900719
VPWR1UV_SA
VPWR2LV_SA
VPWR1LV_SA
6.21.9.16 Message #0F - ABIST_DIS

VCC5E VCC5V VCCAV VCC5E VPWR2 VPWR1 VPWR1 VPWR2 VPWR1
Function XOT_A CC3OT_ PREOT RSTB_A
DIS
CPUV_
ADIS
VCCAU
V_ADIS XUV_A VCC5U VCC3U PD_DO HD_DO
V_ADIS V_ADIS V_ADIS V_ADIS OV_ADI OV_ADI UV_ADI LV_ADI LV_ADI
DIS ADIS _ADIS DIS S S S S S
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 VCC5_EXT OT detection check enable
VCC5EXOT_ADIS
1 VCC5_EXT OT detection check disable
0 VCC5 or VCC3P3 OT detection check enable
VCC5VCC3OT_ADIS
1 VCC5 or VCC3P3 OT detection check disable
0 VCCA or VPRE OT detection check enable
VCCAVPREOT_ADIS
1 VCCA or VPRE OT detection check disable
0 RSTB detection check enable
RSTB_ADIS
1 RSTB detection check disable
0 CP UV detection check enable
CPUV_ADIS
1 CP UV detection check disable
0 VCCA UV detection check enable
VCCAUV_ADIS
1 VCCA UV detection check disable
0 VCC5_EXE UV detection check enable
VCC5EXUV_ADIS
1 VCC5_EXE UV detection check disable
0 VCC5 UV detection check enable
VCC5UV_ADIS
1 VCC5 UV detection check disable
0 VCC3P3 UV detection check enable
VCC3UV_ADIS
1 VCC3P3 UV detection check disable
0 PD_D OV detection check enable
PD_DOV_ADIS
1 PD_D OV detection check disable
0 HD_D OV detection check enable
HD_DOV_ADIS
1 HD_D OV detection check disable
900719

0 VPWR2 OV detection check enable
VPWR2OV_ADIS
1 VPWR2 OV detection check disable
0 VPWR1 OV detection check enable
VPWR1OV_ADIS
1 VPWR1 OV detection check disable
0 VPWR1 UV detection check enable
VPWR1UV_ADIS
1 VPWR1 UV detection check disable
0 VPWR2 LV detection check enable
VPWR2LV_ADIS
1 VPWR2 LV detection check disable
0 VPWR1 LV detection check enable
VPWR1LV_ADIS
1 VPWR1 LV detection check disable
6.21.9.17 Message #10 - WS_COUNT

WS_OV
Function – – – – – – – F WS_COUNTER[7:0]
Element – – – – – – – R R R R R R R R R
Default – – – – – – – 0 0 0 0 0 0 0 0 0

0 No event
WS_OVF
1 Wheel speed counter over flow flag
WS_COUNTER[7:0] Wheel speed counter value
6.21.9.18 Message #11 - WS_S2S

WS4_O WS3_O WS2_O WS1_O WS4_S WS3_S WS2_S WS1_S
Function N N N N D_STAT D_STAT D_STAT D_STAT WS4_SD_RUN[1:0] WS3_SD_RUN[1:0] WS2_SD_RUN[1:0] WS1_SD_RUN[1:0]
Element R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1

0 WSx_HS high-side switch off
WSx_ON
1 WSx_HS high-side switch on
0 No event
WSx_SD_STAT
1 Short-circuit diagnostic between 2WSx_HS channels running
900719

00 N/A
01 Default value
WSx_SD_RUN[1:0]
10 Execute short-circuit diagnostic between 2 WSx_HS channels
11 N/A
6.21.9.19 Message #12 - VLVEN

Function – – HSD_E PMD_E LSD8_E LSD5_E LSD11_ LSD2_E LSD10_ LSD9_E LSD4_E LSD3_E LSD12_ LSD7_E LSD6_E LSD1_E
N N N N EN N EN N N N EN N N N
Element – – R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M R/W/M
Default – – 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 Driver disable
x_EN
1 Driver enable
6.21.9.20 Message #13 - LSD1DC

Function – – – – – – LSD1_DC[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

x_DC[9:0] PWM duty cycle setting

Function – – – – – – LSD6_DC[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0
900719

Function – – – – – – LSD7_DC[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0
6.21.9.23 Message #16 - LSD12DC

Function – – – – – – LSD12_DC[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0
6.21.9.24 Message #17 - LSD3I

LSD3_F
Function – – – – – DC LSD3_I[9:0]
Element – – – – – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default – – – – – 0 0 0 0 0 0 0 0 0 0 0

0 Current regulated operation
x_FDC
1 PWM duty cycle operation
x_I[9:0] Target current value
6.21.9.25 Message #18 - LSD4I

NO2_FD
Function – – – – – C NO2_I[9:0]
Default – – – – – 0 0 0 0 0 0 0 0 0 0 0
900719

6.21.9.26 Message #19 - LSD9I
Function – – – – – LSD9_F LSD9_I[9:0]

DC
Default – – – – – 0 0 0 0 0 0 0 0 0 0 0
6.21.9.27 Message #1A - LSD10I

Function – – – – – LSD10_ LSD10_I[9:0]

FDC
Default – – – – – 0 0 0 0 0 0 0 0 0 0 0
6.21.9.28 Message #1B - LSD2I

LSD2_F
Default – – – – – 0 0 0 0 0 0 0 0 0 0 0
6.21.9.29 Message #1C - LSD11I

Function – – – – – LSD11_ LSD11_I[9:0]

FDC
Default – – – – – 0 0 0 0 0 0 0 0 0 0 0
900719

6.21.9.30 Message #1D - LSD5I
Function – – – – – LSD5_F LSD5_I[9:0]

DC
Default – – – – – 0 0 0 0 0 0 0 0 0 0 0
6.21.9.31 Message #1E - LSD8I

LSD8_F
Default – – – – – 0 0 0 0 0 0 0 0 0 0 0
6.21.9.32 Message #1F - PMDCFG

PMD_O
Function PMD_L PMD_OC_TIME[1: C_MAS PMD_OC_SEL[2:0] PMD_A PMD_DC[7:0]
DA_DIS 0] K CT
Default 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0

0 If PD_D or HD_D > PD_ov turn on PMD and set PMD_LD flag
PMD_LDA_DIS
00 Programmable overcurrent detection filter Time = 9.0 μs
01 Programmable overcurrent detection filter Time = 18 μs
PMD_OC_TIME[1:0]
0 Overcurrent detection masking time after turn ON = 9.0 μs
PMD_OC_MASK
1 Overcurrent detection masking time after turn ON = 1.1 ms
900719

000 Programmable overcurrent detection VDS = 0.69 V
PMD_OC_SEL[2:0]
0 External low-side FET control disable
PMD_ACT
1 External low-side FET control enable
PMD_DC[7:0] x PWM duty cycle programming
6.21.9.33 Message #20 - WDCFG

Function WD_RN[7:0] WD_DIS T_WD_SEL[2:0] WD_ER_CNT[2:0]
Element R R R R R R R R R/W R/W R/W R/W R R R
Default 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0

WD_RN[7:0] x Watchdog random number
0 WD enable
WD_DIS
1 WD disable
000 Watchdog window timeout check disable = 4.0 ms
001 Watchdog window timeout check disable = 8.0 ms
010 Watchdog window timeout check disable = 16 ms
T_WD_SEL[2:0]
WD_ER_CNT[2:0] x WD error count
900719

6.21.9.34 Message #21 - WDSEED
Function WDSEED[15:0]
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDSEED[15:0] x WD SEED value
6.21.9.35 Message #22 - WDMR

Function WDMR[15:0]
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDMR[15:0] MCU calculation result
6.21.9.36 Message #23 - WDAR

Function WDAR[15:0]
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDAR[15:0] 900719 calculation result
6.21.9.37 Message #24 - ADIN1

Function – – – – – – ADIN1[9:0]
Element – – – – – – R R R R R R R R R R
Default – – – – – – 0 0 0 0 0 0 0 0 0 0
900719

ADIN1[9:0] x 10-bit ADC of ADIN1
6.21.9.38 Message #25 - ADIN2

Function – – – – – – ADIN2[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

6.21.9.39 Message #26 - ADIN3

Function – – – – – – ADIN3[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

6.21.9.40 Message #27 - AD_VGS_HS

Function – – – – – – VGS_HS[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VGS_HS[9:0] x 10-bit ADC of safe HS VGS
900719

6.21.9.41 Message #28 - AD_DOSV
Function – – – – – – DOSV[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

DOSV[9:0] x 10-bit ADC of DOSV
6.21.9.42 Message #29 - AD_VINTA

Function – – – – – – VINT_A[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VINT_A[9:0] x 10-bit ADC of VINT_A
6.21.9.43 Message #2A - AD_VINTD

Function – – – – – – VINT_D[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VINT_D[9:0] x 10-bit ADC of VINT_D
6.21.9.44 Message #2B - AD_VCP

Function – – – – – – VCP_VPWR[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0
900719

VCP_VPWR[9:0] x 10-bit ADC of CP
6.21.9.45 Message #2C - AD_VGS_PD

Function – – – – – – VGS_PD[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VGS_PD[9:0] x 10-bit ADC of pump driver VGS
6.21.9.46 Message #2D - AD_VCC3P3

Function – – – – – – VCC3P3V[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VCC3P3V[9:0] x 10-bit ADC of VCC3P3
6.21.9.47 Message #2E - AD_VCC5

Function – – – – – – VCC5[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VCC5[9:0] x 10-bit ADC of VCC5
900719

6.21.9.48 Message #2F - AD_VCC5EXT
Function – – – – – – VCC5_EXT[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VCC5_EXT[9:0] x 10-bit ADC of VCC5_EXT
6.21.9.49 Message #30 - AD_CAN1

Function – – – – – – VCC1_CAN[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VCC1_CAN[9:0] x 10-bit ADC of VCC1_CAN
6.21.9.50 Message #31 - AD_CAN2

Function – – – – – – VCC2_CAN[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VCC2_CAN[9:0] x 10-bit ADC of VCC2_CAN
6.21.9.51 Message #32 - AD_VPRE

Function – – – – – – VPRE[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0
900719

VPRE[9:0] x 10-bit ADC of VPRE
6.21.9.52 Message #33 - AD_VCCA

Function – – – – – – VCCA[9:0]
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

VCCA[9:0] x 10-bit ADC of VCCA
6.21.9.53 Message #34 - AD_DIETMP

Function – – – – – – DIETEMP[9:0]
Element – – – – – – R R R R R R R R RLW RLW
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

DIETEMP[9:0] x 10-bit ADC of die temperature
6.21.9.54 Message #35 - INT1

Function – VLVFLG WDFLT CAN12_ PMD_F LSD2/5/ LSD3/4/ LSD1/6/ WS34_F WS12_F WLD12_ ISOKVS VREG_ SPRVS CAN_W IGN_W
_F F 8/22_F 9/10_F 7/12_F F O_F F N_F U U
Element – R RLW R R R R R R R R R R R RLW RLW
Default – 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 No fault
VLVFLG_F
1 Fault occurs on safe HS pre-driver. Refer to VLV_PMDF register.
0 No fault
WDFLT
1 Fault occurs on WD
0 No fault
CAN12_F
1 Fault occurs on CAN1 or CAN2. Refer to CAN_FLG register.
900719

0 No fault
PMD_F
1 Fault occurs on PMD. Refer to VLV_PMDF rgister.
0 No fault
LSD2/5/8/11_F
1 Fault occurs on LSD2, LSD5, LSD8 or LSD11. Refer to LSD2/5/8/11F register
0 No fault
LSD3/4/9/10_F
1 Fault occurs on LSD3/4/9/10
0 No fault
LSD1/6/7/12_F
1 Fault occurs on LSD3, LSD4, LSD9 or LSD10. Refer to LSD1/6/7/12 register
0 No fault
WS34_F
1 Fault occurs on WS3 or WS4. Refer to WSS34FLT register.
0 No fault
WS12_F
1 Fault occurs on WS1 or WS2. Refer to WSS12FLT register.
0 No fault
WLD12_F
1 Fault occurs on WLD1 or WLD2. Refer to WLD12 register
0 No fault
ISOKVSO_F
1 Fault occurs on K-line of VSO. Refer to ISOKVSO12 register.
0 No fault
VREG_F
1 Fault occurs on regulators. Refer to VREG_FLG register
0 No fault
SPRVSN_F
1 Fault occurs on supervision. Refer to SVFLT register.
0 No wake-up
CAN_WU
1 CAN wake-up
0 No wake-up
IGN_WU
1 Ignition wake-up
6.21.9.55 Message #36 - LSD1/6/7/12F

Function – LSD12_ LSD12_ LSD12_ LSD7_O LSD7_O LSD7_O LSD6_O LSD6_O LSD6_O LSD1_O LSd1_O LSD1_O
OT OC OP T C P T C P T C P
Element – RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default – 0 0 0 0 0 0 0 0 0 0 0 0
900719

0 No fault
x_OT
1 Overtemperature fault
0 No fault
x_OC
1 Overcurrent fault
0 No fault
x_OP
1 Open load fault
6.21.9.56 Message #37 - LSD3/4/9/10F

Function LSD10_ LSD10_ LSD10_ LSD10_ LSD9_C LSD9_O LSD9_O LSD9_O LSD4_C LSD4_O LSD4_O LSD4_O LSD3_C LSD3_O LSD3_O LSD3_O
CRER OT OC OP RER T C P RER T C P RER T C P
Element RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 No fault
x_CRER
1 Current regulation error
0 No fault
x_OT
1 Overtemperature fault
0 No fault
x_OC
1 Overcurrent fault
0 No fault
x_OP
1 Open load fault
6.21.9.57 Message #38 - LSD2/5/8/11F

Function LSD8_C LSD8_O LSD8_O LSD8_O LSD5_C LSD5_O LSD5_O LSD5_O LSD11_ LSD11_ LSD11_ LSD11_ LSD2_C LSD2_O LSD2_O LSD2_O
RER T C P RER T C P CRER OT OC OP RER T C P
Element RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
900719

6.21.9.58 Message #39 - VLV_PMDF
V2V_ST PMD_L PMD_P PMD_O PMD_O AVD_FL HSD_DI HSD_LE HSD_O HSD_O HSD_O HSD_O HSD_O
Function – – – AT D DD_DIS T C_OP T SC AK T C_OP V PEN_R PEN_L
C
Element – – – RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default – – – 0 0 0 0 0 0 0 0 0 0 0 0 0

0 No action
V2V_STAT
1 Automatic valve short diagnostic enable
0 No fault
PMD_LD
1 PMD or HSD load dump, PD_D or HD_D > PD_ov
0 No fault
PMD_PDD_DISC
1 PD_D disconnection fault
0 No fault
PMD_OT
1 PMD overtemperature fault
0 No fault
PMD_OC_OP
1 PMD overcurrent fault or open fault
0 No fault
AVD_FLT
1 ADV fault
0 No fault
HSD_DISC
1 HD_D disconnection fault
0 No fault
HSD_LEAK
1 HSD leakage fault
0 No fault
HSD_OT
1 HSD overtemperature fault
0 No fault
HSD_OC_OP
1 HSD overcurrent fault or open fault
0 No fault
HSD_OV
1 HSD overvoltage fault
0 No fault
HSD_OPEN_R
1 HSD2 active freewheeling diode open fault
0 No fault
HSD_OPEN_L
1 HSD1 active freewheeling diode open fault
900719

6.21.9.59 Message #3A - SVFLT
DIE_TE
Function ABIST_ LBIST_F ALU_OV – EXT_RS FMSG CLK_FA VPWR2 VPWR2 VPWR1 VPWR1 VPWR1 CP_FAI IREF_F FGND MP_WA
FAIL AIL RFLW T IL _OV _LV _UV _OV _LV L AIL RN
Element R R RLW – RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default 0 0 0 – 0 0 0 0 0 0 0 0 0 0 0 0

0 No fault
ABIST_FAIL
1 ABIST fault
0 No fault
LBIST_FAIL
1 LBIST fault
0 No fault
ALU_OVRFLW
1 WD error counter over flow
0 No fault
EXT_RST
1 External reset happens
0 No fault
FMSG
1 SPI fault, data is not 32-bits
0 No fault
CLK_FAIL
1 Clock fault
0 No fault
VPWR2_OV
1 VPWR2 overvoltage fault
0 No warning
VPWR2_LV
1 VPWR2 low-voltage warning
0 No fault
VPWR1_UV
1 VPWR1 undervoltage fault
0 No fault
VPWR1_OV
1 VPWR1 overvoltage fault
0 No warning
VPWR1_LV
1 VPWR1 low-voltage warning
0 No fault
CP_FAIL
1 CP fault
0 No fault
IREF_FAIL
1 IREF fault
0 No fault
FGND
1 Ground disconnection fault
0 No warning
DIE_TEMP_WARN
1 Die temperature warning
900719

6.21.9.60 Message #3B - VREG_FLG
VCC5E VCC5E VCC5E VPRE_I VPRE_S VPRE_ VPRE_ VCCA_ VCCA_ VCCA_ VCC5_U VCC5_ VCC5_V VCC3P3 VCC3P3
Function – XT_UV XT_OV XT_OT LIM UP_DIS UV OV VPRE_ UV OV V OV CC3_OT _UV _OV
C OT
Element – RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default – 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 No fault
VCC5EXT_UV
1 VCC5_EXT undervoltage fault
0 No fault
VCC5EXT_OV
1 VCC5_EXT overvoltage fault
0 No fault
VCC5EXT_OT
1 VCC5_EXT overtemperature fault
0 No fault
VPRE_ILIM
1 VPRE current limitation
0 No fault
VPRE_SUP_DISC
1 VPRE_SUP disconnection fault
0 No fault
VPRE_UV
1 VPRE undervoltage fault
0 No fault
VPRE_OV
1 VPRE overvoltage fault
0 No fault
VCCA_VPRE_OT
1 VCCA or VPRE overtemperature fault
0 No fault
VCCA_UV
1 VCCA undervoltage fault
0 No fault
VCCA_OV
1 VCCA overvoltage vault
0 No fault
VCC5_UV
1 VCC5 undervoltage fault
0 No fault
VCC5_OV
1 VCC5 overvoltage fault
0 No fault
VCC5_VCC3_OT
1 VCC5 or VCC3P3 overtemperature fault
0 No fault
VCC3P3_UV
1 VCC3P3 undervoltage fault
0 No fault
VCC3P3_OV
1 VCC3P3 overvoltage fault
900719

6.21.9.61 Message #3C - WSS12FLT
WS2_R WS2_S2 W2T1_L WS2_S
Function EVCUR WS2_O WS2_O WS2_O WS2_O WS1_R WS1_S2 W1T1_L WS1_S WS1_O WS1_O WS1_O WS1_O
S_SH KG H2BAT P_SH PEN T C EVCUR S_SH KG H2BAT P_SH PEN T C
Element RLW RLW RLR RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 No fault
WSx_REVCUR
1 WSx reverse current fault
0 No fault
WSx_S2S_SH
1 WSx short-circuit fault
0 No fault
WxT1_LKG
1 WSx leakage current fault, ILOW > ILEAK_FLT
0 No fault
WSx_SH2BAT
1 WSx short to battery fault
0 No fault
WSx_OP_SH
1 WSx open or short to battery fault
0 No fault
WSx_OPEN
1 WSx open fault
0 No fault
WSx_OT
1 WSx overtemperature fault
0 No fault
WSx_OC
1 WSx overcurrent fault
6.21.9.62 Message #3D - WSS34FLT

Function WS4_R WS4_S2 W4T1_L WS4_S WS4_O WS4_O WS4_O WS4_O WS3_R WS3_S2 W3T1_L WS3_S WS3_O WS3_O WS3_O WS3_O
EVCUR S_SH KG H2BAT P_SH PEN T C EVCUR S_SH KG H2BAT P_SH PEN T C
Element RLW RLW RLR RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
900719

6.21.9.63 Message #3E - WSI1_T2
W1T2_L W1T2_N
Function – – KG W1T2_DATA[4:0] W1T2ST W1T2FA OTLEG
OP IL
AL
Element – – RLR RLR RLR RLR RLR RLR RLR RLR RLR
Default – – 0 1 1 1 1 1 1 1 1

0 No fault
WxT2_LKG
WxT2_DATA[4:0] x
WxT2STOP x
WSx Type2 data. Refer to Figure 46
WxT2FAIL x
WxT2_NOTLEGAL x
6.21.9.64 Message #3F - WSI2_T2

W2T2_L W2T2_N
Function – – KG W2T2_DATA[4:0] W2T2ST W2T2FA OTLEG – – – – –
OP IL
AL
Element – – RLR RLR RLR RLR RLR RLR RLR RLR RLR – – – – –
Default – – 0 1 1 1 1 1 1 1 1 – – – – –
6.21.9.65 Message #40 - WSI3_T2

W3T2_L W3T2_N
Function – – KG W3T2_DATA[4:0] W3T2ST W3T2FA OTLEG – – – – –
OP IL
AL
Default – – 0 1 1 1 1 1 1 1 1 – – – – –
900719

6.21.9.66 Message #41 - WSI4_T2
W4T2_L
KG W4T2ST W4T2FA W4T2_N
Function – – W4T2_DATA[4:0] OP IL OTLEG – – – – –
AL
Default – – 0 1 1 1 1 1 1 1 1 – – – – –
6.21.9.67 Message #42 - WSI1_T3

W1T3_L W1T3_C
Function – – KG W1T3_DATA[8:0] ERROR W1T3_NOTLEGAL
Element – – 0 1 1 1 1 1 1 1 1 1 0 1 1 1
Default – – RLR RLR RLR RLR RLR RLR RLR RLR RLR RLR RLR RLR RLR RLR

0 No fault
WxT3_LKG
WxT3_DATA[8:0] WSx Type3 data (BIT8 is located in LSB)
WxT3_CERROR
WSx data length error information
WxT3_NOTLEGAL
6.21.9.68 Message #43 - WSI2_T3

W2T3_L W2T3_C
Function – – KG W2T3_DATA[8:0] ERROR W2T3_NOTLEGAL
Element – – 0 1 1 1 1 1 1 1 1 1 0 1 1 1
6.21.9.69 Message #44 - WSI3_T3

Function – – W3T3_L W3T3_DATA[8:0] W3T3_C W3T3_NOTLEGAL

KG ERROR
Element – – 0 1 1 1 1 1 1 1 1 1 0 1 1 1
900719

6.21.9.70 Message #45 - WSI4_T3
Function – – W4T3_L W4T3_DATA[8:0] W4T3_C W4T3_NOTLEGAL

KG ERROR
Element – – 0 1 1 1 1 1 1 1 1 1 0 1 1 1
6.21.9.71 Message #46 - CAN_FLG

VCC2C VCC2C VCC2C CAN2_ CAN2_T VCC1C VCC1C VCC1C CAN1_ CAN1_T
Function – – – – – – ANOT ANOV ANUV OT XD_PD ANOT ANOV ANUV OT XD_PD
Element – – – – – – RLW RLW RLW RLW RLW RLW RLW RLW RLW RLW
Default – – – – – – 0 0 0 0 0 0 0 0 0 0

0 No fault
VCC2CANOT
1 VCC2_CAN overtemperature fault
0 No fault
VCC2CANOV
1 VCC2_CAN overvoltage fault
0 No fault
VCC2CANUV
1 VCC2_CAN undervoltage fault
0 No fault
CAN2_OT
1 CAN2 overtemperature fault
0 No fault
CAN2_TXD_PD
1 CAN2 Tx permanent dominant fault
0 No fault
VCC1CANOT
1 VCC1_CAN overtemperature fault
0 No fault
VCC1CANOV
1 VCC1_CAN overvoltage fault
0 No fault
VCC1CANUV
1 VCC1_CAN undervoltage fault
0 No fault
CAN1_OT
1 CAN1 overtemperature fault
0 No fault
CAN1_TXD_PD
1 CAN21Tx permanent dominant fault
900719

6.21.9.72 Message #47 - WLD12
Function – – WLD2_ WLD1_ WLD2_ WLD1_ WLD2_ WLD1_ WLD2_ WLD1_ WLD2_ WLD1_ ADIN2_ ADIN1_ WLD2_ WLD1_
OP_DIS OP_DIS VDS VDS OP OP OT OT OC OC EN EN ON ON
Element – – R/W R/W R R RLW RLW RLW RLW RLW RLW R/W R/W R/W/M R/W/M
Default – – 0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 Current source enabled on WLD2 output when WLD2 is off. If open load is detected the SPI flag is set
WLD2_OP_DIS
0 Current source enabled on WLD1 output when WLD1 is off. If open load is detected the SPI Flag is set
WLD1_OP_DIS
0 No fault
WLD2_VDS
1 WLD2 VDS is higher than OP_wld
0 No fault
WLD1_VDS
1 WLD1 VDS is higher than OP_wld
0 No fault
WLD2_OP
1 WLD2 open fault
0 No fault
WLD1_OP
1 WLD1 open fault
0 No fault
WLD2_OT
1 WLD2 overtemperature fault
0 No fault
WLD1_OT
1 WLD1 overtemperature fault
0 No fault
WLD2_OC
1 WLD2 overcurrent fault
0 No fault
WLD1_OC
1 WLD1 overcurrent fault
0 WLD2 is controlled by ADIN2
ADIN2_EN
1 WLD2 is controlled by WLD2_ON bit
0 WLD1 is controlled by ADIN1
ADIN1_EN
1 WLD1 is controlled by WLD1_ON bit
0 WLD2 OFF
WLD2_ON
1 WLD2 ON
0 WLD1 OFF
WLD1_ON
1 WLD1 ON
900719

6.21.9.73 Message #48 - ISOKVSO12
VSO_O VSO_O VSO_V VSO_O VSO_O VSO_S K_LINE ISOK_V ISOK_V VSO2_ VSO2_V VSO2_ VSO2_S
Function – – – T C DS PEN P_DIS EL _DIS SO2_OT SO2_O OP DS OP_DIS EL
C
Element – – – RLW RLW R RLW R/W R/W R/W RLW RLW RLW R R/W R/W
Default – – – 0 0 0 0 0 0 0 0 0 0 0 0 0

0 No fault
VSO_OT
1 VSO overtemperature fault
0 No fault
VSO_OC
1 VSO overcurrent fault
0 No fault
VSO_VDS
1 VSO VDS is higher than OP_vso
0 No fault
VSO_OPEN
1 VSO open fault
0 Current source enabled on VSO output when VSO is off. If open load is detected the SPI Flag is set
VSO_OP_DIS
0 VSO is controlled by selectable WSOx output from wheel speed sensor interface
VSO_SEL
1 VSO is controlled by VSO_IN
0 K-line active
K_LINE_DIS
1 VSO2 feature active
0 No fault
ISOK_VSO2_OT
1 K-line/VSO2 overtemperature fault
0 No fault
ISOK_VSO2_OC
1 K-line/VSO2 overcurrent fault
0 No fault
VSO2_OP
1 K-line/VSO2 open fault
0 No fault
VSO2_VDS
1 K-line/VSO2 VDS is higher than OP_isok
0 Current source enabled on VSO2 output when VSO2 is off. If open load is detected the SPI flag is set
VSO2_OP_DIS
0 VSO2 is controlled by WSOx
VSO2_SEL
1 VSO2 is controlled by TxK
900719

6.21.9.74 Message #49 - VLV_VDS
LSD8_V LSD5_V LSD11_V LSD2_V LSD10_V LSD9_V LSD4_V LSD3_V LSD12_V LSD7_V LSD6_V LSD1_V
Function – – – –
DS DS DS DS DS DS DS DS DS DS DS DS
Element – – – – R R R R R R R R R R R R
Default – – – – 0 0 0 0 0 0 0 0 0 0 0 0

0 No fault
x_VDS
1 VDS is higher than OP_lsd
6.21.10 SPI fault reporting

A fault is latched in the SPI registers when the corresponding defects are detected. The SPI fault reporting is done by:
• Level 1 interrupt register, which provides a one glance failure overview. For example, when the VREG_F fault bit condition is
indicated, the level 2 registers are read. For example, the VREG_FLG register is about the voltage output regulators.
• Level 2 interrupt registers, which gives the details and clears the fault in the both levels with a write operation.
6.21.11 SPI reset condition

The SPI registers are cleared when a reset event occurs. There are several condition shown in Table 189. The corresponding reset block
is shown in Table 190.
Table 189. Reset event

Condition number Description
1 Wake-up
2 RSTB forced low externally
3 Clock failure safe mode
4 Charge pump failure safe mode
5 VPWRx overvoltage safe mode
6 VPWRx ‘low’ voltage safe mode (PWRDNCFG = 00)
7 VPWR1 ‘under’ voltage safe mode (PWRDNCFG = 10)
8 VPWR1 ‘under’ voltage safe mode (PWRDNCFG = 01)
9 Watchdog failure (WDFLT or ALU_OVRFLW)
10 MCU regulator undervoltage (VCC3.3, VCC5 or VCCA)
11 VCC5EXT undervoltage or overtemperature
12 MCU regulator overtemperature (VPRE, VCC3.3, VCC5 or VCCA)
13 Exit from LBIST
14 LBIST failure safe mode
15 LBIST valve shutdown (if valves are on when LBIST is requested)
16 VCC5 undervoltage
900719

Table 190. Reset block
Safe mode or condition # from Table 189
Reset name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WSS X X X X X X X X X
VALVE/HSD X X X X X X X X X X X X X X X
PMD X X X X X X X X X X X X X X
WLD X X X X X X X X X X X X
CAN X X X X X X X X
ISOK X X X X X X X X X
ABIST X X X X X X X
Watchdog X X X X X X
ADC X X
PORB X
SPVSN/FLAG X X X
6.21.12 SPI electrical characteristics

Table 191. SPI electrical characteristics
SPI interface timing
fSPI SPI frequency 0.5 – 10 MHz

Watchdog window timeout
T_WD_SEL[2:0]
• 000 3.2 4.0 4.8
• 001 6.4 8.0 9.6
• 010 12.8 16 19.2
tWATCHDOG ms
• 011 25 32 39
• 100 51 64 77
• 101 102 128 154
• 110 204 256 308
• 111 (default) 408 512 616
tACK Acknowledge timeout for watchdog function disable 8.0 10 12 ms
tLEAD Falling edge of CSB to rising edge of SCLK (required setup time) 50 – – ns
tLAG Falling edge of SCLK to rising edge of CSB (required setup time) 50 – – ns
tXFER_DELAY No data time between SPI commands 300 – – ns
tWH High time of SCLK 45 – – ns
tWL Low time of SCLK 45 – – ns
tSU1 SI to rising edge of SCLK (required setup time) 15 – – ns
tSO(EN) Time from falling edge of CSB to SO low-impedance – – 30 ns
tTSO(DIS) Time from rising edge of CSB to SO high-impedance – – 30 ns
tVALID Time from falling edge of SCLK to SO data valid – – 30 ns
900719

6.22 Built-in self test
The 900719 contains the built-in self test for the self diagnostic. LIBST and ABIST are implemented. Both BIST are executed by a SPI
command from the MCU.
6.22.1 LBIST
LBIST checks the logic core integrity, and is performed on-demand by the MCU by setting LBIST_RUN[1:0] bits to 10. However,
LBIST_RUN[1:0] = 00 or 11 are not applicable. Those commands are ignored. After the LBIT execution, LBIST_RUN[1:0] to 01 is required
to be reset to perform a second time. LBIST runs scan patterns on internal logic. While LBIST is running, these sub-systems are shut-off.
The BIST pin status can be used to monitor the procedure. The LBIST and BIST pins are set high.
During an L-bist issue (LBIST_FAIL bit = 1), the microcontroller can request an escape path via an external reset by the RSTB pin (forced
to 0). If the high-side pre-driver was activated, the LBIST activation is delayed by tLSDx_HD_G to turn-off the valves and the safe switch
properly. The cumulated BIST duration time should be below 15 ms.
6.22.2 ABIST
ABIST checks the UV comparator integrity of power supply module (VPRE, VCCA, VCC3P3, and VCC5), and also the comparators driving
the reset table (VPWRx, …) by forcing the toggling of its own comparators’ input, and is requested by SPI command. ABIST is performed
on-demand by setting ABIST_RUN[1:0] to 10. However, ABIST_RUN[1:0] = 00 or 11 are not applicable. Those commands are ignored.
After the ABIT execution, ABIST_RUN[1:0] to 01 is required to be reset to perform a second time. The BIST pin status can be used to
monitor the procedure. The ABIST and BIST pins are set high.
During an ABIST issue (ABIST_FAIL bit = 1), the microcontroller can request an escape path via an external reset by the RSTB pin (forced
to 0). While the ABIST is running, the reporting comparators are masked (during this phase in case of a fault, the event is not taken into
account). If the ABIST_FAIL bit was set, MCU can determine which supervision feature(s) failed by reading the ABIST register. The test
result stores in the dedicated resister (ABISTFAIL). The bit is set to ‘0’ if the test passed and ‘1’ if the test failed. In addition, stuck-high or
stuck-low (including the RSTB input pin) can be diagnosed separately for each test via a dedicated resister (STUCKAT). Each of the
supervision features tested during ABIST (including the RSTB input pin) are able to be skipped by setting the corresponding ABIST-
Disable bit. The cumulated BIST duration time should be below 15 ms.
900719

7 Typical applications
7.1 Introduction
This typical application presents an ESC application schematic using the 900719.
7.1.1 Application diagram
VBAT1 10µ
ESP/ESC braking control unit
VCCA_SUP
M2 VBAT1
VPWR2
VPWR1
VCCA
MCU
VPRE_SUP
4 LSDx
Solenoid
Power PWMed Valves Coils
M1 VCC5
VPRE_S Supply Control (x4Ch) x4
VCC3P3
External VCC5_EXT
5.0V Supply Current 8 LSDx
DOSV Regulated Solenoid
RSTB
Valves Control 2 HSDx Coils
IGN Supervision (x8Ch) x8
VBAT1
Ignition VBAT2
PD_D M3
PD_G
SI, SO, SLK, CSB
4
32bits SPI Pump Motor PD_S
WSAI
with active
WSOx freewheeling M4
VSO1 diode FRW_G
M
WSx_HS 4 Wheel Speed 4
LF, RF, Hall Interface
TxDx 2
RxDx 2
LR & RR Sensor (x4Ch)

RXK
TXK
VBAT1
x4
VSO_IN Vehicule
Speed
Output CAN High K-Line Warning M5 10k 10k
Speed Interface Lamps
(x2Ch) (x2Ch) 2
ECU Voltages ADINx 4
Monitoring 10bits A/D x2
4
Dual CAN ISO K-Line

High Speed
Physical
Layers
Figure 47. 900719 typical application schematic 1
900719

C3
VPW R2
D1 VPW R1
VBAT1
D2 C2 C4
C1
CP
C h a rg e P u m p Band
VP R E_S U P Gap 2 S u p e rv is io n
R1
VPRE_D P re -lin e a r
V PR E _G re g u la to r
V PR E _S
C5 Band D ie T e m p e ra tu re
Gap 1 W a rn in g
Q1 V IN T _ A
C6 In te rn a l R e g u la to rs DOSV
C 16
R9
C7 V IN T _ D
G N D _D 2
C8
5 .0 V L in e a r DEBUG 3 .3 V
(D e b u g m o d e )
VCC5
R e g u la to r In te rn a l F u n c tio n s IG N D4
M C U I/O S u p p ly
RSTB
C9
5 .0 V L in e a r B IS T
IR E F
VC C 5_E XT R e g u la to r IR E F _ R E D U N T
E x te rn a l 5 .0 V S u p p ly
R 11 R 10 A lte rn a tiv e
C 10 C 25 W S xx_SU P
3 .3 V L in e a r 3 2 -b it S P I In te rfa c e 4 4 c o n n e c te d to
V B A T th ro u g h a
R e g u la to r S C L K , C S B , S I, S O d io d e
VCC3P3
M C U I/O S u p p ly
C 11 2 W Sxx_S U P
C 25 C 17 C 18
VC C A _S UP 1 .2 V to 3 .3 V W heel Speed W SAI
L1 4 W S x_ H S
M C U C o re S u p p ly
VCCA_SW
D C /D C B u c k S e n s o r In te rfa c e
D3 4 4
C 12 VCCA C o n v e rte r ² (x 4 C h ) W SO x
C 26 C 19
H a ll
VBAT1 Sensor
VBAT2
VSO1 R12 x4
R 14 PD_D
PD_G
M o to r P u m p V e h ic le S p e e d C20
R2 VBOOT P re -d riv e r w ith O u tp u t 1
D5
R 15 P D_S
F RW _G B o o s ts tra p L o g ic V S O _ IN
R3 C 13
Q2
D6
VBAT1 w ith
RXK
H D _D L -B is t & K -L in e In te rfa c e VBAT1
R6
H D _G A -B is t or
TXK
Q3 HD_S H S P re -d riv e r R13

M
D 11 R7 V e h ic le S p e e d IS O _ V S O 2
R5
D7
R4
Q5 O u tp u t 2 C 21
D8 D 12
R8 LSDx
D ig ita l V a lv e s 5 .0 V S u p p ly fo r V P RE _C AN
D9 S o le n o id C o ils LS D x 4 (x 4 C h ) 3 0 0 m Ω CAN 2 VC C x_C A N C 23

x4
D 10 VBAT2 x4
(x 2 C h ) C24
C 27
R5
H S D x (3 0 0 m Ω ) & 2
RXDx
Q4
S o le n o id C o ils LS D x 8 LSDx C A N H ig h S p e e d 2
TXDx
x8 (2 0 0 /3 0 0 m Ω ) In te rfa c e s 2
C A Nx_H
VBAT1
x8 C27 C u rre n t R e g u la te d (x 2 C h ) 2
C AN x_L
HSDx 2 V a lv e s (x 8 C h )
10k 10k 10k
x2
L S W a rn in g L a m p
C 14 P re -d riv e r 2 W LD x
1 0 b its A D C (x 2 C h ) C22
3 3 (x 3 C h ) x2
A D IN x
G N D _A G ND_P G N D _D1
Figure 48. 900719 typical application schematic 2
900719

7.1.2 Bill of materials
Table 192. Bill of materials (62)
Schematic Assy.
Qty. Value Description Package
label opt.
Capacitors
C1 10 μF (±20 % X7R 50 V) Reduction of emission and immunity

C10 1.0 μF (±20 % X7R 20 V) Reduction of emission and immunity
C12 47 μF ESR < 0.1 Ω (±20 % X7R 20 V) DC/DC converter capacitor
C13 220 nF (±20 % X7R 20 V) Motor pump bootstrap capacitor
C14 22 nF (±20 % X7R 50 V) Reduction of emission and immunity
C18 Reduction of emission and immunity

22 nF (±20 % X7R 50 V)
C20 470 pF (±20 % X7R 50 V) Decoupling
C21 470 pF (±20 % X7R 50 V) Decoupling
C22 22 nF (±20 % X7R 50 V) Decoupling
C24 1.0 μF (±20 % X7R 50 V) Decoupling
C25 1.0 nF (±20 % X7R 50 V) Reduction of emission and immunity
C26 1.0 nF (±20 % X7R 50 V) Reduction of emission and immunity
C4 220 nF (±20 % X7R 20 V) Charge pump tank capacitor
Diodes
D1 SBRS6340T3G Schottky diode for reverse battery protection

D10 RB521S30T1G Reduction of immunity
D11 MM3Z15VB Reduction of immunity
D2 Zener transient voltage suppressor Zener transient voltage suppressor
D3 SS22T3G DC/DC converter Schokky diode
D4 SBRS8340T3G Schottky diode for reverse battery protection
900719

Table 192. Bill of materials (continued) (62)
Schematic Assy.
Qty. Value Description Package
label opt.
Diodes (continued)

Inductors
22 μH ±30%, DCR < 0.1 Ω

L1 DC/DC converter inductor
(CLF6045NIT-220M-D)
Transistors
Q1 STD12NF06L/IPD14N06S2-80 Pre-voltage regulator FET

Q2 STB80NF55-06T/IPB100N04S3-03 Motor pump FET (called M3)
Q3 STD30NF06L/ IPD30N06S2-15 Active recirculation FET for motor pump (called M4)
Q4 STB80NF55-06T/IPB100N04S3-03 Reverse battery protection (called M5)
Q5 STD30NF06L/ IPD30N06S2-15 Safe FET for the valves (called M2)
Resistors
R1 100 mΩ (±1.0 %) Current limitation for pre-voltage regulator FET

R10 10 kΩ (±0.1 %) Pull-down resistor for reference current
R11 10 kΩ (±0.1 %) Pull-down resistor for reference current
R12 10 kΩ (±10 %) Pull-up resistor
R14 50 Ω (±10 %) Reduction of immunity
R3 470 kΩ (±10 %) Off-state in sleep mode
Notes:
62. NXP does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables.
While NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
63. Critical Components. For critical components, it is vital to use the manufacturer listed.
900719

8 Packaging
8.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number.
Package Suffix Package outline drawing number

100-Pin LQFP AF 98ASA00553D
900719

900719

900719

9 Revision history
Rev Date Description

1.0 6/2014 • Initial release
2.0 3/2015 • Major updates throughout this document
3.0 12/2015 • Minor clarifications and corrections to technical data throughout this document
• Moved (8) and (9) to their proper position.

• Corrected (22) from bit 1 to bit 0
• Fixed figure number tags in data sheet
• Corrected HD_S to HSDx in Table 18
• Corrected LD_DMP to PMD_LD in Table 18
• Deleted note for Table 28
• Added ROFF_VCC_CAN parameter to Table 28
4.0 6/2016 • Corrected Figure 17
• Changed fPMD from ±20 % to ±15 % in Table 33
• Changed tOV_HSD in Table 38
• Changed ISOURCE_HSD in Table 38
• Changed title for 6.16.13, Input signal conditioning electrical characteristics, Page 68
• Corrected D1 and D2 elements in Table 155
• Corrected D4, D3, and D2 elements in Table 183
• Updated 8.1, Package mechanical dimensions, Page 131
• Fixed links in revision history
5.0 7/2016
• Changed Orderable parts to SC
• Changed VPWR range to min. 5.3 V in Table 21, Table 24, Table 25, Table 26, Table 29, Table 34, and
Table 38
• Changed VPWR range to min. 5.5 V in Table 28
• Added note 37 to Table 21
9/2016 • Added note 42 to Table 26
6.0
• Corrected Figure 20
• Updated section 6.15.7.1, LSDx valve open detection, Page 58
9/2016 • Added WSx_HS range to Table 41
10/2016 • Corrected typo from WSx_HS to WSx_SUP Table 41
900719

How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There
are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on
Home Page:
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Web Support: NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose,
nxp.com/support nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be
provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including "typicals," must be validated for each customer application by the
customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells
products pursuant to standard terms and conditions of sale, which can be found at the following address:
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© 2016 NXP B.V.
Document Number: SC900719

Rev. 6.0
10/2016

Fully Integrated Electronic Stability Control/electronic Stability Program Braking Chip

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Fully Integrated Electronic Stability Control/electronic Stability Program Braking Chip

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NXP Semiconductors Document Number: SC900719

Data sheet: Advance Information Rev. 6.0, 10/2016

Fully integrated electronic stability

Figure 1. 900719 simplified application diagram

* This document contains certain information on a new product.

Table 1. Orderable part variations

SC900719BAF 1.20 V Yes

SC900719DAF 3.30 V Yes

5.0 V Linear BIST

3.3 V Linear 32-bit SPI 4

VCCA_SUP 1.2 V to 3.3 V Wheel Speed WSAI

VCCA Converter ² (x4Ch) 4

PD_D Motor Pump Vehicle Speed

HSDx (300 mΩ) & 2

GND_A GND_P GND_D1

Figure 2. 900719 simplified internal block diagram

3.1 Pinout diagram

Figure 3. 900719 pinout diagram

Table 2. 900719 pin definitions

5 PD_S A_Out Source feedback high-side FET for pump motor

7 PD_D A_Out Drain feedback high-side FET for pump motor

9 PD_G A_Out Gate control high-side FET for pump motor

10 GND_P GND Power ground

11 LSD1 A_Out Low-side FET for digital valve

13 LSD2 A_Out Low-side FET for digital/current regulated valve

15 LSD3 A_Out Low-side FET for digital/current regulated valve

19 LSD5 A_Out Low-side FET for digital/current regulated valve

20, 51, 53, 56, 74 NC NC These pins are shorted to ground.

22 GND_P GND Power ground

23 RXK D_Out ISO K-line receiver

24 RSTB D_IO MCU reset (4)

25 BIST D_Out BIST monitoring output

26 SO D_Out SPI data to MCU

27 WSAI D_Out Type III sensor additional information

28 WSO1 D_Out Sensor output for RR (right rear)

29 WSO2 D_Out Sensor output for LR (left rear)

30 WSO3 D_Out Sensor output for RF (right front)

32 RXD1 D_Out CAN 1 receiver

33 RXD2 D_Out CAN 2 receiver

34 GND_D2 GND Digital ground 2 for DOSV voltage monitoring

35 DOSV A_In Digital output voltage supply

36 CAN2_L A_IO CAN 2 bus

37 CAN2_H A_IO CAN 2 bus

38 VCC2_CAN A_Out CAN 2 transceiver supply

39 VPRE_CAN A_In CAN transceivers pre-regulator supply

40 VCC1_CAN A_Out CAN 1 transceiver supply

41 CAN1_H A_IO CAN 1 bus

42 CAN1_L A_IO CAN 1 bus

43 TXD1 D_In CAN 1 transceiver

44 TXD2 D_In CAN 2 transceiver

45 VSO_IN D_In Vehicle speed input

46 DEBUG D-In Watchdog disable input

47 CSB D-In SPI chip select

49 SCLK D-In SPI clock

50 TXK D-In ISO K-line transceiver

52 IGN A_In Ignition

54, 66 GND_P GND Power ground

55 LSD7 A_Out Low-side FET for digital valve

59 LSD9 A_Out Low-side FET for digital/current regulated valve

61 LSD10 A_Out Low-side FET for digital/current regulated valve

65 LSD12 A_Out Low-side FET for digital valve

67 VSO A_Out Vehicle speed output 1

69 WLD2 A_Out Warning lamp pre-driver 2