IM08 Basic Electronics 2023

Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY

Bayombong, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No. 08: ECE01-2S-2022-2023
College: Engineering
Campus: Bambang
DEGREE Bachelor of Science in

COURSE NO. ECE 101
PROGRAM Mechanical Engineering
SPECIALIZATION COURSE TITLE
YEAR LEVEL 2nd Year TIME FRAME WKNO. IM NO. 08
I. UNIT TITLE/CHAPTER TITLE
Bipolar-Junction Transistor
II. LESSON TITLE
1. Introduction
1.1 Transistor Construction
1.2 Transistor Operation
1.3 Transistor Characteristic Curve
2. Transistor Data Sheets
2.1Transistor Casing and Terminal Identification
2.2 Transistor Casing and Terminal Identifications
3. BJT Transistor Biasing Techniques
3.1 Operating Point
3.2 Fixed-Bias Configuration
3.3 Emitter-Bias Configuration
. 3.4 Voltage-Divider Bias Configuration
3.5 Collector Feedback Configuration
4. Design Operation
5. Transistor Switching Networks
III. LESSON OVERVIEW
This module provides the students the fundamental knowledge about the basic construction, operations,
concepts and analysis of Bipolar-Junction Transistor which is mainly the heart of all electronics systems
now a days.
IV. DESIRED LEARNING OUTCOMES
At the end of the lesson, the students should be able to:
1. Explain the operation of Bipolar-Junction Transistor

2. Describe the Characteristic Curves of an BJT device.
3. Discuss the different BJT transistor configurations.
4. Calculate the different DC parameters involving BJT transistor amplifiers.
5. Analyze the stability of BJT transistor amplifiers.
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IM No. 08: ECE01-2S-2022-2023
V. LESSON CONTENT
1. Introduction
As a short history, during the period 1904 to1947, the vacuum tube was the electronic device of interest
and development. In 1904, the vacuum-tube diode was introduced by J. A. Fleming. Shortly thereafter,
in 1906, Lee De Forest added a third element, called the control grid, to the vacuum diode, resulting in
the first amplifier, the triode. In the following years, radio and television provided great stimulation to the
tube industry. The production rose from about 1 million tubes in 1922 to about 100 million in 1937. In the
early 1930s the four-element tetrode and the five-element pentode gained prominence in the electron-
tube industry. In the years to follow, the industry became one of primary importance, and rapid advances
were made in design, manufacturing techniques, high-power and high-frequency applications, and
miniaturization.
On December 23, 1947, however, the electronics industry was to experience the advent of a completely
new direction of interest and development. It was on the afternoon of this day that Dr. S. William
Shockley, Walter H. Brattain, and John Bardeen demonstrated the amplifying action of the first transistor
device at the Bell Telephone Laboratories as shown in Figure 1. The original transistor (a point-contact
transistor) is shown in Figure 2.
The advantages of this three-terminal solid-state device over the tube were immediately obvious: It was
smaller and lightweight; it had no heater requirement or heater loss; it had a rugged construction; it was
more efficient since less power was absorbed by the device itself; it was instantly available for use,
requiring no warm-up period; and lower operating voltages were possible.
Figure 1. Coinventors of the first transistor Figure 2. The first transistor.

at Bell Laboratories.
1.1 Transistor Construction
The transistor is a three-layer semiconductor device consisting of either two n - and one p -type
layers of material or two p - and one n -type layers of material. The former is called an npn
transistor, and the latter is called a pnp transistor. Both types are shown in Figure 3. The emitter
layer is heavily doped, with the base and collector only lightly doped. The outer layers have widths
much greater than the sandwiched p - or n -type material. As shown in Figure 3, the ratio of the
total width to that of the center layer is 0.150/0.001 = 150:1. The doping of the sandwiched layer
is also considerably less than that of the outer layers (typically, 1:10 or less). This lower doping
level decreases the conductivity (increases the resistance) of this material by limiting the number
of “free” carriers.
Again, shown in Figure 3, the terminals have been indicated by the capital letters E for emitter, C
for collector, and B for base. The abbreviation BJT, from bipolar junction transistor, is often
applied to this three-terminal device. The term bipolar reflects the fact that holes and electrons
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participate in the injection process into the oppositely polarized material. If only one carrier is
employed (electron or hole), it is considered a unipolar device.
(a) (b)
Figure 3. Types of transistors: (a) pnp (b) npn.
1.2 Transistor Operation
The basic operation of the transistor will now be described using the pnp transistor of Figure 4.
The operation of the npn transistor is exactly the same if the roles played by the electron and hole
are interchanged. In Figure 4(a), the pnp transistor has been redrawn without the base-to-collector
bias. Note the similarities between this situation and that of the forward-biased diode in the past
module. The depletion region has been reduced in width due to the applied bias, resulting in a
heavy flow of majority carriers from the p - to the n -type material.
As we get rid of the base-to-emitter bias of the pnp transistor as shown in Figure 4(b), we consider
the similarities between this situation and that of the reverse-biased diode. Recall that the flow of
majority carriers is zero, resulting in only a minority-carrier flow, as indicated in Figure 4(b). One
p–n junction of a transistor is reverse-biased, whereas the other is forward-biased.
Figure 4. Biasing a transistor: (a) forward-bias; (b) reverse-bias.
In Figure 5, both biasing potentials have been applied to a pnp transistor, with the resulting
majority- and minority-carrier flows indicated. Note in Figure 5 the widths of the depletion regions,
indicating clearly which junction is forward-biased and which is reverse-biased.
As indicated in Figure 5, a large number of majority carriers will diffuse across the forward-biased
p–n junction into the n -type material. The question then is whether these carriers will contribute
directly to the base current 𝐼𝐵 or pass directly into the p -type material. Since the sandwiched n -
type material is very thin and has a low conductivity, a very small number of these carriers will
take this path of high resistance to the base terminal. The magnitude of the base current is
typically on the order of microamperes, as compared to milliamperes for the emitter and collector
currents. The larger number of these majority carriers will diffuse across the reverse-biased
junction into the p -type material connected to the collector terminal as indicated. The reason for
the relative ease with which the majority carriers can cross the reverse-biased junction is easily
understood if we consider that for the reverse-biased diode the injected majority carriers will
appear as minority carriers in the n -type material. In other words, there has been an injection of
minority carriers into the n -type base region material. Combining this with the fact that all the
minority carriers in the depletion region will cross the reverse-biased junction of a diode accounts
for the flow.
Applying Kirchhoff’s current law (KCL) to the transistor of Figure 5 as if it were a single node, we
obtain
𝑰 𝑬 = 𝑰𝑪 + 𝑰𝑩 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏
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and find that the emitter current is the sum of the collector and base currents. The collector
current, however, comprises two components—the majority and the minority carriers as
indicated in Figure 5.0. The minority-current component is called the leakage current and is
given the symbol 𝐼𝐶𝑂 (𝐼𝐶 current with emitter terminal 𝑂pen). The collector current, therefore, is
determined in total by
𝑰𝑪 = 𝑰𝑪𝒎𝒂𝒋𝒐𝒓𝒊𝒕𝒚 + 𝑰𝑪𝑶𝒎𝒊𝒏𝒐𝒓𝒊𝒕𝒚 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐
For general-purpose transistors, 𝐼𝐶 is measured in milliamperes and 𝐼𝐶𝑂 is measured in

microamperes or nanoamperes. 𝐼𝐶𝑂 , like 𝐼𝑆 for a reverse-biased diode, is temperature sensitive
and must be examined carefully when applications of wide temperature ranges are considered. It
can severely affect the stability of a system at high temperature if not considered properly.
Improvements in construction techniques have resulted in significantly lower levels of 𝐼𝐶𝑂 , to the
point where its effect can often be ignored.
Figure 5. Majority and minority carrier flow of a pnp transistor
1.3 Transistor Characteristic Curve
1.3.1 Common-Base
The common-base terminology is derived from the fact that the base is common to both
the input and output sides of the configuration as shown in Figure 6. In addition, the
base is usually the terminal closest to, or at, ground potential. The arrow in the graphic
symbol defines the direction of emitter current (conventional flow) through the device.
To fully describe the behavior of a three-terminal device such as the common-base

amplifiers of Figure 6, it requires two sets of characteristics—one for the driving point or
input parameters and the other for the output side.
The output set relates an output current (𝐼𝐶 ) to an output voltage (𝑉𝐶𝐵 ) for various levels
of input current (𝐼𝐸 ) as shown in Figure 7. The output or collector set of characteristics has
three basic regions of interest, as indicated: the active region, cutoff region, and
saturation region. The active region is the region normally employed for linear
(undistorted) amplifiers. In particular: In the active region the base–emitter junction is
forward-biased, whereas the collector–base junction is reverse-biased.
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Figure 6. Notation and symbols used with the common-base configuration:

(a) pnp transistor; (b) npn transistor.
Figure 7. Output or collector characteristics for a common-base transistor amplifier.
Note in Figure 7 that as the emitter current increases above zero, the collector current
increases to a magnitude essentially equal to that of the emitter current as determined by
the basic transistor-current relations. Note also the almost negligible effect of 𝑉𝐶𝐵 on the
collector current for the active region. The curves clearly indicate that a first approximation
to the relationship between 𝐼𝐸 and 𝐼𝐶 in the active region is given by
𝑰𝑪 ≅ 𝑰𝑬 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟑
As inferred by its name, the cutoff region is defined as that region where the collector
current is 0 A, as revealed on Figure 7. In addition, the cutoff region the base–emitter
and collector–base junctions of a transistor are both reverse-biased.
The saturation region is defined as that region of the characteristics to the left of
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𝑉𝐶𝐵 = 0𝑉. The horizontal scale in this region was expanded to clearly show the dramatic
change in characteristics in this region. Note the exponential increase in collector current
as the voltage 𝑉𝐶𝐵 increases toward 0 V. In the saturation region the base–emitter and
collector–base junctions are forward-biased.
Take note also that is, once a transistor is in the “on” state, the base-to-emitter voltage will
be assumed to be the following:
𝑽𝑩𝑬 ≅ 𝟎. 𝟕 𝑽 ( 𝒇𝒐𝒓 𝑺𝒊𝒍𝒊𝒄𝒐𝒏 𝒕𝒚𝒑𝒆 𝒔𝒆𝒎𝒊𝒄𝒐𝒏𝒅𝒖𝒄𝒕𝒐𝒓) 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟒
In other words, the effect of variations due to 𝑉𝐶𝐵 and the slope of the input characteristics
will be ignored as we strive to analyze transistor networks in a manner that will provide a
good approximation to the actual response without getting too involved with parameter
variations of less importance.
1.3.1.1 Alpha
In the dc mode the levels of 𝐼𝐶 and 𝐼𝐸 due to the majority carriers are related by a quantity
called alpha and defined by the following equation:
𝑰𝑪
𝜶𝒅𝒄 = 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟓
𝑰𝑬
where 𝐼𝐶 and 𝐼𝐸 are the levels of current at the point of operation. Even though the
characteristics of Figure 7 would suggest that 𝛼 = 1, for practical devices alpha typically
extends from 0.90 to 0.998, with most values approaching the high end of the range.
Since alpha is defined solely for the majority carriers, Equation # 2 becomes
𝑰𝑪 = 𝜶𝑰𝑬 + 𝑰𝑪 𝑩𝑶 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟔
For ac mode situations where the point of operation moves on the characteristic curve,
an ac alpha is defined by
𝚫𝑰𝑪
𝜶𝒂𝒄 = | 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟕
𝚫𝑰𝑬 𝑽𝑪𝑩=𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕
The ac alpha is formally called the common-base , short-circuit , amplification factor,

for reasons that will be more obvious when we examine transistor equivalent circuits
1.3.2 Common-Emitter Configuration
The most frequently encountered transistor configuration appears in Figure 8 for the pnp
and npn transistors. It is called the common-emitter configuration because the emitter is
common to both the input and output terminals (in this case common to both the base and
collector terminals). Two sets of characteristics are again necessary to describe fully the
behavior of the common-emitter configuration: one for the input or base–emitter circuit and
one for the output or collector–emitter circuit. Both are shown in Figure 9.
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Figure 8. Notation and symbols used with the common-emitter configuration:

(a) npn transistor;(b) pnp transistor.
Figure 9.0 Characteristics of a silicon transistor in the common-emitter configuration:

(a) collector characteristics; (b) base characteristics.
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The emitter, collector, and base currents are shown in their actual conventional current
direction. Even though the transistor configuration has changed, the current relations
developed earlier for the common-base configuration are still applicable. That is, 𝐼𝐸 = 𝐼𝐶 +
𝐼𝐵 and 𝐼𝐶 = 𝛼𝐼𝐸 .
For the common-emitter configuration the output characteristics are a plot of the output
current (𝐼𝐶 ) versus output voltage (𝑉𝐶𝐸 ) for a range of values of input current (𝐼𝐵 ). The
input characteristics are a plot of the input current (𝐼𝐵 ) versus the input voltage (𝑉𝐵𝐸 ) for a
range of values of output voltage (𝑉𝐶𝐸 ).
Note that on the characteristics, the magnitude of 𝐼𝐵 is in microamperes, compared to

milliamperes of 𝐼𝐶 . Consider also that the curves of 𝐼𝐵 are not as horizontal as those
obtained for 𝐼𝐸 in the common-base configuration, indicating that the collector-to-emitter
voltage will influence the magnitude of the collector current.
The active region for the common-emitter configuration is that portion of the upper-right
quadrant that has the greatest linearity, that is, that region in which the curves for 𝐼𝐵 are
nearly straight and equally spaced. In Figure 9, a this region exists to the right of the
vertical dashed line at 𝑉𝐶𝐸 𝑠𝑎𝑡 and above the curve for 𝐼𝐵 equal to zero. The region to the
left of 𝑉𝐶𝐸 𝑠𝑎𝑡 is called the saturation region.
In the active region of a common-emitter amplifier, the base–emitter junction is

forward-biased, whereas the collector–base junction is reverse-biased.
For future reference, the collector current defined by the condition 𝐼𝐵 = 0 𝑚𝐴 will be
assigned the notation indicated by the following equation:
𝑰𝑪𝑩𝑶
𝑰𝑪𝑬𝑶 = | 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟖
𝟏 − 𝜶 𝑰𝑩=𝟎 µ𝑨
For linear (least distortion) amplification purposes, cutoff for the common-emitter
configuration will be defined by 𝐼𝐶 = 𝐼𝐶𝐸𝑂 . In other words, the region below 𝐼𝐵 = 0µ𝐴 is to
be avoided if an undistorted output signal is required.
When employed as a switch in the logic circuitry of a computer, a transistor will have two
points of operation of interest: one in the cutoff and one in the saturation region. The cutoff
condition should ideally be 𝐼𝐶 = 𝑜𝑚𝐴 for the chosen 𝑉𝐶𝐸 voltage. Since 𝐼𝐶𝐸𝑂 is typically
low in magnitude for silicon materials, cutoff will exist for switching purposes when 𝐼𝐵 =
0 µ𝐴 or 𝐼𝐶 = 𝐼𝐶𝐸 for silicon transistors only . For germanium transistors, however, cutoff
for switching purposes will be defined as those conditions that exist when 𝐼𝐶 = 𝐼𝐶𝐵𝑂 . This
condition can normally be obtained for germanium transistors by reverse-biasing the base-
to-emitter junction a few tenths of a volt.
Figure 10.0 Circuit conditions related to 𝐼𝐶𝐸𝑂
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1.3.2.1 Beta (𝜷)
In the dc mode the levels of 𝐼𝐶 and 𝐼𝐵 are related by a quantity called beta and defined by
the following equation:
𝑰𝑪
𝜷𝒅𝒄 = 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 9
𝑰𝑩
Where 𝐼𝐶 and 𝐼𝑩 are determined at a particular operating point on the characteristics. For
practical devices the level of 𝛽 typically ranges from about 50 to over 400, with most in the
midrange. As for a, the parameter 𝛽 reveals the relative magnitude of one current with
respect to the other. For a device with a 𝛽 of 200, the collector current is 200 times the
magnitude of the base current.
On the specification sheets 𝛽𝑑𝑐 is usually included as ℎ𝐹𝐸 with the italic letter ℎ derived
from an ac ℎybrid equivalent circuit. The subscript FE is derived from forward-current
amplification and common- emitter configuration, respectively.
For ac situations an ac beta is defined as follows:
𝚫𝑰𝑪
𝜷𝒂𝒄 = | 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 10
𝚫𝑰𝑩 𝑽
𝑪𝑬=𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕
The formal name for 𝛽𝑎𝑐 is common-emitter, forward-current, amplification factor. Since
the collector current is usually the output current for a common-emitter configuration and
the base current is the input current, the term amplification is included in the nomenclature
above.
On specification sheets 𝛽𝑎𝑐 is normally referred to as ℎ𝑓𝑒 . Note that the only difference
between the notation used for the dc beta, specifically, 𝛽𝑑𝑐 = ℎ𝐹𝐸 , is the type of lettering
for each subscript quantity.
A relationship can be developed between 𝛽 and 𝛼 using the basic relationships introduced
𝐼 𝐼 𝐼 𝐼
thus far. Using 𝛽 = 𝐶⁄𝐼 , we have 𝐼𝐵 = 𝛽𝐶 , and from 𝛼 = 𝐶⁄𝐼 we have 𝐼𝐸 = 𝐶⁄𝛼.
𝐵 𝐸
Substituting into
𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵
We have
𝐼𝐶
= 𝐼𝐶 + 𝐼𝐶
𝛼 𝛽
and dividing both sides of the equation by 𝐼𝐶 results in
1 1
=1+
𝛼 𝛽
Or
𝛽 = 𝛼𝛽 + 𝛼 = (𝛽 + 1)𝛼
So that
𝜷
𝜶= 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟏
𝜷+𝟏
or
𝜶
𝜷= 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟐
𝟏−𝜶
In addition, recall that

𝐼𝐶𝐵𝑂
𝐼𝐶𝐸𝑂 =
1−𝛼
But using an equivalence of
1
= 𝛽+1
1−𝛼
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Derived from the above, we find that
𝐼𝐶𝐸𝑂 = (𝛽 + 1)𝐼𝐶𝐵𝑂
Or
𝑰𝑪𝑬𝑶 ≅ 𝜷𝑰𝑪𝑩𝑶 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟑
Beta is a particularly important parameter because it provides a direct link between current
levels of the input and output circuits for a common-emitter configuration. That is,
𝑰𝑪 = 𝜷𝑰𝑩 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟒
And since
𝐼𝐸 = 𝐼𝐶 + 𝐼𝑩
= 𝛽𝐼𝑩 + 𝐼𝑩
We have
𝑰𝑬 = (𝜷 + 𝟏)𝑰𝑩 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟓
1.3.3. Breakdown Region
As with the common-base configuration, there is a maximum collector-emitter voltage that

can be applied and still remain in the active stable region of operation. In Figure 11 the
characteristics of Figure 7 have been extended to demonstrate the impact on the
characteristics at high levels of 𝑉𝐶𝐸 . At high levels of base current, the currents almost
climb vertically, whereas at lower levels a region develops that seems to back up on itself.
This region is particularly noteworthy because an increase in current is resulting in a drop
in voltage-totally different from that of any resistive element where an increase in current
results in an increase in potential drop across the resistor. Regions of this nature are said
to have a negative-resistance characteristic.
Figure 11. Examining the breakdown region of a transistor in the common-emitter configuration.
The recommended maximum value for a transistor under normal operating conditions is
labeled 𝐵𝑉𝐶𝐸𝑂 as shown in Figure 11 or 𝑉(𝐵𝑅)𝐶𝐸𝑂 . It is less than 𝐵𝑉𝐶𝐵𝑂 and in fact, is often
half the value of𝐵𝑉𝐶𝐵𝑂 .
For this breakdown region there are two reasons for the dramatic change in the curves.
One is the avalanche breakdown mentioned for the common-base configuration, whereas
the other, called punch-through, is due to the Early Effect. In total the avalanche effect is
dominant because any increase in base current due to the breakdown phenomena will be
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increase the resulting collector current by a factor beta. This increase in collector current
will then contribute to the ionization (generation of free carriers) process during
breakdown, which will cause a further increase in base current and even higher levels of
collector current.
1.3.4 Limits of Operation
For each transistor there is a region of operation on the characteristics that will ensure
that the maximum ratings are not being exceeded and the output signal exhibits minimum
distortion. Such a region has been defined for the transistor characteristics of Figure 12.0.
Some of the limits of operation are self-explanatory, such as maximum collector current
(normally referred to on the specification sheet as continuous collector current) and
maximum collector-to-emitter voltage (often abbreviated as 𝐵𝑉𝐶𝐸𝑂 or 𝑉(𝐵𝑅)𝐶𝐵𝑂 on the
specification sheet). For the transistor of Figure 12, 𝐼𝐶𝑚𝑎𝑥 was specified as 50 mA and
𝐵𝑉𝐶𝐸𝑂 as 20 V. The vertical line on the characteristics defined as 𝑉𝐶𝐸𝑠𝑎𝑡 specifies the
minimum 𝑉𝐶𝐸 that can be applied without falling into the nonlinear region labeled the
saturation region.
The level of 𝑉𝐶𝐸𝑠𝑎𝑡 is typically in the neighborhood of the 0.3 V specified for this transistor.
The maximum dissipation level is defined by the following equation:
𝑷𝑪𝒎𝒂𝒙 = 𝑽𝑪𝑬 𝑰𝑪 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟔
Figure 12. Defining the linear (undistorted) region of operation for a transistor.
For the device of Figure 12.0, the collector power dissipation was specified as 300 mW.
The question then arises of how to plot the collector power dissipation curve specified by
the fact that
𝑃𝐶𝑚𝑎𝑥 = 𝑉𝐶𝐸 𝐼𝐶 = 300 𝑚𝑊
At 𝑰𝑪𝒎𝒂𝒙 : At any point on the characteristics the product of 𝑉𝐶𝐸 and 𝐼𝐶 must be equal to
300 mW. If we choose 𝐼𝐶 to be the maximum value of 50 mA and substitute into the
relationship above, we obtain
𝑉𝐶𝐸 𝐼𝐶 = 300 𝑚𝑊
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𝑉𝐶𝐸 (50 𝑚𝐴) = 300 𝑚𝑊
300𝑚𝑊
𝑉𝐶𝐸 =
50 𝑚𝐴
𝑉𝐶𝐸 = 𝟔𝑽
At 𝑽𝑪𝑬 𝒎𝒂𝒙 As a result we find that if 𝑉𝐶𝐸 = 50𝑚𝐴 , then 𝑉𝐶𝐸 = 6𝑉 on the power dissipation
curve as indicated in Figure 12. If we now choose 𝑉𝐶𝐸 to be its maximum value of 20 V,
the level of 𝐼𝐶 is the following:
(20𝑉)𝐼𝐶 = 300𝑚𝑊
300𝑚𝑊
𝐼𝐶 =
20𝑉
𝐼𝐶 = 15 𝑚𝐴
Defining a second point on the power curve.

1
At 𝐼𝐶 = 2 𝐼𝐶𝑚𝑎𝑥 If we now choose a level of 𝐼𝐶 in the midrange such as 25 mA and solve
for the resulting level of 𝑉𝐶𝐸 ,we obtain
𝑉𝐶𝐸 (25𝑚𝐴) = 300 𝑚𝑊
And
300𝑚𝑊
𝑉𝐶𝐸 =
25𝑚𝐴
𝑉𝐶𝐸 = 𝟏𝟐𝑽
as also indicated in Figure 12.
The cutoff region is defined as that region below 𝐼𝐶 = 𝐼𝐶𝐸𝑂 . This region must also be
avoided if the output signal is to have minimum distortion. On some specification sheets
only 𝐼𝐶𝐵𝑂 is provided. One must then use the equation 𝐼𝐶𝐸𝑂 = 𝛽𝐼𝐶𝐵𝑂 to establish some
idea of the cutoff level if the characteristic curves are unavailable. Operation in the
resulting region of Figure 12 will ensure minimum distortion of the output signal and current
and voltage levels that will not damage the device.
If the characteristic curves are unavailable or do not appear on the specification sheet (as
is often the case), one must simply be sure that 𝐼𝐶 , 𝑉𝐶𝐸 , and their product 𝑉𝐶𝐸 . 𝐼𝐶 fall into
the following range:
𝐼𝐶𝐸𝑂 ≤ 𝐼𝐶 ≤ 𝐼𝐶𝑚𝑎𝑥
𝑉𝐶𝐸𝑠𝑎𝑡 ≤ 𝑉𝐶𝐸 ≤ 𝑉𝐶𝐸𝑚𝑎𝑥
𝑽𝑪𝑬 𝑰𝑪 ≤ 𝑷𝑪𝒎𝒂𝒙 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 17
For the common-base characteristics the maximum power curve is defined by the f
ollowing product of output quantities:
𝑷𝑪𝒎𝒂𝒙 = 𝑽𝑪𝑩 𝑰𝑪 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟖
1.3.5 Biasing
You have learned about the three basic configurations of a BJT such as (a) common base
(CB), (b) common emitter (CE), (c) common collector (CC) or emitter follower. For the
proper biasing of
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2. Transistor Specification Sheet
Since the specification sheet is the communication link between the manufacturer and user of the
device, it is particularly important that the information provided be recognized and correctly
understood. Although all the parameters have not been introduced, a broad number will now be
familiar.
The information provided in Figure 13 is provided by the Fairchild Semiconductor Corporation. The
2N4123 is a general-purpose npn transistor with the casing and terminal identification appearing in
the top-right corner of Figure 13. Most specification sheets are broken down into maximum ratings,
thermal characteristics, and electrical characteristics.
The electrical characteristics are further broken down into “on,” “off,” and small-signal characteristics.
The “on” and “off” characteristics refer to dc limits, whereas the small-signal characteristics include
the parameters of importance to ac operation.
Note in the maximum rating list that 𝑉𝐶𝐸𝑚𝑎𝑥 = 𝑉𝐶𝐸𝑂 = 30 V with 𝐼𝐶𝑚𝑎𝑥 = 200 mA. The maximum collector
dissipation 𝑃𝐶𝑚𝑎𝑥 = PD = 625 mW. The derating factor under the maximum rating specifies that the
maximum rating must be decreased 5 mW for every 1° rise in temperature above 25°C.
In the “off” characteristics 𝐼𝐶𝐵𝑂 is specified as 50 nA and in the “on” characteristics 𝑉𝐶𝐸𝑠𝑎𝑡 = 0.3 V. The
level of ℎ𝐹𝐸 has a range of 50 to 150 at 𝐼𝐶 = 2𝑚𝐴 and 𝑉𝐶𝐸 = 1V and a minimum value of 25 at a higher
current of 50 mA at the same voltage.
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Figure 13.0 Sample transistor specification sheet.

The limits of operation have now been defined for the device using ℎ𝐹𝐸 = 150 (the upper limit) and
𝐼𝐶𝐸𝑂 ≅ 𝛽𝐼𝐶𝐵𝑂 = (150) (50 nA) = 7.5 µA. Certainly, for many applications the 7.5 µA 0.0075 mA
can be considered to be 0 mA on an approximate basis.
Limits of Operation
7.5 µA ≤ 𝐼𝐶 ≤ 200 𝑚𝐴
0.3 𝑉 ≤ 𝑉𝐶𝐸 ≤ 30 𝑉
𝑉𝐶𝐸𝑂 𝐼𝐶 ≤ 650 𝑚𝑊
𝛽 Variation
In the small-signal characteristics the level of ℎ𝑓𝑒 (𝛽𝑎𝑐 ) is provided along with a plot of how it varies
with collector current in Figure 14.0. In Figure 15.0 the effect of temperature and collector current
on the level of ℎ𝐹𝐸 (𝛽𝑑𝑐 ) is demonstrated. At room temperature (25°C), note that ℎ𝐹𝐸 (𝛽𝑑𝑐 ) is a
maximum value of 1 in the neighborhood of about 8 mA. As 𝐼𝐶 increases beyond this level, ℎ𝐹𝐸
drops off to one-half the value with 𝐼𝐶 equal to 50 mA. It also drops to this level if 𝐼𝐶 decreases to
the low level of 0.15 mA.
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Since this is a normalized curve, if we have a transistor with 𝛽𝑑𝑐 = ℎ𝐹𝐸 = 120 at room temperature
(25°C), the maximum value at 8 mA is 120. At 𝐼𝐶 = 50 mA it has dropped to about 0.52 and ℎ𝑓𝑒 =
(0.52)120 = 62.4.
In other words, normalizing reveals that the actual level of ℎ𝐹𝐸 at any level of 𝐼𝐶 has been divided
by the maximum value of ℎ𝐹𝐸 at that temperature and 𝐼𝐶 = 8 mA.
Figure 14. 𝛽 versus 𝐼𝐶
Figure 15. effect of temperature and collector current on the level of ℎ𝐹𝐸 (𝛽𝑑𝑐 )
Capacitance Variation
The capacitance 𝐶𝑖𝑏𝑜 and 𝐶𝑜𝑏𝑜 of Figure 16 are the input and output capacitance levels,
respectively, for the transistor in the common-base configuration. Their level is such that their
impact can be ignored except for relatively high frequencies. Otherwise, they can be
approximated by open circuits in any dc or ac analysis.
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Figure 16. Capacitance Variation
Switching Times
Figure 17 includes the important parameters that define the response of a transistor to an input
that switches from the “off” to “on” state or vice versa.
Figure 17. Capacitance
2.1 Transistor Casing and Terminal Identification
Figure 18. Various types of general-purpose or switching transistors:

(a) low power; (b) medium power; (c) medium to high power.
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Figure 19. Transistor terminal identification.
The internal construction of a TO-92 package in the Fairchild line appears in Figure 20.0.
Note the very small size of the actual semiconductor device. There are gold bond wires,
a copper frame, and an epoxy encapsulation.
Figure 20.0 Internal construction of a Fairchild transistor in a TO-92 package.
3.0 BJT Transistor Biasing Techniques
The analysis or design of a transistor amplifier requires a knowledge of both the dc and the ac
response of the system. Too often it is assumed that the transistor is a magical device that can
raise the level of the applied ac input without the assistance of an external energy source.
In actual, any increase in ac voltage, current, or power is the result of a transfer of energy from
the applied dc supplies. The analysis or design of any electronic amplifier therefore has two
components: a dc and an ac portion. Fortunately, the superposition theorem is applicable, and
the investigation of the dc conditions can be totally separated from the ac response. However,
one must keep in mind that during the design or synthesis stage the choice of parameters for the
required dc levels will affect the ac response, and vice versa.
Use of the following important basic relationships for a transistor analysis and design;
𝑽𝑩𝑬 ≅ 𝟎. 𝟕 𝑽 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 #𝟏𝟗
𝑰𝑬 = (𝜷 + 𝟏)𝑰𝑩 ≅ 𝑰𝑪 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟎
𝑰𝑪 = 𝜷𝑰𝑩 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟏
In most instances the base current 𝐼𝐵 is the first quantity to be determined. Once 𝐼𝐵 is known, the
relationships of Equation # 19 through # 21 can be applied to find the remaining quantities of
interest. The similarities in analysis will be immediately obvious as we progress through the
module. The equations for 𝐼𝐵 are so similar for a number of configurations that one equation can
be derived from another simply by dropping or adding a term or two.
.
3.1 Operating Point
The term biasing means the application of dc voltages to establish a fixed level of current
and voltage for proper operation. For transistor amplifiers the resulting dc current and
voltage establish an operating point on the characteristics that define the region that will
be employed for amplification of the applied signal. Because the operating point is a fixed
point on the characteristics, it is also called the quiescent point (abbreviated Q -point).
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By definition, quiescent means quiet, still, inactive. Figure 21 shows a general output
device characteristic with four operating points indicated.
The biasing circuit can be designed to set the device operation at any of these points or
others within the active region. The maximum ratings are indicated on the characteristics
of Figure shown by a horizontal line for the maximum collector current 𝐼𝐶𝑚𝑎𝑥 and a vertical
line at the maximum collector-to-emitter voltage 𝑉𝐶𝐸𝑚𝑎𝑥 . The maximum power constraint is
defined by the curve 𝑃𝐶𝑚𝑎𝑥 in the same figure.
At the lower end of the scales are the cutoff region, defined by 𝐼𝐵 ≤ 0 µ𝐴, and the
saturation region, defined by 𝑉𝐶𝐸 ≤ 𝑉𝐶𝐸𝑠𝑎𝑡 .
Figure 21.0 Various operating points within the limits of operation of a transistor.
(Operating Points---A, B, C, & D)
For the BJT to be biased in its linear or active operating region the following must be true:
1. The base–emitter junction must be forward-biased (p-region voltage more positive),

with a resulting forward-bias voltage of about 0.6 V to 0.7 V.
2. The base–collector junction must be reverse-biased (n-region more positive),with the

reverse-bias voltage being any value within the maximum limits of the device.
Operation in the cutoff, saturation, and linear regions of the BJT characteristic are provided
as follows:
1. Linear-region operation:
Base–emitter junction forward-biased
Base–collector junction reverse-biased
2. Cutoff-region operation:
Base–emitter junction reverse-biased
Base–collector junction reverse-biased
3. Saturation-region operation:
Base–emitter junction forward-biased
Base–collector junction forward-biased
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3.2 Fixed-Bias Configuration
The fixed-bias circuit of Figure 22 is the simplest transistor dc bias configuration. Even
though the network employs an npn transistor, the equations and calculations apply
equally well to a pnp transistor configuration merely by changing all current directions and
voltage polarities. The current directions of Figure 22 are the actual current directions, and
the voltages are defined by the standard double-subscript notation.
For the dc analysis the network can be isolated from the indicated ac levels by replacing
the capacitors with an open-circuit equivalent because the reactance of a capacitor is a
function of the applied frequency. The frequency of dc is 0 Herts, f = 0 Hz, and 𝑋𝐶 =
1 1
𝜋𝑓𝐶 = 2 𝜋(0)𝐶 = ∞ Ω. In addition, the dc supply 𝑉𝐶𝐶 can be separated into two supplies
2
(for analysis purposes only) as shown in Figure 23.0 to permit a separation of input and
output circuits. It also reduces the linkage between the two to the base current 𝐼𝐵 .
Figure 22. Fixed-biased circuit Figure 23. DC equivalent circuit
Base-Emitter Loop
First step is to determine the base–emitter circuit loop equation of Figure 22. Writing
Kirchhoff’s voltage equation (KVL) in the clockwise direction for the loop, we obtain
+𝑽𝑪𝑪 − 𝑰𝑩 𝑹𝑩 − 𝑽𝑩𝑬 = 𝟎 (𝒗𝒆𝒓𝒚 𝒊𝒎𝒑𝒐𝒓𝒕𝒂𝒏𝒕 𝒆𝒒𝒖𝒂𝒕𝒊𝒐𝒏)
Figure 24. Base-emitter loop
Note the polarity of the voltage drop across 𝑅𝐵 as established by the indicated direction of
𝐼𝐵 . Solving the equation for the current 𝐼𝐵 results in the following:
𝑽𝑪𝑪 − 𝑽𝑩𝑬
𝑰𝑩 = 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟏
𝑹𝑩
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Collector-Emitter Loop
The collector–emitter section of the network appears in Figure 25 with the indicated
direction of current 𝐼𝐶 and the resulting polarity across 𝑅𝐶 . Applying Kirchhoff’s voltage law
in the clockwise direction around the output of the amplifier and considering the polarities
of supply and 𝑉𝐶𝐸 results to:
+𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐸 = 0
Figure 25. Collector-emitter loop
And
𝑽𝑪𝑬 = 𝑽𝑪𝑪 − 𝑰𝑪 𝑹𝑪 ( 𝒗𝒆𝒓𝒚 𝒊𝒎𝒑𝒐𝒓𝒕𝒂𝒏𝒕 𝒆𝒒𝒖𝒂𝒕𝒊𝒐𝒏)
This equation states that the voltage across the collector–emitter region of a transistor in
the fixed-bias configuration is the supply voltage less the drop across 𝑅𝐶 .
The magnitude of the collector current is related directly to 𝐼𝐵 through
𝐼𝐶 = 𝛽𝐼𝐵
The single- and double-subscript notation represents the voltage drops across a given
resistor or components or a circuit. Normally, for single-subscript notation, the reference
is the ground or the 0 volt potential, indicated as;
𝑉𝐶 , 𝑉𝐵, 𝑉𝐸 , etc
That is, the voltage measured or calculated is equal to the voltage across the point 𝑉𝐶 with
respect to ground reference. While the double-subscript, measures the voltage across the
two point indicated by the two letters of the subscripts such example:
𝑉𝐶𝐸 , 𝑉𝐶𝐵 , 𝑉𝐵𝐸 , 𝑒𝑡𝑐
That is, the voltage being determined is the voltage drop across the two points: between
collector terminal and emitter terminal as for 𝑉𝐶𝐸 .
Also
𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸
Where 𝑉𝐶𝐸 is the voltage from collector to emitter and 𝑉𝐶 and 𝑉𝐸 are the voltages from
collector and emitter to ground, respectively. In this case, since 𝑉𝐸 = 0𝑉 for fixed-biased
because of the missing resistor at the emitter terminal, we have
𝑉𝐶𝐸 = 𝑉𝐶
In addition
𝑉𝐵𝐸 = 𝑉𝐵 − 𝑉𝐸
And 𝑉𝐸 = 0𝑉, then
𝑉𝐵𝐸 = 𝑉𝑩
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Example # 1:
Determine the following for the fixed-bias configuration of Figure 26.0

a. 𝐼𝐵𝑞 and 𝐼𝐶𝑞 .
b. 𝑉𝐶𝐸𝑞
c. 𝑉𝐵 and 𝑉𝐶
d. 𝑉𝐵𝐶
Figure 26. DC fixed-bias circuit for Example # 1.
Solution:
First step is to get the dc equivalent circuit by neglecting the effects of the capacitors because
they are considered open circuit in dc ( 0 Hz).
a. Now, applying KVL at the input section of the amplifier, resulting to:
Base-emitter loop equation:

+𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 = 0
And solving for the base current 𝐼𝐵
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵
𝐼𝐵 = 47.0833 µA (store it in your calculator’s memories for the succeeding calculations)
Solving for the collector current;

Note: recall your calculator memory for the value of the base current.
𝑰𝑪 = 𝟐. 𝟑𝟓𝟒𝟐 𝒎𝑨 (again, store it in your calculator’s memories)
b. Apply KVL in clockwise direction at the output of your amplifier ( collector-to-emitter loop)
Collector-emitter loop equation:
+𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐸 = 0
And solving for the collector to emitter voltage

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
𝑽𝑪𝑬 = 𝟔. 𝟖𝟐𝟎𝟖 𝑽
c. Solving for 𝑉𝐵 , we have

𝑉𝐵𝐸 = 𝑉𝐵 − 𝑉𝐸
But
𝑉𝐸 = 0 𝑉𝑜𝑙𝑡
therefore
𝑉𝐵 = 𝑉𝐵𝐸 = 𝟎. 𝟕 𝑽
Solving for 𝑉𝐶 , from
Then 𝑽𝑪 = 𝑽𝑪𝑬 = 𝟔. 𝟖𝟐𝟎𝟖 𝑽
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d. Solving for 𝑉𝐵𝐶 , from the double-subscript notation yields
𝑉𝐵𝐶 = 𝑉𝐵 − 𝑉𝐶
𝑉𝐵𝐶 = 0.7 𝑉 − 6.8208 𝑉
𝑽𝑩𝑪 = −𝟔. 𝟏𝟐𝟎𝟖 𝑽
with the negative sign revealing that the junction is reversed-biased, as it should be for linear
amplification. That is, the true polarity of the voltage drop from the Figure 26.0 should be reversed.
Transistor Saturation
The term saturation is applied to any system where levels have reached their maximum values.
A saturated sponge is one that cannot hold another drop of water. For a transistor operating in
the saturation region, the current is a maximum value for the particular design. Change the
design and the corresponding saturation level may rise or drop. Of course, the highest saturation
level is defined by the maximum collector current as provided by the specification sheet.
Saturation conditions are normally avoided because the base–collector junction is no longer
reverse-biased and the output amplified signal will be distorted. An operating point in the
saturation region is depicted in Figure 27.
Note that it is in a region where the characteristic curves join and the collector-to-emitter voltage
is at or below 𝑉𝐶𝐸𝑠𝑎𝑡 . In addition, the collector current is relatively high on the characteristics.
(a) (b)
Figure 27.0 Saturation regions: (a) actual; (b) approximate.
If we approximate the curves of Figure 27(a) by those appearing in Figure 27(b), a quick, direct
method for determining the saturation level becomes apparent. In Figure 27(b), the current is
relatively high, and the voltage 𝐕𝐂𝐄 is assumed to be 0 V. Applying Ohm’s law, we can determine
the resistance between collector and emitter terminals as follows:
𝑉𝐶𝐸 0𝑉
𝑅𝐶𝐸 = = =0Ω
𝐼𝐶 𝐼𝐶𝑠𝑎𝑡
Applying the results to the network schematic results in the configuration of Figure 28.
Figure 28. Determining 𝐼𝐶𝑠𝑎𝑡 of a given transistor
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Determining 𝑰𝑪𝒔𝒂𝒕 of Fixed-Bias Configuration
Figure 29. Determining 𝐼𝐶𝑠𝑎𝑡 for the fixed-bias configuration.
In determining the 𝐼𝐶𝑠𝑎𝑡 of any transistor amplifier just set first the value of 𝑉𝐶𝐸 = 0𝑉. Then, second
step is applying KVL around the output loop or collector- emitter loop to calculate the 𝐼𝐶𝑠𝑎𝑡 .The
resulting equation for the fixed-bias configuration is;
+𝑉𝐶𝐶 − 𝐼𝐶𝑠𝑎𝑡 𝑅𝐶 − 𝑉𝐶𝐸 = 0

And
𝑽𝑪𝑪
𝑰𝑪𝒔𝒂𝒕 = 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟐
𝑹𝑪
Once 𝐼𝐶𝑠𝑎𝑡 is known, we have some idea of the maximum possible collector current for the chosen
design and the level to stay below if we expect linear amplification.
Example # 2:
Determine the saturation level for the network of Figure 30.
Figure 30. DC fixed-bias circuit for Example # 1.
Solution:
Applying KVL at the output section;

+𝑉𝐶𝐶 − 𝐼𝐶𝑠𝑎𝑡 𝑅𝐶 − 𝑉𝐶𝐸 = 0
Set 𝑉𝐶𝐸 = 0𝑉, and solving the 𝐼𝐶𝑠𝑎𝑡
we have
𝑉𝐶𝐶 12𝑉
𝐼𝐶𝑠𝑎𝑡 = = = 𝟓. 𝟒𝟓 𝒎𝑨
𝑅𝐶 2.2𝑘Ω
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3.3 Emitter-Bias Configuration
The dc bias network of Figure 31 contains an emitter resistor to improve the stability level
over that of the fixed-bias configuration. The more stable a configuration, the less its
response will change due to undesirable changes in temperature and parameter
variations. The improved stability will be demonstrated through a numerical example. The
analysis will be performed by first examining the base–emitter-loop and then using the
results to investigate the collector–emitter loop. The dc equivalent of Figure 31 appears in
Figure 32 with a separation of the source to create an input and output section.
Figure 31. BJT bias circuit with emitter resistor. Figure 32. DC equivalent ckt of Figure 31.
Base-Emitter Loop
The base–emitter loop of the network of Figure 32.0 can be redrawn as shown in Figure
33. Writing Kirchhoff’s voltage law around the indicated loop in the clockwise direction
results in the following equation:
+𝑽𝑪𝑪 − 𝑰𝑩 𝑹𝑩 − 𝑽𝑩𝑬 − 𝑰𝑬 𝑹𝑬 = 𝟎 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟑
Figure 33. Base-emitter loop
But the current 𝐼𝐸

𝐼𝐸 = (𝛽 + 1)𝐼𝐵
Substituting for 𝐼𝐸 in equation # 23.0 results in
𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 − (𝛽 + 1)𝐼𝐵 𝑅𝐸 = 0

Grouping the terms
−𝐼𝐵 (𝑅𝐵 + (𝛽 + 1)𝑅𝐸 ) − 𝑉𝐶𝐶 − 𝑉𝐵𝐸 = 0
Multiplying through by (-1), we have

IM No. 08: ECE01-2S-2022-2023
𝐼𝐵 (𝑅𝐵 + (𝛽 + 1)𝑅𝐸 ) − 𝑉𝐶𝐶 + 𝑉𝐵𝐸 = 0

With
𝐼𝐵 (𝑅𝐵 + (𝛽 + 1)𝑅𝐸 ) = 𝑉𝐶𝐶 − 𝑉𝐵𝐸
And solving for the 𝐼𝐵 gives
𝑽𝑪𝑪 − 𝑽𝑩𝑬
𝑰𝑩 = 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟒
𝑹𝑩 + (𝜷 + 𝟏)𝑹𝑬
Important Concept
There is an interesting result that can be derived from Equation # 24 if the equation is
used to sketch a series network that would result in the same equation. Such is the case
for the network of Figure 34.0. Solving for the current 𝐼𝐵 results in the same equation as
obtained above. Note that aside from the base-to-emitter voltage 𝑉𝐵𝐸 , the resistor 𝑅𝐸 is
reflected back to the input base circuit by a factor (𝛽 + 1). In other words, the emitter
resistor, which is part of the collector–emitter loop, “appears as” (𝛽 + 1)𝑅𝐸 in the base–
emitter loop. Because 𝛽 is typically 50 or more, the emitter resistor appears to be a great
deal larger in the base circuit. In general, therefore, for the configuration of Figure 35,
𝑹𝒊 = (𝜷 + 𝟏)𝑹𝑬 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟓
Figure 34. Network derived from Equation # 24
Figure 35. Reflected impedance level of 𝑅𝐸
The collector–emitter loop appears in Figure 36.0. Writing Kirchhoff’s voltage law for the
indicated loop in the clockwise direction results in
+𝐼𝐸 𝑅𝐸 + 𝑉𝐶𝐸 + 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐶 = 0
Substituting 𝐼𝐸 ≅ 𝐼𝐶 and grouping terms gives
𝑉𝐶𝐸 − 𝑉𝐶𝐶 + 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 ) = 0

And
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 )
IM No. 08: ECE01-2S-2022-2023
Figure 36. Collector-emitter loop
The single-subscript voltage 𝑉𝐸 is the voltage from emitter to ground and is determined
by
𝑉𝐸 = 𝐼𝐸 𝑅𝐸
whereas the voltage from collector to ground can be determined from
And
𝑉𝐶 = 𝑉𝐶𝐸 − 𝑉𝐸
Or
𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
The voltage at the base with respect to ground can be determined by
𝑉𝐵 = 𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵
or
𝑉𝐵 = 𝑉𝐵𝐸 − 𝑉𝐸
Example # 3:
For the emitter-bias network of Fig. 37, determine:
a. 𝐼𝐵𝑞
b. 𝐼𝐶𝑞 .
c. 𝑉𝐶𝐸𝑞
d. 𝑉𝐶
e. 𝑉𝐸
f. 𝑉𝐵
g. 𝑉𝐵𝐶
Figure 37.0 Emitter-stabilized bias circuit for Example # 3.
Solution:
Step # 1: Transformed the circuit in a dc equivalent circuit by removing the capacitors because
they are considered open-circuit in the dc analysis.
a. Base-emitter loop
Applying KVL around in clock-wise direction in the input section of the amplifier resulting to,
+𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 − 𝐼𝐸 𝑅𝐸 = 0
IM No. 08: ECE01-2S-2022-2023
But 𝐼𝐸 = (𝛽 + 1)𝐼𝐵 , substituting ti the above equation
+𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 − (𝛽 + 1)𝐼𝐵 𝑅𝐸 = 0

Solving for 𝐼𝐵
𝐼𝐵 =
𝑅𝐵 + (𝛽 + 1)𝑅𝐸
20𝑉−0.7𝑉
= 430𝐾Ω+(51)(1𝐾Ω)
= 𝟒𝟎. 𝟏𝟐𝟒𝟕 µ𝑨 ;(store this in your calculator)
b. 𝐼𝐶 = 𝛽𝐼𝐵
= (50)(𝐼𝐵 ) ; recall the value of 𝐼𝐵 in your calculator
= 2.0062mA
c. Collector-Emitter loop
𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸 𝑅𝐸 = 0
Solving for 𝑉𝐶𝐸 , and 𝐼𝐸 ≅ 𝐼𝐶
= 20𝑉 − 𝐼𝐶 (2𝐾Ω + 1𝐾Ω)
= 𝟏𝟑. 𝟗𝟖𝟏𝟐𝟖𝟖𝟗𝟖 𝑉; (store)

d. 𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
= 20𝑉 − 𝐼𝐶 (2𝐾Ω)
= 𝟏𝟓. 𝟗𝟖𝟕𝟓𝟐𝟓𝟗𝟗𝑽 ; (store)
e. 𝑉𝐸 = 𝑉𝐶 − 𝑉𝐶𝐸
= 𝟐. 𝟎𝟎𝟔𝟐𝟑𝟕𝟎𝟎𝟔 𝑽
Another solution is using 𝑉𝐸 = 𝐼𝐸 𝑅𝐸 ≅ 𝐼𝐶 𝑅𝐸
= 𝟐. 𝟎𝟎𝟔𝟐𝟑𝟕𝟎𝟎𝟔𝑽
f. 𝑉𝐵 = 𝑉𝐵𝐸 + 𝑉𝐸
= 0.7V + 𝑉𝐸
= 𝟐. 𝟕𝟎𝟔𝟐𝟑𝟕𝟎𝟎𝟔𝑽
g. 𝑉𝐵𝐶 = 𝑉𝐵 − 𝑉𝐶
= −𝟏𝟑. 𝟐𝟖𝟏𝟐𝟖𝟖𝟗𝟖𝑽
(negative because it is reverse-biased as requirement)
Saturation Level
The collector saturation level or maximum collector current for an emitter-bias design can be
determined using the same approach applied to the fixed-bias configuration: Apply a short circuit
between the collector–emitter terminals as shown in Figure 38.0 and calculate the resulting
collector current.
𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸 𝑅𝐸 = 0
And solving for 𝐼𝐶𝑠𝑎𝑡

𝑉𝐶𝐶
𝐼𝐶𝑠𝑎𝑡 =
𝑅𝐶 + 𝑅𝐸
IM No. 08: ECE01-2S-2022-2023
Figure 38. Determining 𝐼𝐶𝑠𝑎𝑡 for the emitterstabilized bias circuit.
Example # 4
Determine the saturation current for the network of Example # 3.
Solution:
𝑉𝐶𝐶 20𝑉
𝐼𝐶𝑠𝑎𝑡 = =
𝑅𝐶 + 𝑅𝐸 2𝐾Ω + 1𝐾Ω
= 𝟔. 𝟔𝟔𝟔𝟔𝟔𝟔𝟕𝒎𝑨
3.4 Voltage-Divider Bias Configuration
The 𝛽 is temperature sensitive, especially for silicon transistors, and the actual value of
beta is usually not well defined. Now, it would be desirable to develop a bias circuit that is
less dependent on, or in fact is independent of, the transistor beta. The voltage-divider
bias configuration of Figure 39 is such a network.
Figure 39. Voltage-divider bias configuration.
If analyzed on an exact basis, the sensitivity to changes in beta is quite small. If the circuit
parameters are properly chosen, the resulting levels of 𝐼𝐶𝑞 and 𝑉𝐶𝐸𝑞 can be almost totally
independent of beta. Recall from previous discussions that a Q -point is defined by a fixed
level of 𝐼𝐶𝑞 and 𝑉𝐶𝐸𝑞 as shown in Figure 40.
IM No. 08: ECE01-2S-2022-2023
Figure 40.0 Defining the Q-point for the voltage-divider bias

configuration.
The level of 𝐼𝐵𝑞 will change with the change in beta, but the operating point on the
characteristics defined by 𝐼𝐶𝑞 and 𝑉𝐶𝐸𝑞 can remain fixed if the proper circuit parameters are
employed.
Exact Analysis
The dc analysis of the network of Figure 39. can be redrawn as shown in Figure 41. The
input side of the network can then be redrawn as shown in Figure 42 for the dc analysis.
Figure 41. DC components of the voltage-divider configuration.
Figure 42. Redrawing the input side of the network of Figure 39.
The Thévenin equivalent network for the network to the left of the base terminal can then
be found in the following manner:
𝑹𝑻𝒉 : The voltage source is replaced by a short-circuit equivalent as shown in Figure 43.
IM No. 08: ECE01-2S-2022-2023
Figure 43. Determining 𝑅𝑇ℎ
𝑹𝑻𝒉 = 𝑹𝟏 //𝑹𝟐 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟔
(Note: 𝑅1 is in parallel connection with 𝑅2 )
𝑬𝑻𝒉 : The voltage source 𝑉𝐶𝐶 is returned to the network and the open-circuit Thévenin
voltage of Figure 44 is determined as follows:
Figure 44. Determining 𝐸𝑇ℎ
Applying the voltage-divider rule gives
𝑹𝟐 𝑽𝑪𝑪
𝑬𝑻𝒉 = 𝑽𝑹𝟐 = 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟕
𝑹𝟏 + 𝑹𝟐
The Thévenin network is then again redrawn as shown in Figure 45, and 𝐼𝐵𝑄 can be
determined by first applying Kirchhoff’s voltage law in the clockwise direction for the loop
indicated:
Figure 45. Inserting the Thévenin equivalent circuit.
𝐸𝑇ℎ − 𝐼𝐵 𝑅𝑇ℎ − 𝑉𝐵𝐸 − 𝐼𝐸 𝑅𝐸 = 0
Substituting 𝐼𝐸 = (𝛽 + 1)𝐼𝐵 , and solving for 𝐼𝐵 results in;
𝐸𝑇ℎ − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝑇ℎ − (𝛽 + 1)𝑅𝐸
Once 𝐼𝐵 is known, the remaining quantities of the network can be found in the same
manner as developed for the emitter-bias configuration. That is,
IM No. 08: ECE01-2S-2022-2023
which is exactly the same as for emitter-bias configuration. The remaining equations for
𝑉𝐸 , 𝑉𝐶 , and 𝑉𝐵 are also the same as obtained for the emitter-bias configuration.
Example # 5
Determine the dc bias voltage 𝑉𝐶𝐸 and the current 𝐼𝐶 for the voltage-divider configuration using the exact
solution of Figure 46.
Figure 46. Beta-stabilized circuit for Example # 5.
Solution:
First: determine the dc equivalent circuit by neglecting the effects of the capacitors.
Second: determine 𝑅𝑇ℎ and 𝐸𝑇ℎ ;

𝑅𝑇ℎ = 𝑅1 //𝑅2
(39𝐾Ω)(3.9𝐾Ω)
= 39𝐾Ω +3.9𝐾Ω
= 𝟑. 𝟓𝟒𝟓𝟒𝟓𝟒𝟓𝟒𝟓𝟒 𝑲Ω
𝑉𝐶𝐶 𝑅2
𝐸𝑇ℎ =
𝑅1 + 𝑅2
(22𝑉)(3.9𝐾Ω)
=
39𝐾Ω+3.9𝐾Ω
= 𝟐. 𝟎 𝑽
Solving for 𝐼𝐵
𝐸𝑇ℎ − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝑇ℎ − (𝛽 + 1)𝑅𝐸
2.0𝑉−0.7𝑉
= 𝑅𝑇ℎ −(101)(1.5𝐾Ω
= 𝟖. 𝟑𝟖𝟒𝟔𝟑𝟕𝟗𝟑𝟔 µ𝑨
Solving for 𝐼𝐶
= (100)𝐼𝐵
= 𝟖𝟑𝟖. 𝟒𝟔𝟑𝟕𝟗𝟑𝟔 µ𝑨
Solving for 𝑉𝐶𝐸
IM No. 08: ECE01-2S-2022-2023
= 22𝑉 − 𝐼𝐶 (10𝐾Ω + 1.5𝐾Ω)
= 𝟏𝟐. 𝟑𝟓𝟕𝟔𝟔𝟔𝟑𝟕𝑽
Approximate Analysis
The input section of the voltage-divider configuration can be represented by the network of Figure 47.
The resistance 𝑅𝑖 is the equivalent resistance between base and ground for the transistor with an emitter
resistor 𝑅𝐸 . Recall that the reflected resistance between base and emitter is defined by 𝑅𝑖 = (𝛽 + 1)𝑅𝐸 .
If 𝑅𝑖 is much larger than the resistance 𝑅2 , the current 𝐼𝐵 will be much smaller than 𝐼2 (current always
seeks the path of least resistance) and 𝐼2 will be approximately equal to 𝐼1 . If we accept the approximation
that 𝐼𝐵 is essentially 0 A compared to 𝐼1 or 𝐼2 , then 𝐼1 = 𝐼2 , and 𝑅1 and 𝑅2 can be considered series
elements. The voltage across 𝑅2 , which is actually the base voltage, can be determined
Figure 47.0 Partial-bias circuit for calculating the approximate base voltage 𝑉𝐵 .
using the voltage-divider rule (hence the name for the configuration). That is,
𝑉𝐶𝐶 𝑅2
𝑉𝐵 =
𝑅1 + 𝑅2
Because 𝑅𝑖 = (𝛽 + 1)𝑅𝐸 ≅ 𝛽𝑅𝐸 the condition that will define whether the approximate approach
can be applied is
𝜷𝑹𝑬 ≥ 𝟏𝟎 𝑹𝟐 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐𝟖
(Important Note: this equation needs to be satisfied if you are going to used approximate analysis)
In other words, if 𝛽 times the value of 𝑅𝐸 is at least 10 times the value of 𝑅2 , the approximate
approach can be applied with a high degree of accuracy.
Once 𝑉𝐵 is determined, the level of 𝑉𝐸 can be calculated from
𝑉𝐸 = 𝑉𝐵 − 𝑉𝐵𝐸
And the emitter current can be determined from
𝐼𝐸 = 𝑉𝐸 /𝑅𝐸
And
𝐼𝐶𝑄 ≅ 𝐼𝐸
The collector-to-emitter voltage is determined by

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝐼𝐸 𝑅𝐸
But because 𝐼𝐸 ≅ 𝐼𝐶
𝑉𝐶𝐸𝑄 = 𝑉𝐶𝐶 − 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 )
IM No. 08: ECE01-2S-2022-2023
Example # 6
Repeat the analysis of Example # 5 using the approximate technique, and compare solutions for 𝐼𝐶𝑄 and
𝑉𝐶𝐸𝑄 .
Solution:
Testing:
𝛽𝑅𝐸 ≥ 10𝑅2
(100)(1.5𝐾Ω) ≥ 10 (3.9𝐾Ω)
150 𝐾Ω ≥ 39 𝐾Ω
𝑺𝒂𝒕𝒊𝒔𝒇𝒊𝒆𝒅
(meaning, we can use the approximate analysis with acceptable error)
Solving for 𝑉𝐵
𝑉𝐶𝐶 𝑅2
𝑉𝐵 =
𝑅1 + 𝑅2
(3.9𝐾Ω)(22𝑉)
= (39𝐾Ω+3.9𝐾Ω)
= 2.0 𝑉
Solving 𝑉𝐸
𝑉𝐸 = 𝑉𝐵 − 𝑉𝐵𝐸
= 2.0𝑉 − 0.7𝑉
= 𝟏. 𝟑𝑽
Solving for 𝐼𝐶𝑄
𝑉𝐸
𝐼𝐶𝑄 =
𝑅𝐸
1.3𝑉
= 1.5𝐾Ω
= 𝟖𝟔𝟔. 𝟔𝟔𝟔𝟔𝟔𝟔𝟕µ𝑨
= 22𝑉 − 𝐼𝐶𝑄 (10𝐾Ω + 1.5𝐾Ω)
= 𝟏𝟐. 𝟎𝟑𝟑𝟑𝟑𝟑𝟑𝑽
Table 1. Comparison for Exact and Approximate
Exact Analysis Approximate Percent Error

Analysis
𝐼𝐶𝑄 838.4637936 µ𝐴 866.6666667µ𝐴 3.36%
𝑉𝐶𝐸𝑄 12.35766637𝑉 12.0333333𝑉 2.62%
IM No. 08: ECE01-2S-2022-2023
The output collector–emitter circuit for the voltage-divider configuration has the same appearance as the
emitter-biased circuit analyzed. The resulting equation for the saturation current (when 𝑉𝐶𝐸 is set to 0 V
on the schematic) is therefore the same as obtained for the emitter-biased configuration. That is,
𝑉𝐶𝐶
𝑅𝐶 + 𝑅𝐸
3.5 Collector Feedback Configuration
An improved level of stability can also be obtained by introducing a feedback path from collector
to base as shown in Figure 49. Although the Q -point is not totally independent of beta (even
under approximate conditions), the sensitivity to changes in beta or temperature variations is
normally less than encountered for the fixed-bias or emitter-biased configurations.
The analysis will again be performed by first analyzing the base–emitter loop, with the results then
applied to the collector–emitter loop.
Figure 49. DC bias circuit with voltage feedback.
Base-Emitter Loop
The base–emitter loop for the voltage feedback configuration is shown in Figure 50. Writing
Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in
𝑉𝐶𝐶 − 𝐼 ′ 𝐶 𝑅𝐶 − 𝐼𝐵 𝑅𝐹 − 𝑉𝐵𝐸 − 𝐼𝐸 𝑅𝑅 = 0
Figure 50. Base–emitter loop for the network of Figure 49.0
It is important to note that the current through 𝑅𝐶 is not 𝐼𝐶 , but 𝐼′𝐶 (where 𝐼′𝐶 = 𝐼𝐶 + 𝐼𝐵 ).
However, the level of 𝐼𝐶 and 𝐼′𝐶 far exceeds the usual level of 𝐼𝐵 , and the approximation 𝐼′𝐶 = 𝐼𝐶
is normally employed. Substituting 𝐼′𝐶 = 𝐼𝐶 = 𝛽𝐼𝐵 and 𝐼𝐸 ≅ 𝐼𝐶 results in
𝑉𝐶𝐶 − 𝛽𝐼𝐵 𝑅𝐶 − 𝐼𝐵 𝑅𝐹 − 𝑉𝐵𝐸 − 𝛽𝐼𝐵 𝑅𝐸 = 0

IM No. 08: ECE01-2S-2022-2023
Gathering terms, we have

𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝛽𝐼𝐵 (𝑅𝐶 + 𝑅𝐸 ) − 𝐼𝐵 𝑅𝐹 = 0
And solving for 𝐼𝐵 yields
𝐼𝐵 =
𝑅𝐹 + 𝛽(𝑅𝐶 + 𝑅𝐸 )
The collector–emitter loop for the network of Figure 50.0 is provided in Figure 51. Applying
Kirchhoff’s voltage law around the indicated loop in the clockwise direction results in
𝐼𝐸 𝑅𝐸 + 𝑉𝐶𝐸 + 𝐼′𝐶 𝑅𝐶 − 𝑉𝐶𝐶 = 0
But 𝐼′𝐶 ≅ 𝐼𝐶 and 𝐼𝐸 ≅ 𝐼𝐶 , we have
𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 ) + 𝑉𝐶𝐸 − 𝑉𝐶𝐶 = 0

And
which is exactly as obtained for the emitter-bias and voltage-divider bias configurations.
Figure 51. Collector–emitter loop for the given network
Example # 7:
Determine the quiescent levels of 𝐼𝐶𝑄 and 𝑉𝐶𝐸𝑄 for the network of Figure 52.
Figure 52. Network for Example 7
IM No. 08: ECE01-2S-2022-2023
Solution:
First step: determine the dc equivalent circuit by letting the capacitors open-circuited.
Solving for the base current 𝐼𝐵
𝐼𝐵 =
𝑅𝐹 + 𝛽(𝑅𝐶 + 𝑅𝐸 )
10𝑉−0.7𝑉
= 250𝐾Ω+(90)(4.7𝐾Ω+1.2𝐾Ω)
= 𝟏𝟏. 𝟗𝟎𝟕𝟖𝟏𝟎𝟓µ𝑨
Solving for collector current 𝐼𝐶
= (90)𝐼𝐵
= 𝟏. 𝟎𝟕𝟏𝟕𝟎𝟐𝟗𝟒𝟓𝒎𝑨
Solving for the collector-to-emitter voltage, 𝑉𝐶𝐸
= 10𝑉 − 𝐼𝐶 (4.7𝐾Ω + 1.2𝐾Ω)
= 𝟑. 𝟔𝟕𝟔𝟗𝟓𝟐𝟔𝟐𝟓 𝑽
Using the approximation 𝐼′𝐶 = 𝐼𝐶 , we find that the equation for the saturation current is the
same as obtained for the voltage-divider and emitter-bias configurations. That is,
𝑉𝐶𝐶
𝐼𝐶𝑠𝑎𝑡 = 𝐼𝐶𝑚𝑎𝑥 =
𝑅𝐶 + 𝑅𝐸
3.6 Emitter-Follower Configuration
This lesson will examine a configuration where the output is taken off the emitter terminal as
shown in Figure 53. The dc equivalent of the network of Figure 53 appears in Figure 54.
Figure 53. Common-collector (emitter-follower) configuration.
IM No. 08: ECE01-2S-2022-2023
Figure 54. dc equivalent circuit of the Figure 53.
Applying Kirchhoff’s voltage rule to the input circuit will result in
−𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 − 𝐼𝐸 𝑅𝐸 + 𝑉𝐸𝐸 = 0

And using 𝐼𝐸 = (𝛽 + 1)𝐼𝐵
𝐼𝐵 𝑅𝐵 (𝛽 + 1)𝐼𝐵 𝑅𝐸 = 𝑉𝐸𝐸 − 𝑉𝐵𝐸

And finally;
𝑉𝐸𝐸 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵 + (𝛽 + 1)𝑅𝐸
For the output network, am application of Kirchhoff’s voltage law will result in
−𝑉𝐶𝐸 − 𝐼𝐸 𝑅𝐸 + 𝑉𝐸𝐸 = 0
And
𝑉𝐶𝐸 = 𝑉𝐸𝐸 − 𝐼𝐸 𝑅𝐸
Example # 8:
Determine the .𝐼𝐸𝑄 and 𝑉𝐶𝐸𝑄 of the network shown in Figure 55.
Figure 55. Network for Example # 8
IM No. 08: ECE01-2S-2022-2023
Solution:
First Step: determine the dc equivalent circuit by letting the capacitors open-circuited.
Solving for the value of 𝐼𝐵
𝐼𝐵 =
𝑅𝐵 + (𝛽 + 1)𝑅𝐸
20𝑉−0.7𝑉
= 240𝐾Ω+(91)(2𝐾Ω
= 𝟒𝟓. 𝟕𝟑𝟒𝟓𝟗𝟕𝟏𝟔 µ𝑨
Solving for 𝐼𝐸
𝐼𝐸 = (𝛽 + 1)𝐼𝐵
= (91)𝐼𝐵
= 𝟒. 𝟏𝟔𝟏𝟖𝟒𝟖𝟑𝟒𝟏 𝒎𝑨
𝑉𝐶𝐸 = 𝑉𝐸𝐸 − 𝐼𝐸 𝑅𝐸
= 20𝑉 − 𝐼𝐸 (2𝑘Ω)
= 𝟏𝟏. 𝟔𝟕𝟔𝟑𝟎𝟑𝟑𝟐 𝑽
3.7 Common-Base Configuration
The common-base configuration is unique in that the applied signal is connected to the emitter
terminal and the base is at, or just above, ground potential. It is a fairly popular configuration
because in the ac domain it has a very low input impedance, high output impedance, and good
gain.
A typical common-base configuration appears in Figure 56. Note that two supplies are used in
this configuration and the base is the common terminal between the input emitter terminal and
output collector terminal.
Figure 56. Common-base configuration.
The dc equivalent of the input side of Figure 56 appears in Figure 57.
Figure 57. Input dc equivalent of Figure 56.0.
IM No. 08: ECE01-2S-2022-2023
Applying Kirchhoff’s voltage law will result in
−𝑉𝐸𝐸 + 𝐼𝐸 𝑅𝐸 + 𝑉𝐵𝐸 = 0
𝐼𝐸 =
𝑅𝐸
Figure 58. Determining 𝑉𝐶𝐸 and 𝑉𝐶𝐵
Applying Kirchhoff’s voltage law to the entire outside perimeter of the network of Fig. 58 will result
in
−𝑉𝐸𝐸 + 𝐼𝐸 𝑅𝐸 + 𝑉𝐶𝐸 + 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐶 = 0

And solving for 𝑉𝐶𝐸
𝑉𝐶𝐸 = 𝑉𝐸𝐸 + 𝑉𝐶𝐶 − 𝐼𝐸 𝑅𝐸 − 𝐼𝐶 𝑅𝐶

But 𝐼𝐸 ≅ 𝐼𝐶
𝑉𝐶𝐸 = 𝑉𝐸𝐸 + 𝑉𝐶𝐶 − 𝐼𝐸 (𝑅𝐶 + 𝑅𝐸 )
The voltage 𝑉𝐶𝐵 of Figure 58 can be found by applying Kirchhoff’s voltage law to the output loop
of Figure 58 to obtain:
𝑉𝐶𝐵 + 𝐼𝐶 𝑅𝐶 + −𝑉𝐶𝐶 = 0
And
𝑉𝐶𝐵 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
Using 𝐼𝐶 ≅ 𝐼𝐸
𝑉𝐶𝐵 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
Example # 9:
Determine the currents 𝐼𝐸 and 𝐼𝐵 and the voltages 𝑉𝐶𝐸 and 𝑉𝐶𝐵 for the common-base configuration
of Figure 59.
Figure 59. Common-base network for Example # 9.
IM No. 08: ECE01-2S-2022-2023
Solution:
First Step: Neglect the effect of the capacitors by drawing a dc equivalent circuit with an open-
circuited capacitors.
Solving for 𝐼𝐸
𝐼𝐸 =
𝑅𝐸
4𝑉−.7𝑉
= 1.2 𝐾Ω
= 𝟐. 𝟕𝟓 𝒎𝑨
Solving for the base current 𝐼𝐵
𝐼𝐸
𝐼𝐵 =
(𝛽 + 1)
2.75𝑚𝐴
= 60+1
= 𝟒𝟓. 𝟎𝟖𝟏𝟗𝟔𝟕𝟐𝟏 µ𝑨
Solving for the collector-to-emitter voltage, 𝑉𝐶𝐸
𝑉𝐶𝐸 = 𝑉𝐸𝐸 + 𝑉𝐶𝐶 − 𝐼 𝐸 (𝑅 𝐶 + 𝑅 𝐸 )
= 4𝑉 + 10𝑉 − (2.75𝑚𝐴)(2.4𝐾Ω + 1.2𝐾Ω)
= 𝟒. 𝟏 𝑽
Solving for the collector-to-base voltage, 𝑉𝐶𝐵
𝑉𝐶𝐵 = 𝑉𝐶𝐶 − 𝐼 𝐶 𝑅 𝐶 = 𝑉𝐶𝐶 − 𝛽𝐼 𝐵 𝑅 𝐶
= 10𝑉 − (60)𝐼 𝐵 (2.4𝐾Ω)
= 𝟑. 𝟓𝟎𝟖𝟏𝟗𝟔𝟕𝟐𝟏𝑽
3.8 Miscellaneous Bias Configuration
There are a number of BJT bias configurations that do not match the basic model of those
analyzed in the previous lessons. In fact, there are variations in design that would require many
more pages than is possible in a single publication.
However, the primary purpose here is to emphasize those characteristics of the device that permit
a dc analysis of the configuration and to establish a general procedure toward the desired solution.
For each configuration discussed thus far, the first step has been the derivation of an expression
for the base current. Once the base current is known, the collector current and voltage levels of
the output circuit can be determined quite directly. This is not to imply that all solutions will take
this path, but it does suggest a possible route to follow if a new configuration is encountered.
IM No. 08: ECE01-2S-2022-2023
Example # 10:
For the network of Figure 60

a. Determine 𝐼𝐶𝑄 and 𝑉𝐶𝐸𝑄 .
b. Find 𝑉𝐵 , 𝑉𝐶 , 𝑉𝐸 , and 𝑉𝐵𝐶 .
Figure 60. Collector feedback with 𝑅𝐸 = 0Ω
Solution:
First Step: Disregard the effects of the capacitors by an open-circuit equivalent.
a. The absence of 𝑅𝐸 reduces the reflection of resistive levels to simply that of 𝑅𝐶 , and the
equation for 𝐼𝐵 reduces to
𝐼𝐵 =
𝑅𝐵 + 𝛽𝑅𝐶
20𝑉−0.7𝑉
= 680𝐾Ω+(120)(4.7𝐾Ω)
= 𝟏𝟓. 𝟓𝟏𝟒𝟒𝟔𝟗𝟒𝟓 µ𝑨
Solving for collector current
= (120)𝐼𝐵
= 𝟏. 𝟖𝟔𝟏𝟕𝟑𝟔𝟑𝟑𝟒 𝒎𝑨
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
= 20𝑉 − 𝐼𝐶 (4.7𝐾Ω)
= 𝟏𝟏. 𝟐𝟒𝟗𝟖𝟑𝟗𝟐𝟑 𝑽
b. Solving for 𝑉𝐵
𝑉𝐵 = 𝑉𝐵𝐸 = 𝟎. 𝟕𝑽
Solving for 𝑉𝐶
𝑉𝐶 = 𝑉𝐶𝐸 = 𝟏𝟏. 𝟐𝟒𝟗𝟖𝟑𝟗𝟐𝟑𝑽
Solving for 𝑉𝐸
𝑉𝐸 = 𝟎𝑽
Solving for 𝑉𝐵𝐶
𝑉𝐵𝐶 = 𝑉𝐵 − 𝑉𝐶
= 0.7𝑉 − 𝑉𝐶
= −𝟏𝟎. 𝟓𝟒𝟗𝟖𝟑𝟗𝟐𝟑𝑽
IM No. 08: ECE01-2S-2022-2023
Example # 11:
Determine 𝑉𝐶 and 𝑉𝐵 for the network of Figure 61.
Figure 61. Network for Example # 11
Solution:
Applying Kirchhoff’s voltage law in the clockwise direction for the base–emitter loop results in
−𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 + 𝑉𝐸𝐸 = 0

And
𝐼𝐵 =
𝑅𝐵
Substituting yields
9𝑉 − 0.7𝑉
𝐼𝐵 =
100𝐾Ω
8.3𝑉
= 100𝐾Ω
= 𝟖𝟑 µ𝑨
Solving for the collector current
= (45)(83µA)
= 3.735 𝑚𝐴
Solving for the collector voltage
𝑉𝐶 = −𝐼𝐶 𝑅𝐶
= −(3.735 𝑚𝐴)(1.2𝐾Ω)
= −𝟒. 𝟒𝟖𝟐 𝑽
Solving for the base voltage
𝑉𝐵 = −(𝐼𝐵 𝑅𝐵 )
= −𝟖. 𝟑 𝑽
IM No. 08: ECE01-2S-2022-2023
Example # 12:
Determine 𝑉𝐶 and 𝑉𝐵 for the network of Figure 62.
Figure 62.Network for Example # 12
Solution:
The Thévenin resistance and voltage are determined for the network to the left of the base
terminal as shown in Figure 63.0 and Figure 64.0.
𝑅𝑇ℎ :
𝑅𝑇ℎ = 𝑅1 //𝑅2
= 8.2𝐾Ω//2.2𝐾Ω
= 1.734615385 𝑘Ω
Figure 63.0 Determining 𝑅𝑇ℎ Figure 64.0 Determining 𝐸𝑇ℎ
𝐸𝑇ℎ :
𝑉𝐶𝐶 + 𝑉𝐸𝐸
𝐼=
𝑅1 + 𝑅2
20𝑉+20𝑉
=
8.2𝐾Ω+2.2 𝐾Ω
= 3.846153846 𝑚𝐴
𝐸𝑇ℎ = 𝐼𝑅2 − 𝑉𝐸𝐸
= (𝐼)(2.2𝐾Ω) − 20𝑉
= −11.53846154 𝑉
IM No. 08: ECE01-2S-2022-2023
The network can then be redrawn as shown in Figure 65.0, where the application of Kirchhoff’s
voltage law results in
−𝐸𝑇ℎ − 𝐼𝐵 𝑅𝑇ℎ − 𝑉𝐵𝐸 − 𝐼𝐸 𝑅𝐸 + 𝑉𝐸𝐸 = 0
Figure 65. Substituting the Thévenin equivalent circuit.
Substituting 𝐼𝐸 = (𝛽 + 1)𝐼𝐵 gives
𝑉𝐸𝐸 − 𝐸𝑇ℎ − 𝑉𝐵𝐸 − (𝛽 + 1)𝐼𝐵 𝑅𝐸 − 𝐼𝐵 𝑅𝑇ℎ = 0
and
𝑉𝐸𝐸 − 𝐸𝑇ℎ − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝑇ℎ + (𝛽 + 1)𝑅𝐸
20𝑉−(11.53846154)− 0.7𝑉
= (1.734615385)+(121)(1.8𝐾Ω)
= 35.35450866 µ𝐴
Solving for 𝐼𝐶
= (120)(𝐼𝐵 )
= 4.24254104𝑚𝐴
Solving for 𝑉𝐶
𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
= 20𝑉 − (𝐼𝐶 )(2.7𝐾Ω)
= 8.545139193V
Solving base voltage
𝑉𝐵 = −𝐸𝑇ℎ − 𝐼𝐵 𝑅𝑇ℎ
= −(11.53846154 𝑉) − (35.35450866µ𝐴)(1.734615385𝑘Ω)
= −𝟏𝟏. 𝟓𝟗𝟗𝟕𝟖𝟖𝟎𝟏 𝑽
IM No. 08: ECE01-2S-2022-2023
4.0 Design Operation
The design sequence is obviously sensitive to the components that are already specified and the
elements to be determined. If the transistor and supplies are specified, the design process will simply
determine the required resistors for a particular design.
Once the theoretical values of the resistors are determined, the nearest standard commercial values
(please see Table 2) are normally chosen and any variations due to not using the exact resistance values
are accepted as part of the design. This is certainly a valid approximation considering the tolerances
normally associated with resistive elements and the transistor parameters.
If resistive values are to be determined, one of the most powerful equations is simply Ohm’s law in the
following form:
𝑅𝑢𝑛𝑘𝑛𝑜𝑤𝑛 = 𝑉𝑅 /𝐼𝑅
Table 2. Standard Values of Commercially Available Resistors
IM No. 08: ECE01-2S-2022-2023
4.1 Design of a Current-Gain-Stabilized (Beta-Independent) Circuit
The circuit of Figure 66 provides stabilization both for leakage and current gain (beta) changes.
The four resistor values shown must be obtained for the specified operating point.
Engineering judgment in selecting a value of emitter voltage 𝑉𝐸 should be properly selected, for
our design we will use 1/10 of the 𝑉𝐶𝐶 .
Example # 13:
Determine the levels of 𝑅𝐶 , 𝑅𝐸 , 𝑅1 , and 𝑅2 for the network of Figure 66 for the operating point
indicated.
Figure 66. Current-gain-stabilized circuit for design considerations.
Solution:
1 1
𝑉𝐸 = 𝑉 = 10 (20𝑉) = 2 𝑉
10 𝐶𝐶
𝑉𝐸 𝑉𝐸 2𝑉
𝑅𝐸 = 𝐼𝐸
≅ 𝐼𝐶
= 10𝑚𝐴 = 200 Ω → 𝟐𝟎𝟎 Ω (𝑆𝑡𝑎𝑛𝑑𝑎𝑟𝑑 𝑉𝑎𝑙𝑢𝑒 𝑜𝑓 𝐶𝑜𝑚𝑚𝑒𝑟𝑐𝑖𝑎𝑙𝑙𝑦 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑙𝑒 𝑅𝑒𝑠𝑖𝑠𝑡𝑜𝑟)
𝑉𝑅𝑐 𝑉𝐶𝐶−𝑉𝐶𝐸 − 𝑉𝐸 (20𝑉−8𝑉−2𝑉)

𝑅𝐶 = = = = 1 𝐾Ω
𝐼𝐶 𝐼𝐶 10 𝑚𝐴
→ 𝟏 𝑲Ω (𝑆𝑡𝑎𝑛𝑑𝑎𝑟𝑑 𝑉𝑎𝑙𝑢𝑒 𝑜𝑓 𝐶𝑜𝑚𝑚𝑒𝑟𝑐𝑖𝑎𝑙𝑙𝑦 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑙𝑒 𝑅𝑒𝑠𝑖𝑠𝑡𝑜𝑟)
𝑉𝐵 = 𝑉𝐵𝐸 + 𝑉𝐸 = 0.7𝑉 + 2𝑉 = 2.7 𝑉
The equations for the calculation of the base resistors 𝑅1 and 𝑅2 will require a little thought. Using
the value of base voltage calculated above and the value of the supply voltage will provide one
equation—but there are two unknowns, 𝑅1 and 𝑅2 .
An additional equation can be obtained from an understanding of the operation of these two
resistors in providing the necessary base voltage. For the circuit to operate efficiently, it is
assumed that the current through 𝑅1 and 𝑅2 should be approximately equal to and much larger
than the base current (at least 10:1). This fact and the voltage-divider equation for the base
voltage provide the two relationships necessary to determine the base resistors. That is,
1
𝑅2 ≤ 𝛽𝑅𝐸
10
IM No. 08: ECE01-2S-2022-2023
And
𝑅2 𝑉𝐶𝐶
𝑉𝐵 =
𝑅1 + 𝑅2
Substitution yields
1
𝑅2 ≤ (80)(0.2𝐾Ω)
10
= 1.6 KΩ
𝑆𝑡𝑎𝑛𝑑𝑎𝑟𝑑 𝑉𝑎𝑙𝑢𝑒 𝑜𝑓 𝐶𝑜𝑚𝑚𝑒𝑟𝑐𝑖𝑎𝑙𝑙𝑦 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑙𝑒 𝑅𝑒𝑠𝑖𝑠𝑡𝑜𝑟)
(1.6𝐾Ω)(20𝑉)
𝑉𝐵 = 2.7𝑉 =
𝑅1 + 1.6 𝐾Ω
And
2.7 𝑅1 + 4.32 𝐾Ω = 32𝐾Ω
2.7 𝑅1 = 27.68𝐾Ω
𝑅1 = 10.25 𝐾Ω
Now use 10KΩ for 𝑅1 because it is the nearest value between 10KΩ and 11KΩ.
Final Answers:
𝑅1 = 10𝐾Ω
𝑅2 = 1.6 𝐾Ω
𝑅𝐸 = 200 Ω
𝑅𝐶 = 1 𝐾Ω
5.0 Transistor Switching Networks
The application of transistors is not limited solely to the amplification of signals. Through proper design,
transistors can be used as switches for computer and control applications. The network of Figure 67 can
be employed as an inverter in computer logic circuitry.
Note that the output voltage 𝑉𝐶 is opposite to that applied to the base or input terminal. In addition, note
the absence of a dc supply connected to the base circuit. The only dc source is connected to the collector
or output side, and for computer applications is typically equal to the magnitude of the “high” side of the
applied signal—in this case 5 V. The resistor 𝑅𝐵 will ensure that the full applied voltage of 5 V will not
appear across the base-to-emitter junction. It will also set the 𝐼𝐵 level for the “on” condition.
Figure 67.0Transistor inverter circuit
IM No. 08: ECE01-2S-2022-2023
Proper design for the inversion process requires that the operating point switch from cutoff to saturation
along the load line depicted in Figure 68.0. For our purposes we will assume that 𝐼𝐶 = 𝐼𝐶𝐸𝑂 ≅ 0 𝑚𝐴 when
𝐼𝐵 = 0 µ𝐴 (an excellent approximation in light of improving construction techniques). In addition, we will
assume that 𝑉𝐶𝐸 = 𝑉𝐶𝐸𝑠𝑎𝑡 ≅ 0𝑉 rather than the typical 0.1-V to 0.3-V level.
Figure 68. Transistor inverter load-line
When 𝑉𝐼 = 5𝑉, the transistor will be “on” and the design must ensure that the network is heavily saturated
by a level of 𝐼𝐵 greater than that associated with the 𝐼𝐵 curve appearing near the saturation level. In
Figure 68.0, this requires that 𝐼𝐵 > 50 µ𝐴. The saturation level for the collector current for the circuit of
Figure 68.0 is defined by
𝑰𝑪𝒔𝒂𝒕 = 𝑽𝑪𝑪 /𝑹𝑪
The level of 𝐼𝐵 in the active region just before saturation results can be approximated by the following
equation:
𝐼𝐵𝑚𝑎𝑥 ≅ 𝐼𝐶𝑠𝑎𝑡 /𝛽𝑑𝑐
For the saturation level we must therefore ensure that the following condition is satisfied:
𝑰𝑪𝒔𝒂𝒕 𝑰𝑪𝒔𝒂𝒕
𝑰𝑩 > 𝒐𝒓 𝑰𝑩 = ( 𝟏. 𝟓)
𝜷𝒅𝒄 𝜷𝒅𝒄
IM No. 08: ECE01-2S-2022-2023
Example # 14:
Determine 𝑅𝐵 and 𝑅𝐶 for the transistor inverter of Figure 69.0 if 𝑰𝑪𝒔𝒂𝒕 = 𝟏𝟎 𝒎𝑨.
Figure 69.0Transistor inverter circuit for Example # 14.
Solution:
At saturation,
𝑉𝐶𝐶
𝑅𝐶
And
𝑉𝐶𝐶 10𝑉
𝑅𝐶 = = = 𝟏 𝑲Ω
𝐼𝐶𝑠𝑎𝑡 10𝑚𝐴
Again, at saturation,
𝐼𝐶𝑠𝑎𝑡 10𝑚𝐴
𝐼𝐵 ≅
= = 40 µ𝐴
𝛽𝑑𝑐 250
Choosing 𝐼𝐵 = (1.5)(40µ𝐴) = 60µ𝐴 to ensure saturation and using
𝑉𝑖 − 0.7𝑉
𝐼𝐵 =
𝑅𝐵
We obtain
10𝑉 − 0.7𝑉
𝑅𝐵 = = 155 𝐾Ω
60µ𝐴
Choose 𝑅𝐵 = 150𝐾Ω (Standard Value of Commercially Available Resistor), then
10𝑉 − 0.7𝑉
𝐼𝐵 = = 62 µ𝐴
150 𝐾Ω
And
𝐼𝐶𝑠𝑎𝑡
𝐼𝐵 = 62 µ𝐴 > = 40 µ𝐴
𝛽𝑑𝑐
Therefore, use
𝑹𝑩 = 𝟏𝟓𝟎 𝑲Ω
𝑹𝑪 = 𝟏 𝑲Ω
There are transistors that are referred to as switching transistors due to the speed with which they can
switch from one voltage level to the other. In Figure 70 the periods of time defined as 𝑡𝑆 , 𝑡𝑑 , 𝑡𝑟 and 𝑡𝑓
are provided versus collector current.
IM No. 08: ECE01-2S-2022-2023
Their impact on the speed of response of the collector output is defined by the collector current response
of Figure 70. The total time required for the transistor to switch from the “off” to the “on” state is designated
as 𝑡𝑜𝑛 and is defined by
𝑡𝑜𝑛 = 𝑡𝑟 + 𝑡𝑑
Figure 70. Defining the time intervals of a pulse waveform.
with 𝑡𝑑 the delay time between the changing state of the input and the beginning of a response at the
output. The time element 𝑡𝑟 is the rise time from 10% to 90% of the final value. The total time required
for a transistor to switch from the “on” to the “off” state is referred to as 𝑡𝑜𝑓𝑓 and is defined by
𝑡𝑜𝑓𝑓 = 𝑡𝑠 + 𝑡𝑓
where 𝑡𝑠 is the storage time and 𝑡𝑓 the fall time from 90% to 10% of the initial value.
For the general-purpose transistor, the following are sample parameters;
𝑡𝑠 = 120 𝑛𝑠
𝑡𝑑 = 25 𝑛𝑠
𝑡𝑟 = 13 𝑛𝑠
𝑡𝑓 = 12 𝑛𝑠
𝑡𝑜𝑛 = 𝑡𝑟 + 𝑡𝑑 = 13𝑛𝑠 + 25 𝑛𝑠 = 𝟑𝟖𝒏𝒔
𝑡𝑜𝑓𝑓 = 𝑡𝑠 + 𝑡𝑓 = 120𝑛𝑠 + 12 𝑛𝑠 = 𝟏𝟑𝟐 𝒏𝒔
Comparing it to a switching transistor;
𝑡𝑜𝑛 = 12 𝑛𝑠
𝑡𝑜𝑓𝑓 = 18 𝑛𝑠
IM No. 08: ECE01-2S-2022-2023
VI. LEARNING ACTIVITIES
VII. EVALUATION (Note: Not to be included in the student’s copy of the IM)
VIII. ASSIGNMENT
IX. REFERENCES
A. Book/Printed Resources
Boylestad, R.L. & Nashelsky, L. (2013). Electronic devices and circuit theory (11th Ed.) Pearson Education
South Asia. Singapore
Floyd, T.L. (2005). Electronic devices: conventional current version (7th Ed.). Pearson Education South
Asia. Singapore.
Neamen, D.A. (2002). Electronics circuit analysis and design (2nd Ed.). Philippines: McGraw-Hill
International Edition.
B. e-Resources/ e-Book
Schultz, Mitchel E. (2016). Grob Basic Electronics. (12 Edition). McGraw-Hill

Education, 2 Penn Plaza,
New York, NY 10121. https://engineeringbookslibrary.com/grobs-basic-electronics-
12th-edition/
MIT OpenCourseWare ( 30 August 2019) Circuits and Electronics

http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-
circuits-and-electronics-spring-2007
Dube.D.C. ( 30 August 2019 ) Electronics I

https://freevideolectures.com/course/3062/electronics-i
ALLDATASHEET.COM (25 SEPTEMBER 2020) 1N4001 Datasheet (PDF) - Bytesonic Electronics

Co., Ltd.https://pdf1.alldatasheet.com/datasheet-
pdf/view/1169555/BYTESONIC/1N4001.html

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Republic of the Philippines

NUEVA VIZCAYA STATE UNIVERSITY

DEGREE Bachelor of Science in

I. UNIT TITLE/CHAPTER TITLE

II. LESSON TITLE

III. LESSON OVERVIEW

IV. DESIRED LEARNING OUTCOMES

At the end of the lesson, the students should be able to:

1. Explain the operation of Bipolar-Junction Transistor

Figure 1. Coinventors of the first transistor Figure 2. The first transistor.

1.1 Transistor Construction

1.2 Transistor Operation

Figure 4. Biasing a transistor: (a) forward-bias; (b) reverse-bias.

𝑰𝑪 = 𝑰𝑪𝒎𝒂𝒋𝒐𝒓𝒊𝒕𝒚 + 𝑰𝑪𝑶𝒎𝒊𝒏𝒐𝒓𝒊𝒕𝒚 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟐

For general-purpose transistors, 𝐼𝐶 is measured in milliamperes and 𝐼𝐶𝑂 is measured in

Figure 5. Majority and minority carrier flow of a pnp transistor

1.3 Transistor Characteristic Curve

To fully describe the behavior of a three-terminal device such as the common-base

Figure 6. Notation and symbols used with the common-base configuration:

Figure 7. Output or collector characteristics for a common-base transistor amplifier.

𝑽𝑩𝑬 ≅ 𝟎. 𝟕 𝑽 ( 𝒇𝒐𝒓 𝑺𝒊𝒍𝒊𝒄𝒐𝒏 𝒕𝒚𝒑𝒆 𝒔𝒆𝒎𝒊𝒄𝒐𝒏𝒅𝒖𝒄𝒕𝒐𝒓) 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟒

The ac alpha is formally called the common-base , short-circuit , amplification factor,

1.3.2 Common-Emitter Configuration

Figure 8. Notation and symbols used with the common-emitter configuration:

Figure 9.0 Characteristics of a silicon transistor in the common-emitter configuration:

Note that on the characteristics, the magnitude of 𝐼𝐵 is in microamperes, compared to

In the active region of a common-emitter amplifier, the base–emitter junction is

Figure 10.0 Circuit conditions related to 𝐼𝐶𝐸𝑂

For ac situations an ac beta is defined as follows:

In addition, recall that

1.3.3. Breakdown Region

As with the common-base configuration, there is a maximum collector-emitter voltage that

1.3.4 Limits of Operation

𝑷𝑪𝒎𝒂𝒙 = 𝑽𝑪𝑬 𝑰𝑪 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟔

𝑃𝐶𝑚𝑎𝑥 = 𝑉𝐶𝐸 𝐼𝐶 = 300 𝑚𝑊

𝑉𝐶𝐸 (50 𝑚𝐴) = 300 𝑚𝑊

Defining a second point on the power curve.

𝑉𝐶𝐸 (25𝑚𝐴) = 300 𝑚𝑊

as also indicated in Figure 12.

𝑉𝐶𝐸𝑠𝑎𝑡 ≤ 𝑉𝐶𝐸 ≤ 𝑉𝐶𝐸𝑚𝑎𝑥

𝑽𝑪𝑬 𝑰𝑪 ≤ 𝑷𝑪𝒎𝒂𝒙 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 17

𝑷𝑪𝒎𝒂𝒙 = 𝑽𝑪𝑩 𝑰𝑪 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 # 𝟏𝟖

2. Transistor Specification Sheet

Figure 13.0 Sample transistor specification sheet.

Figure 14. 𝛽 versus 𝐼𝐶

Figure 16. Capacitance Variation

Figure 17. Capacitance

2.1 Transistor Casing and Terminal Identification

Figure 18. Various types of general-purpose or switching transistors:

Figure 19. Transistor terminal identification.

Figure 20.0 Internal construction of a Fairchild transistor in a TO-92 package.

3.0 BJT Transistor Biasing Techniques

𝑽𝑩𝑬 ≅ 𝟎. 𝟕 𝑽 𝑬𝒒𝒖𝒂𝒕𝒊𝒐𝒏 #𝟏𝟗

3.1 Operating Point

1. The base–emitter junction must be forward-biased (p-region voltage more positive),

2. The base–collector junction must be reverse-biased (n-region more positive),with the

Figure 22. Fixed-biased circuit Figure 23. DC equivalent circuit

+𝑽𝑪𝑪 − 𝑰𝑩 𝑹𝑩 − 𝑽𝑩𝑬 = 𝟎 (𝒗𝒆𝒓𝒚 𝒊𝒎𝒑𝒐𝒓𝒕𝒂𝒏𝒕 𝒆𝒒𝒖𝒂𝒕𝒊𝒐𝒏)

Figure 24. Base-emitter loop

Figure 25. Collector-emitter loop

The magnitude of the collector current is related directly to 𝐼𝐵 through

𝑉𝐶𝐸 , 𝑉𝐶𝐵 , 𝑉𝐵𝐸 , 𝑒𝑡𝑐

And 𝑉𝐸 = 0𝑉, then