VLSI Technology

Unit II: VLSI Circuit Design Processes: Basic CMOS Technology,

n-well CMOS process, p-well CMOS VLSI Design process, Twin
tub process, Silicon on insulator; CMOS process enhancement-
Interconnect; circuit elements, Stick Diagrams, Design Rules and
Layouts, Lambda based design rules, Contact cuts, CMOS Lambda
and Micron based design rules, Layout Diagrams for logic gates,
Transistor structures, wires and vias, Scaling of MOS circuits-
Scaling models, scaling factors, scaling factors for device
parameters, Limitations of Scaling. [8L]
Dr Pushpa Giri
Asst. Prof., ECE dept.
 Basic MOS Transistors
Minimum line width
Transistor cross section
Charge inversion channel
Source connected to substrate
Enhancement vs Depletion mode
devices
pMOS are 2.5 time slower than nMOS
due to electron and hole mobilities
 Fabrication Technology
Silicon of extremely high purity
chemically purified then grown into large crystals
Wafers
crystals are sliced into wafers
wafer diameter is currently 150mm, 200mm, 300mm
wafer thickness <1mm
surface is polished to optical smoothness
Wafer is then ready for processing
Each wafer will yield many chips
chip die size varies from about 5mmx5mm to 15mmx15mm
A whole wafer is processed at a time
 Fabrication Technology
Different parts of each die will be made
P-type or N-type (small amount of other
atoms intentionally introduced - doping
-implant)
Interconnections are made with metal
Insulation used is typically SiO2. SiN is
also used. New materials being
investigated (low-k dielectrics)
 Fabrication Technology
nMOS Fabrication
CMOS Fabrication
p-well process
n-well process
twin-tub process
 Fabrication Technology
All the devices on the wafer are made at the same time
After the circuitry has been placed on the chip
the chip is overglassed (with a passivation layer) to protect it
only those areas which connect to the outside world will be left
uncovered (the pads)
The wafer finally passes to a test station
test probes send test signal patterns to the chip and monitor the
output of the chip
The yield of a process is the percentage of die which pass this
testing
The wafer is then scribed and separated up into the individual
chips. These are then packaged
Chips are ‘binned’ according to their performance
 CMOS Technology
First proposed in the 1960s. Was not seriously considered until
the severe limitations in power density and dissipation occurred
in NMOS circuits
Now the dominant technology in IC manufacturing
Employs both pMOS and nMOS transistors to form logic
elements
The advantage of CMOS is that its logic elements draw
significant current only during the transition from one state to
another and very little current between transitions - hence
power is conserved.
In the case of an inverter, in either logic state one of the
transistors is off. Since the transistors are in series, (~ no)
current flows.
See twin-well cross sections
 BiCMOS
A known deficiency of MOS technology is its limited load driving
capabilities (due to limited current sourcing and sinking abilities
of pMOS and nMOS transistors.
Bipolar transistors have
higher gain
better high frequency characteristics
BiCMOS gates can be an efficient way of speeding up VLSI
circuits
See table for comparison between CMOS and BiCMOS
CMOS fabrication process can be extended for BiCMOS
Example Applications
CMOS - Logic
BiCMOS - I/O and driver circuits
ECL - critical high speed parts of the system
Transistor Types
◼ Bipolar transistors
◼ npn or pnp silicon structure
◼ Small current into very thin base layer controls large currents
between emitter and collector
◼ Base currents limit integration density

◼ Metal Oxide Semiconductor Field Effect Transistors

◼ nMOS and pMOS MOSFETS
◼ Voltage applied to insulated gate controls current between
source and drain
◼ Low power allows very high integration
◼ First patent in the ’20s in USA and Germany
◼ Not widely used until the ’60s or ’70s
Technology Comparisons
 MOSFET as a variable resistor

The conductive channel between S and D can be viewed as resistor, which is

voltage dependent.
 MOS Transistors
Four terminal device: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors (body is also called the substrate)
SiO2 (oxide) is a “good” insulator (separates the gate from the body
Called metal–oxide–semiconductor (MOS) capacitor, even though
gate is mostly made of poly-crystalline silicon (polysilicon)

Source Gate Drain Source Gate Drain

Polysilicon Polysilicon
SiO 2 SiO 2

n+ n+ p+ p+
p bulk Si n bulk Si

NMOS PMOS
NMOS Fabrication
NMOS Fabrication
 Diffusion
• Introducing impurities into the selected region of a semiconductor in order to
alter its electronic properties is called Diffusion.

• Impurity atoms are introduced into the surface of a silicon wafer which
diffuses into the lattice because of their tendency to move from regions of high
to low concentration and takes place only at 900-1100ºC.

• Diffusion is used to form bases, emitter and resistors in bipolar device

technology.

• It is also used to form source drain regions, dope polysilicon in MOS device
technology.
 Diffusion Mechanism

Two types of Diffusion Mechanism are:

•Substitutional Diffusion
•Interstitial Diffusion
 Substitutional Diffusion
• At higher temperature many
atoms in the semiconductors
move out of their lattice site,
leaving vacancies into which
impurity atoms can move.

• Silicon atoms of parents crystals

are replaced by impurity atoms.
 Interstitial Diffusion
• In such type of Diffusion type, the
impurity atom does not replace the Silicon
atoms, but instead move into the
interstitial voids in the lattice.

• E.g. Gold, Copper, Nickel

• Since these impurities are smaller, hence

can not replace the host atom.
Ion Implantation
 Photo-Resist

In the Photo Lithographic process, a drop of light sensitive liquid is applied

to the silicon wafer is known as Photo-resist.

When a photo resist is exposed to UV light their solubility increases or

decreases.

According to this photoresist are classified as:

Positive Photo-resist
Negative Photo-resist
Photo-Resist
•Ion implantation is a low-temperature process by which ions of one
element are accelerated into a solid target, thereby changing the
physical, chemical, or electrical properties of the target.
•Ion implantation is used in semiconductor device fabrication and in
metal finishing, as well as in materials science research.
•The ions can alter the elemental composition of the target (if the
ions differ in composition from the target) if they stop and remain in
the target. Ion implantation also causes chemical and physical
changes when the ions impinge on the target at high energy.
•The crystal structure of the target can be damaged or even
destroyed by the energetic collision cascades, and ions of
sufficiently high energy (10s of MeV) can cause nuclear
transmutation.
In the diffusion process, the dopant atoms are introduced from the
gas phase of by using doped-oxide sources. The doping
concentration decreases monotonically from the surface, and the
in-depth distribution of the dopant is determined mainly by the
temperature and diffusion time.
 CMOS Fabrication
(a) Define n-well diffusion (mask #1) (c) LOCOS oxidation

(b) Define active regions (mask #2) (d) Polysilicon gate (mask #3)
 CMOS Fabrication
(e) n+ diffusion (mask #4) (g) Contact holes (mask #6)

(f) p+ diffusion (mask #5) (h) Metallization (mask #7)

Figure A.3 A typical n-well CMOS process flow.

CROSS-SECTIONAL DIAGRAM OF
AN N- AND P-MOSFET.
Cross-sectional diagram of a
BiCMOS process.
Duel-well Process or Twin-tub Process :
In Duel-well process both p-well and n-well for NMOS and PMOS
transistors respectively are formed on the same substrate. The main
advantage of this process is that the threshold voltage, body effect
parameter and the transconductance can be optimized separately. The
starting material for this process is p+ substrate with epitaxially grown
p-layer which is also called as epilayer. The process steps of twin-tub
process are shown in Figure below.
The process starts with a p-substrate surfaced with a lightly doped p-
epitaxial layer.
Step 1 : A thin layer of SiO2 is deposited which will serve as the pad
oxide.
Step 2 : A thicker sacrificial silicon nitride layer is deposited by
chemical vapour deposition.
Step 3 : A plasma etching process is used to create trenches used for insulating the devices.
Step 4 : The trenches are filled with SiO2 which is called as the field oxide.
Step 5 : To provide flat surface chemical mechanical planarization is performed and also
sacrificial nitride and pad oxide is removed.
Step 6 : The p-well mask is used to expose only the p-well areas, after this implant and
annealing sequence is applied to adjust the well doping. This is followed by second implant
step to adjust the threshold NMOS transistor.
Step 7 : The n-well mask is used to expose only the n-well areas, after this implant and
annealing sequence is applied to adjust the well doping. This is followed by a second
implant step to adjust the threshold voltage of PMOS transistor.
Step 8 : A thin layer of gate oxide and polysilicon is chemically deposited and patterned
with the help of polysilicon mask.
Step 9 : Ion implantation to dope the source and drain regions of the PMOS (p +) and
NMOS (n+) transistors is used this will also form n+ polysilicon gate and p+ polysilicon gate
for NMOS and PMOS transistors respectively.
Step 10 : Then the oxide or nitride spacers are formed by chemical vapour deposition
(CVD).
Step 11 : In this step contact or holes are etched, metal is deposited and patterned. After the
deposition of last metal layer final passivation or overglass is deposited for protection.
 Silicon On Insulator (SOI)

•In semiconductor manufacturing, silicon on insulator (SOI)

technology is fabrication of silicon semiconductor devices in a layered
silicon–insulator–silicon substrate, to reduce parasitic
capacitance within the device, thereby improving performance.
•SOI-based devices differ from conventional silicon-built devices in
that the silicon junction is above an electrical insulator, typically silicon
dioxide or sapphire (these types of devices are called silicon on
sapphire, or SOS).
•The choice of insulator depends largely on intended application, with
sapphire being used for high-performance radio frequency (RF) and
radiation-sensitive applications, and silicon dioxide for diminished
short-channel effects in other microelectronics devices.
•The insulating layer and topmost silicon layer also vary widely with
application
 Advantages of SOI

Lower parasitic capacitance due to isolation from the bulk silicon,

which improves power consumption at matched performance
Resistance to latchup due to complete isolation of the n- and p-well
structures
Higher performance at equivalent VDD. Can work at low VDD's[5]
Reduced temperature dependency due to no doping
Better yield due to high density, better wafer utilization
Reduced antenna issues
No body or well taps are needed
Lower leakage currents due to isolation thus higher power efficiency
Inherently radiation hardened (resistant to soft errors), reducing the
need for redundancy
CMOS Process Enhancements :

In the Analog, Digital or RF CMOS integrated circuits along with

transistors other elements such as interconnects, resistors,
capacitors are to be integrated on chip. In order to achieve this,
enhancements in CMOS process technology is required. The main
goals of adding CMOS enhancements are :

(1) To provide on chip capacitors for analog circuits.

(2) To provide on chip resistors.
(3) To provide routing of interconnects.
The enhancements in CMOS technology are :
(1) Multilevel metal layers.
(2) Multilevel poly layers.
Transistors :

To enhance the CMOS technology the bipolar transistors can be integrated on chip
in CMOS technology and this forms the BiCMOS technology. Here we will discuss
the processing requirements to make these devices on chip.
Figure below shows the cross-section of BiCMOS process in which NMOS and npn
transistor are fabricated on the same substrate. The starting material is p substrate on
which n type epitaxial layer is grown.
To form the NMOS transistor a p well is diffused in selected area. And n+ diffusions
form the source and drain contacts. The nepilar is diffused with the p+ diffusion
which forms the base for the npn transistor both the devices i.e. NMOS and npn
transistors are isolated by field oxide.
Interconnect :

The most important enhancement in CMOS processes is the additions

of signal and power supply routing layers. The advantage of this type
of routing is it improves power and clock distribution to the different
modules inside the chip. The interconnect layers involved in process
are :
(1) Metal interconnect
(2) Polysilicon interconnect
(3) Local interconnect.
The second layer of metal interconnect (Metal 2) is required for digital
Integrated circuits. The connection between first metal layer (Metal 1)
and second metal layer (Metal 2) is established with the help of via.
For high speed chips third metal layer (Metal 3) is also required.
Polysilicon Interconnect layers are used in ICs because of its high
melting points as compare to Al. But the major problem with
polysilicon interconnect is it has high sheet resistance because of this
for long distance interconnects this provides significant delay.
If silicide is used as a interconnect layer for connecting different cells then it is called as
local interconnect. The important advantage of local interconnect is it allows direct
connection between polysilicon and diffusion regions due to this metal contacts are
eliminated which reduces the chip area.
Circuit Elements :
Resistor :
In order to create the on chip resistors n-well or polysilicon materials can be used. The
resistance of a material is a function of the materials resistivity and the dimensions of
the material. Figure below shows the slab of the material. The resistance between the
two leads A and B is given as,
R = Rsheet
where Rsheet is the sheet resistance of material in W/square.
 CMOS Process Enhancement

• Multiple threshold voltage & oxide thickness – Low core

voltage for low power – High I/O voltage for interface
compatibility
• Silicon on Insulator : higher speed
• High-K gate dielectrics : thinner EOT
• Higher mobility : SiGe BJT, strained silicon
• Low-leakage transistor : finFET, gate-all-around (GAA) FET
• Plastic Transistors : flexible electronic paper
• High-voltage transistor : LCD driver, power electronics
• Copper interconnection : high conductivity
• Low-K dielectrics : low wire capacitance
•A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide
semiconductor) integrated circuit (IC) manufactured by stacking silicon
wafers or dies and interconnecting them vertically using, for
instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they
behave as a single device to achieve performance improvements at reduced
power and smaller footprint than conventional two dimensional processes.
•The 3D IC is one of several 3D integration schemes that exploit the z-
direction to achieve electrical performance benefits
in microelectronics and nanoelectronics.
•3D integrated circuits can be classified by their level of interconnect
hierarchy at the global (package), intermediate (bond pad) and local
(transistor) level.
•In general, 3D integration is a broad term that includes such technologies as
3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based
integration; 3D stacked ICs (3D-SICs); monolithic 3D ICs; 3D
heterogeneous integration; and 3D systems integration.