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BVHDL
BVHDL
By Benjamin Abramov
Course Topics
n Preface ………………………..…………….2
n Topic one ……………………………………32
n Topic two …………………….....................119
n Topic three…………………………………..206
n Topic four ……………………………………315
System Verilog
VHDL Verilog
AHDL
Abel
System C
•Layout (circuit) Level – Describes the layer in silicon including all necessary
physical data.
•RTL Level – A description of every Register in the design and the Logic in between.
Does not include timing and does not relate to technology.
VHDL Language
Simulator
Synthesizer
Fitter
Synthesizer: provides a “net list” – design block diagram from the highest
level (the whole design as one block) to the lowest level (single logic gates).
D=A+C; D<=A+C;
A=B*D; A<=B*D;
Correct Erroneous
statement statement
D=A+C;
Erroneous
D=E*F;
statement
Correct D<=A+C;
statement
D<=E*F;
All rights reserved to Abramov B. 24
HDL vs. Programming Language
C language example: VHDL language example:
D=A+C; Same
E=B*D; results
Or
E=B*D; D<=A+C;
D=A+C; E<=B*D;
Or
Different
E<=B*D;
results
D<=A+C;
All rights reserved to Abramov B. 25
HDL vs. Programming Language
Programming Language HDL
A basic identifier
• May only contain alphabetic letters ( ‘A’ to ‘Z’ and ‘a’ to ‘z’),
decimal digits ( ‘0’ to ‘9’ ) and the underline character (‘_’)
• Must start with an alphabetic character
• May not include two successive underline characters.
For example:
The meta-comments,
-- RTL_SYNTHESIS OFF
and
-- RTL_SYNTHESIS ON
X AND In 0
z MUX
GATE In 1
y
In2 4-1
In3
s1s0
All rights reserved to Abramov B. 35
Entity (cont)
Entity Parameters
Connections
Its ports and its generics are declared within the entity .
Syntax: optionally
entity entity_name is
generic(generic_list);
port(port_list);
end entity entity_name;
optionally
Sel(1:0)
Frequency
Divider Freq_Out
Freq_In
Rst
entity frequency_divider is
port (
rst : in bit;
sel : in bit_vector(1 downto 0);
freq_in : in bit;
freq_out : out bit
);
end entity frequency_divider;
in yes no
out no yes
A buffer mode port behaves in the similar way to an inout mode port,
in that the port can be both read and
assigned in the entity or block.
entity any_block is
port(
a : in bit;
b : in bit;
c : in bit;
d : in bit;
f : in bit;
e : out bit;
out_sig : buffer bit
);
end entity any_block;
Transmit out
A
logic
Return for
“reuse”
B
logic
Inout port
always should
be
controlled!!!
Real Time
Unconstrained Constrained
String
Severity_level
File_open_status
Boolean File_open_kind
Bit Character
Boolean
Bit
Integer
For example:
10=10;
“010”=”010”;
3 ns = 3 ns;
123=234;
‘a’/=’a’;
It is defined as
type bit is (‘0’,’1’);
my_bit<=‘1’;
The way the vector elements are indexed depends on the defined
range, and can be either ascending or descending .
Note! The first bit and last bit index numbers define the
number of bits in the vector (i.e. high - low + 1).
Little endian form is preferred!!!
All rights reserved to Abramov B. 56
Bit Vector (cont)
1 0 1 1 1 1 0 0
declaration
n range direction must be the same as the original
vector
n a single index is use to access a single bit e.g.
vec(4);
When integer range not declared, then by default the range is 32 bit.
port(
);
The operations that can be performed on values of integer types include the
familiar arithmetic operations.
natural >= 0;
positive >= 1;
Syntax:
architecture arc_entity_name of entity_name is
architecture declaration area
begin
concurrent statements
end architecture arc_entity_name;
üComponent
üType,
üSubtype,
üConstant,
üSignal,
üAttribute,
üFunction,
üProcedure,
üFile.
signal
signal
wire/bus ff/register
Examples :
Acceptable VHDL,
Y<= not ( (a and b) or c) after 10 ns;
but delay is ignored
rst_n<= ‘1’ , ‘0’ after 10 ns, ‘1’ after 50 ns; by synthesis tools
t
10 ns 50 ns
Syntax:
constant constant_name : type :=value;
-----------------------------------------------------------------------------------
my_sig <= all_ones; -- the constant used to set of default value
Structural VHDL:
üPossibility of creating hierarchical designs built from a set of
interconnected components.
Design refinement :
üSimplification of debugging process
üThe smaller, less complex circuit, the easier debugging process
Component representation:
üIn terms of other, smaller components (structural VHDL)
üLogic expressions
üUsing behavioural VHDL (mixed style coding)
All rights reserved to Abramov B. 91
Component (cont)
Structural VHDL:
üEntity implementation by specifying its composition from subsystems
üStructural architectural body – system composed only of interconnected subsystems
üElements of structural architecture:
1. Signal declaration
2. Component declaration - specification of external interface to component
in terms of generic constants and ports.
Component declaration uses the same name of component as entity of
the component module.
The same port declaration as module entity declared as component.
3. Component instantiation – specifies usage of module in design
For example :
u2: half_adder
port map ( a_xor_b, ci , s, co2);
u2: half_adder
port map ( a_xor_b, ci , s, open);
Process
Response
Checker
begin
u1: reg
port map (clk,rst,en,d,q);
clk <= not clk after 5 ns; -- defined clock frequency 100 MHz
rst <= ‘1’ ,’0’ after 50 ns;
en <= ‘1’ after 100 ns, ‘0’ after 120 ns, ‘1’ after 200 ns;
d <= x”01” after 20 ns, x”02” after 40 ns, x”03” after 60 ns, x”04”
after 80 ns, x”05” after 100 ns; -- and more
Entity declaration
Architecture
Configuration
Equivalent assignment is :
nibble(3)<=a;
nibble(2)<=b;
nibble(1)<=c;
nibble(0)<=d;
Aggregate
(a,b,c,d)<= bit_vector’(x”5”);
Equivalent assignment is :
a<=‘0’;
b<=‘1’;
c<=‘0’;
d<=‘1’;
Concatenation
The concatenation operator (denoted as &) composes two one-
dimensional arrays into one larger array of the same type.
üBe Careful!
b”0” -- 1 bit with value 0
o”0” -- 3 bits with value 0, same as B”000”
x”0” -- 4 bits with value 0, same as B”0000”
b”0” ¹ o”0” ¹ x”0”
sig1 (2)
a
Smart_box
All rights reserved to Abramov B. 128
Scalar types
Next scalar type (integer type is first) is floating point type .
floating_type_definition := range_constraint
For example:
if ( now < 100 ns) then
wait for (100 ns – now);
do something
end if;
CHARACTER_VAR: character;
...
CHARACTER_VAR <= ’A’;
Also, the characters '0' and '1' are members of both bit and
character types.
The string index always starts from 1 and should be ascending only!!!
idle
St_start St_2
St_1
Example :
type octal_digit is (‘0’,’1’,’2’,’3’,’4’,’5’,’6’,’7’);
signal curr_digit : octal_digit;
………….
…………
curr_digit <= ‘2’;
logic_level<=high;
temperature_level<=high;
logic_level<=level’(high);
library IEEE;
use IEEE.std_logic_1164.all;
----------------------------------
entity any_entity is
port(
a : out std_logic;
b : in std_logic;
c : in std_logic
);
end entity any_entity;
U U U U U U U U U U
U X X X X X X X X X
U X 0 X 0 0 0 0 X 0
U X X 1 1 1 1 1 X 1
U X 0 1 Z W L H X Z
U X 0 1 W W W W X W
U X 0 1 L W L W X L
U X 0 1 H W W H X H
U X X X X X X X X -
sl : std_logic;
sul : std_ulogic;
sl<=sul; --correct;
sul<=sl; --correct;
slv<=sulv; --wrong;
sulv<=slv; --wrong;
b<=a + 7; -- wrong
b<=unsigned(a) + 7; -- correct
•Designs that have only positive vectors will use the std_logic_unsigned package.
•Designs that have positive and negative vectors will use the std_logic_signed package.
empty_flag<=my_word=large_word’(others=>’0’);
The above logical operators operate on values of types bit, boolean, std_ulogic,
std_logic and also on one-dimensional arrays of these types.
For array operands, the operation is applied between corresponding elements of each
array, yielding an array of the same length as the result.
parity_bit <= ((din(7) xor din(6)) xor (din(5) xor din(4))) xor
((din(3) xor din(2)) xor (din(1) xor din(0)));
Z <= A + B + C + D;
Z <= ((A + B) + C) + D;
Z <= (A + B) + (C + D);
The equality operators (= and /=) can have operands of any type.
For composite types, two values are equal if all of their corresponding
elements are equal.
The remaining operators must have operands which are scalar types or
one-dimensional arrays of discrete types.
Be careful !!!
The multiplication and division operations are source
of hardware overhead.
The synthesis tools supports division operation only
for constants (one from two operands).
6 mod 4 -- 2
4 mod 6 -- 4
6 mod (-4) -- -2
(-6) mod 4 -- 2
The result of the rem operator has the sign of its first operand ,
while the result of the mod operators has the sign of the second operand.
6 rem 4 -- 2
4 rem 6 -- 4
6 rem (-4) -- 2
(-6) rem 4 -- -2
entity mul is
port(
a : in integer range ((2**8) – 1) downto 0;
b : in integer range ((2**8) – 1) downto 0;
res : out integer range ((2**16) – 1) downto 0
);
end entity mul;
* / mod rem
+ (sign) - (sign)
+ - &
Name Operation
0 a7 a6 a5 a4 a3 a2 a1 a0 1
0 b7 b6 b5 b4 b3 b2 b1 b0 cin
n Process…………………….207
n Wait statements …………..217
n Combinatorial Process……225
n Synchronous Process…….239
n Sequential Statements……255
n NULL Statements………….301
n Processes Guidelines …….303
n Behavioral Description…….307
n Wait statements ……..…….314
Asynchronous processes:
describe a combinatorial logic hardware
(muxes,decoders,encoders,arithmetic devices).
Synchronous processes:
describe a “clocked” logic
(FF,registers,shift registers,counters).
üSensitivity list and explicit wait statements may not be specified in the same process.
üThe process description style with sensitivity list is preferable for synthesis.
process
begin
warning_level<= ( curr_value=critical_value);
wait on curr_value,critical_value;
end process;
Syntax:
wait;
wait on signal_list;
wait until condition;
wait for n time_units;
Example :
wait for 50 ns;
statements.
process
begin
warning_level<= ( curr_value=critical_value);
wait on curr_value,critical_value;
end process;
Signal c is not included into sensitivity list, therefore the process does
not respond when c changes its value.
So what get is the following circuit:
process(a,b) is
begin
if(a=b) then
Sig<=c;
else
Sig<=d;
end if;
end process;
by library functions:
rising_edge(arg : std_logic) return boolean
falling_edge(arg : std_logic) return boolean
clk’event and clk=‘1’ returns TRUE at change to ‘1’ of any other value, even ‘H’
and rising_edge returns TRUE only at transition from ‘0’ to ‘1’.
entity dff is
port( clk: in std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity dff;
CLK
0
1
• Clocks are NEVER
generated within
any logic
en<= ‘0’ when state=‘0’ else ‘1’ when state=‘1’ else ‘0’;
p_reg: process ( en) is
begin
if rising_edge (en) then
q<= d;
end if;
end process p_reg;
All rights reserved to Abramov B. 253
FF coding rules
process (clk) is
……………………………………
if rising_edge (clk) and (en=’1’)
then
--Signal assignment
Resolution :
Synthesis tool should produce an error and not produce any results
Rules:
Ø Only one of the branches is executed.
Ø The order is important – the first true condition causes
Ø the sequential statements after it to be executed.
Ø The rest are ignored.
Ø The first condition gets the highest priority.
Example:
process(a,b) is
begin Created D-latch
if (a=’1’) then with enable (a).
x<=b;
end if;
end process;
process(a,b) is
begin
if (a=’1’) then
x<=b;
else
x<=’0’;
end if;
end process;
process(a,b) is
begin
x<=’0’; -- default assignment latches prevented
if (a=’1’) then
x<=b;
end if;
end process;
process(…,….) is
begin
some statement …………………………………..
………………
if (cond1) then
sig1<=a; sequential
………. sequential
Different
signals !!!!!!
end process;
process(…,….) is
process(…,….) is begin
begin some statement
some statement ………………
……………… if (cond2) then
Regular,
if (cond1) then sig1<=b;
sig1<=a; more understandable description
……….
……….
elsif(cond1) then
if(cond2) then sig1<=a;
sig1<=b; ……….
………. end process;
Same signal!!!!!!
end process;
case_statement_alternative ::=
when choices =>
sequence_of_statements
choices ::= choice { | choice }
choice ::=
simple_expression
| discrete_range
| element_simple_name
| others
Note :that all the choices must be distinct, that is, no value may
be duplicated.
case sel is
when 0 => y<=a;
when 1 to 4 => y<=b;
when 5|7|9 => y<=c;
when others => y<=d;
end case;
case sel is
when “000” => y<=a;
when “001” to “100” => y<=b; -- wrong! The sel is vector
when “101”|”110” => y<=c; -- correct
when others => y<=d;
end case;
case sel is
when 0 => y<=a;
when 1 to 4 => y<=b;
when 3|5|7|9=> y<=c; -- error, 3 included
-- into previous choice
when others => y<=d;
end case;
arbiter: process(addr,power_up,valid) is
begin
bios <='0';
flash <='0';
sram <='0';
eeprom <='0'; -- preventing transparent latches
-- with default assignment
signal a : integer ;
signal output_signal, x, y, z : bit_vector (3 downto 0) ;
....
output_signal <= x when (a=1) else y when (a=2) else
z when (a=3) else "0000" ;
....
output_signal <= x when (a=‘1’) else y when (b=‘1’) else x"0" ;
case controller_command is
when forward =>
engage_motor_forward;
when reverse =>
engage_motor_reverse;
when idle => null;
end case;
An incomplete IF statement:
process (a,b,c,d) is
begin
if (a = '1') then
out_sig <= c;
elsif (b ='1') then
out_sig <= d;
end if;
end process;
In the example above a latch is required to hold the value
when a = b = '0'
process(clk,n_reset) is
begin
if (n_reset = '0') then
last <= 0;
elsif rising_edge(clk) then
last <= curr;
curr <= curr + 1;
end if;
end process;
In the above example curr is not given a value during reset.
Therefore its value must be retained
process (clk,n_reset) is
begin
if (n_reset = '0') then
smp_b <= '0';
smp_a <= '0';
elsif rising_edge(clk) then
smp_a <= a;
end if;
end process;
smp_b <= b;
c <= smp_a XOR smp_b;
In the above example smp_b is assigned from 2 sources.
Process Process
Signals
Process Process
Events
entity mux is
port
(
a, b, c, d : in bit;
s0, s1 : in bit;
x : out bit
);
end entity mux;
n Generic ……………………….316
n FSM …………………………..336
Syntax:
entity e_name is
generic (generic list);
port(
port_list
);
end entity e_name name;
Instance_label : component_name
generic map ( generic_list => value)
port map ( port_association_list);
en en
Count 1 Count 2 Count 3
8 8 8
entity gcount is
generic ( size : natural:=8);
port( clk : in std_logic;
rst : in std_logic;
en : in boolean;
q : out std_logic_vector((size -1) downto 0);
tc : out boolean);
end entity gcount;
u2: gcount
generic map (size => 8)
port map (clk,rst,tc0,q(15 downto 8),tc1);
u3: gcount
generic map (size => 8)
port map (clk,rst,en2,q(23 downto 16),open);
Mealy FSM’s
Moore FSM’s
Medvedev FSM’s
input signals
Present Next state logic
clock state
register
reset Output logic
output signals
input signals
Present Next state logic
clock state
register
output signals
reset Output logic
input signals
Present Next state logic
clock state
register
output signals
reset
• one describing the combinatorial logic that calculates the next state
Inputs Outputs
Current State
wait_on_rd_start
start_of_read_cycle
='0'
Moore FSM Example
start_of_read_cycle='1' State Transition diagram may
be good way for starting of
read_fifo
wait_for_one_clk
FSM design
fifo_re<='1';
eop_int='1'
latch_descriptor eop_int='0'
send_data
descriptor_le<='1'
rows_counter_ld
send_sop
sop_int<='1';
num_of_rows_count_ld<='1';
Xi Zk
Inputs Combinational
Outputs
Logic for
Outputs and
Next State
q
q