ARM Instruction Set and

Architecture
Prof. Amlan Chakrabarti

ARM Instruction Set
• Data Processing Instructions: These instructions
perform arithmetic and logical operations on data
stored in registers. They include operations like
addition, subtraction, bitwise AND/OR/XOR, shifting,
and more.
• ARM data processing instructions can be broadly
categorized into three groups:
• Arithmetic Instructions: These instructions perform
basic arithmetic operations on data. Common
arithmetic instructions include:
• ADD: Adds two operands and stores the result.
• SUB: Subtracts one operand from another and stores
the result.
• MUL: Multiplies two operands and stores the result.
• DIV: Divides one operand by another and stores the
result.
• ADC: Adds two operands along with the carry flag and
stores the result.
• Logical Instructions: These instructions perform bitwise logica
operations on data. Common logical instructions include:
• AND: Performs a bitwise AND operation between two
operands.
• ORR: Performs a bitwise OR operation between two
operands.
• EOR: Performs a bitwise exclusive OR (XOR) operation
between two operands.
• BIC: Performs a bitwise AND operation with the complement
of the second operand.
• Shift and Rotate Instructions: These instructions shift or
rotate the bits of an operand. Common shift and rotate
instructions include:
• LSL: Logical Shift Left shifts the bits of an operand leftwards.
• LSR: Logical Shift Right shifts the bits of an operand
rightwards.
• ASR: Arithmetic Shift Right shifts the bits of an operand
rightwards with sign extension.
• ROR: Rotate Right rotates the bits of an operand rightwards.
ARM instructions often involve three operands: the destination register, the first
source operand, and the second source operand. The result of the operation is
stored in the destination register.
 • Post-indexed Offset: The offset is added to the base register
ARM Instruction Set after the memory access.
• LDR R8, [R9], #16 ; Load the value at memory location (R9) into R8 and
update R9 to (R9 + 16)
• STR R10, [R11], #-24 ; Store the value in R10 to memory location (R11)
• Load and Store Instructions: These instructions are and update R11 to (R11 - 24)
fundamental for manipulating data in memory and are
used extensively in programming for tasks like variable • Register Offset: The offset is specified using a register's value.
storage and data manipulation. ARM load and store • LDR R12, [R13, R14] ; Load the value at memory location (R13 + R14) into
instructions have various forms, including those that R12
deal with different data sizes and addressing modes. • STR R15, [R16, -R17] ; Store the value in R15 to memory location (R16 -
R17)
• The basic format of ARM load and store instructions is • LDR, LDM, STM with PC (Pseudo-Branches): These
as follows: instructions are used to load or store a value to/from memory,
• LDR/STR Rd, [Rn, +/-Offset]
and they can also be used for branching indirectly by
• Immediate Offset: The offset is a constant value added manipulating the program counter (PC). This is often used for
to the base register.
table lookups or jump tables.
• LDR R0, [R1, #4] ; Load the value at memory location (R1 + 4)
into R0 • LDR PC, [R5] ; Load the value at memory location pointed to by R5 into
• STR R2, [R3, #-8] ; Store the value in R2 to memory location (R3 PC, causing a branch
- 8) • "LDM" instruction in ARM assembly stands for "Load Multiple" and is
used to load multiple values from memory into a group of registers.
• Pre-indexed Offset: The offset is added to the base • ldm r4, {r0, r1, r2, r3} ;Here, it takes a base register (in this case,
register before the memory access. r4) and a register set (in this case, {r0, r1, r2, r3}). It loads
• LDR R4, [R5, #12]! ; Load the value at memory location (R5 + 12) consecutive words from the address in the base register into the
into R4 and update R5 to (R5 + 12) registers in the set.
• STR R6, [R7, #-20]! ; Store the value in R6 to memory location
(R7 - 20) and update R7 to (R7 - 20)
 • BCC, BCS, BNE, BEQ, etc. (Conditional Branches): These
ARM Instruction Set instructions perform conditional jumps based on the state of
the CPU's status flags. They allow for implementing
• Branch Instructions: ARM branch instructions are used to conditional statements.
control the flow of program execution by altering the sequence • BEQ label_name ; Branch to label_name if the Zero flag is set (previous
of instructions executed in a program. Branch instructions operation's result was zero)
allow programs to perform conditional jumps, unconditional • BNE label_name ; Branch to label_name if the Zero flag is not set
jumps, and subroutine calls, enabling the implementation of (previous operation's result was not zero)
loops, conditional statements, function calls, and more.
• CBZ, CBNZ (Compare and Branch on Zero/Non-Zero): These
• B (Branch): This instruction performs an unconditional jump to instructions are used to check the value of a register and
a specified target address. It is used for implementing loops
and unconditional jumps in the program flow. branch based on its state.
• B label_name ; Unconditionally jump to the label_name • CBZ R3, label_name ; Branch to label_name if the value in R3 is zero
• CBNZ R4, label_name ; Branch to label_name if the value in R4 is not
• BL (Branch with Link): This instruction is used for subroutine zero
calls. It saves the return address (address of the instruction
after the BL instruction) in the link register (LR or R14) before
branching to the specified target address.
• BL subroutine_name ; Call subroutine_name and save the return address
in LR

• BX (Branch and Exchange): This instruction is used to

switch between ARM and Thumb instruction sets. It
changes the processor mode based on the target address's
least significant bit.
• BX R2 ; Branch to the address stored in register R2 and switch instruction
sets if necessary
 ARM Instruction Set
• Control Instructions: ARM control instructions are a • WFI (Wait For Interrupt): This instruction puts the
subset of instructions that allow you to control the processor into a low-power state until an interrupt occurs.
behavior of the processor and the execution flow of a • WFI ; Put the processor to sleep until an interrupt occurs
program. These instructions include operations like
changing processor modes, modifying status flags,
enabling/disabling interrupts, and more. • MRS: Move to ARM register from system coprocessor
register
• MSR (Move to Status Register): This instruction is used • MRS R1, SCTLR ; writes the contents of the CP15 coprocessor
to set specific fields in the Current Program Status register SCTLR into R1
Register (CPSR), which holds information about the
processor's operating mode, condition flags, and other
control bits.
• MSR CPSR_c, #0x13 ; Switch to Supervisor mode and set the
Interrupt disable flag
• MRS (Move from Status Register): This instruction is
used to load fields from the CPSR into a general-purpose
register.
• MRS R0, CPSR ; Load the value of CPSR into R0
• SWI (Software Interrupt): This instruction is used to
request a supervisor mode operation (a system call or
software interrupt) to handle certain tasks, such as
interacting with the operating system.
• SWI 0x123456 ; Generate a software interrupt with the
specified value