Computer

Architecture
Prof. Dr. Talha Ali Khan

Ali Visifard
Sequential logic circuit
Flip-Flops
Flip-Flops
• A flip-flop is a binary cell capable of storing one bit of information
• Flip-flops are storage elements(Memory) employed in clocked
sequential circuits
• Clock Pulse can change the state in flip-flops. (The output state of flip-
flops, on the other hand, change depending on the value of the clock
input C)

Clock and Enable: A clock (better represented as clk) is a signal which is used to make the flipflop work
at its positive or negative edge (in exceptional case both edge). But, an enable is a signal which makes
the flipflop function as long as it is high (1). It can be made low (0) to make the flipflop stops its function
Flip-Flops
How many flip-flop types are there?
• Latch or Set-Reset (SR) flip-flop.
• JK flip-flop.
• D (Delay or Data) flip-flop.
• T (Toggle) flip-flop.
SR Flip-Flop

S R Q State
0 0 Last State No Change
0 1 0 Reset
1 0 1 Set
1 1 Not Applied (?) Forbidden
SR Flip-Flop
SR flip-flop is also known as an asynchronous SR Latch.
The latch responds to the edge signals.
It has three inputs ‘S’, ‘R’ and ‘C’ and one output ‘Q’
 Truth Table of NOR
x y (x+y)'
SR Flip-Flop 0
0
0
1
1
0
1 0 0
1 1 0

Truth Table of SR Flip-Flop S R Q Q'

S transitions from 0 to 1, 0 0 0 0
Output changes, Set
1 0 1 0 After S = 1, R = 0

0 0 1 0 Output is Latch to the last state

R transitions from 1 to 0, 1 0 1 0 Output is Latch to the last state

Output changes, Reset
0 1 0 1 After S = 0, R = 1

0 0 0 1
 SR Flip-Flop using NAND Gates
(Technically, RS Flip-Flop)
An SR flip flop can also be designed by cross coupling of two NAND gates, but the Hold and
Forbidden states are reversed. It is an active low input SR flip – flop and hence let us call
it RS Flip-Flop. The circuit of SR flip – flop using NAND gates is shown in below figure

R S Q State
1 1 Last State No Change
1 0 1 Set
0 1 0 Reset
0 0 Not Applied (?) Forbidden
 SR Flip-Flop using NAND Gates
The RS Flip-Flop using NAND gates can be converted to have a same truth table as a regular SR
Flip-Flip by inverting the inputs. Instead of using inverters, we can use NAND gates with
common input as shown in the following figure.
Clock Signal

A clock signal is a voltage signal that oscillates between 1 and 0 (high) at a fixed
frequency.

A clock signal is generated by a clock generator

It is used to coordinate different actions in digital circuits

Clocked SR Flip-Flop

• The Flip-Flop will retain its previous state when CP = 0

• The set state is reached when S = 1, R = 0 and CP = 1

• The reset state is achieved with S = 0, R =1 and CP = 1

Clocked SR Flip-Flop
The same can be achieved by using NOR gates. The circuit of clocked SR flip – flop using NOR gates
is shown below.
Clocked SR Flip-Flop
Two types of clocked SR flip – flops are possible: based on NAND and based on NOR. The circuit of
clocked SR flip – flop using NAND gates is shown below

Clock R S Q State
↓ or 0 X X Last State No Change
(Hold)
↑ or 1 0 0 Last State No Change
(Hold)
↑ or 1 0 1 1 Set
↑ or 1 1 0 0 Reset
↑ or 1 1 1 Not Applied (?) Forbidden
JK Flip-Flop
• JK flip-flop is a refined form of SR flip-flop
• Its output depends upon the input combination but only transitions
with the positive edge of clock signal c
 Truth Table of NAND

JK Flip-Flop x y
0 0
(xy)'
1
0 1 1
1 0 1
1 1 0
 x y (xy)'
D Flip-Flop 0
0
0
1
1
1
1 0 1
1 1 0
Data Flip-Flop

D Flip-flop is a modified clocked SR Flip-flop

To make sure both S and R are not ‘1’ at the same time, a NOT gate is added between them.

When clock is enabled (1)

When D = 0, the output Q goes to 0
When D = 1, the output Q goes to 1
T (Trigger) Flip-Flop
Trigger Flip-flop is made by connecting the inputs of a JK flip flop

When T = 0, the clock transition does not change the output Q.

When T = 1, the clock transition complements the output to Q’.
Excitation Tables

• Excitation tables specify the next state when the input and present state are known

• We wish to find the input conditions that cause a certain required transition

• Excitation table lists the required input combinations for a given change of state
Excitation Tables Examples Don’t Care State
What is Clock Pulse?
Sequential Circuits
• Depends on the times at which:
• storage elements observe their inputs, (Edge or Level)
• storage elements change their state
• Synchronous
• Behavior defined from knowledge of its signals at discrete instances of time
• Storage elements observe inputs and can change state only in relation to a timing signal
(clock pulses from a clock)
• Asynchronous
• Behavior defined from knowledge of inputs at any instance of time and the order in
continuous time in which inputs change
Behavior of Sequential Circuits
• The behavior of a sequential circuit depends upon
1. Inputs

2. Outputs

3. State of the Flip-Flops

• The outputs and the next state are a function of

1. Inputs

2. Present State
Flip Flop Input and output Equations
Consider the following circuit with one input variable x
Let's find the input equations of both flip flips

Let D1 be the input for first flip-flop and

D2 be the input for second flip-flop

D1 = Ax + Bx
D2 = A’x

The output equation is

y = Ax’ + Bx’
Basic Model of a Sequential Circuits
Example
Implement a JK flip-flop using a D-flip-flop and a multiplexer:
Example
Draw the output pulse for the following circuit:
Implementing filp flaps practically
• https://www.youtube.com/watch?v=KM0DdEaY5sY
• https://www.youtube.com/watch?v=peCh_859q7Q