Application Note

李彥德
AN028 – Apr 2014

Compensation Design for Peak Current-Mode Buck Converters

Abstract

Peak Current-Mode Controlled Buck Converters are currently very popular and widely adopted in consumer electronics and
computer peripheral power management. This application note presents a design procedure for feedback compensation of peak
current-mode buck converters, and also introduces the SIMPLIS tool for circuit simulations and the Mathcad mathematical
software for quantitative design, and finally provides the verified results by actual measurements.

Contents

1. Open-Loop Analysis of Peak Current Mode Buck Converters ...................................................................2

2. Compensation Design of Peak Current-Mode Buck Converters ................................................................7

3. The Closed-Loop Analysis of Peak Current-Mode Buck Converters ........................................................ 11

4. Conclusion ............................................................................................................................................. 13

5. References ............................................................................................................................................ 13

AN028 © 2014 Richtek Technology Corporation 1

Compensation Design for

Peak Current-Mode Buck Converters

1. Open-Loop Analysis of Peak Current Mode Buck Converters

Peak current-mode control is implemented by an inner current loop, composed of a current sensing circuit, Ri, with a slope
compensation (saw-tooth ramp) circuit. The sensed current ramp is summed with the saw-tooth ramp, and then is compared with
the output of the error amplifier, VC. And the result is used to control the ON-time, TON, of the MOSFET. The circuit diagram is
shown in Figure 1.

Figure 1. The circuit diagram of a peak current-mode buck converter

For peak current-mode, sub-harmonic oscillation may occur for duty cycle D > 0.5. In Figure 2, TON is the ON-time of the MOSFET,
and TS is the switching period; the dashed line is for the perturbed inductor current, and the solid line is for the ideal steady-state
inductor current. For D < 0.5, if a perturbation is initiated, it will be completely damped after a few cycles; that is, an unstable state
caused by the perturbation will gradually be stabilized. However, for D > 0.5, if a perturbation is initiated, it will continue to increase
for the next few cycles, which makes the system unstable. Slope compensation is therefore introduced to eliminate the risk of this
sub-harmonic oscillation so that the system can remain stable. Slope compensation is implemented by adding a saw-tooth ramp
of the same frequency as of the control circuit to the sensed inductor current ramp so that the system can still be stable at duty
cycle above 0.5.

Figure 2. The sensed inductor current ramps by Ri at duty cycles D < 0.5 and D > 0.5

AN028 © 2014 Richtek Technology Corporation 2

 Compensation Design for

Peak Current-Mode Buck Converters

The small-signal model of a peak current-mode buck converter [1] [2] will be introduced in this section. The Buck PWM Switch
Model, proposed by V. Vorperian [1] and the small-signal model for peak current-mode control, by Raymond B. Ridley [2] are
displayed in Figure 3. The equations derived according to the model will be applied in compensation design for peak current-
mode buck converters.

Figure 3. The Buck PWM switch model and the small-signal model for peak current-mode control

The open-loop transfer function of a peak current-mode buck converter is listed below [1], [2]:

Ro
Gd  s    Fp  s   Fh  s 
1
 (1)
Ri Ro  Ts
1  mc  1  D   0.5 
L1

Fp (s) in Equation (1), which dominates the open-loop low-frequency characteristics of this configuration, is shown below, as
Equation (2), which has a zero and a pole.

1  s  Cout  RC
Fp  s   (2)
s
1
ωp

Fh (s) in Equation (1) represents the high-frequency characteristics of this configuration, where the current-sense transformer Ri
plays an important role. Fh (s) is described below, as Equation (3) and it has two high-frequency poles.

Fh  s  
1
(3)
 
2
s s
1 
ωn  Qp ωn

AN028 © 2014 Richtek Technology Corporation 3

Compensation Design for

Peak Current-Mode Buck Converters

Figure 4 shows a low-frequency dominant pole (at a slope of -20dB / decade), and a high-frequency double pole (at a slope of -
40dB / decade decaying). The ESR zero in between is from the ESR of the output capacitor.

Figure 4. The Bode plot of the open-loop peak current-mode buck converter

The equations for compensation design will be analyzed step by step as follows:

To begin with, the equation of the exact low-frequency pole is presented below:

1 
 mc  1  D   0.5
1 Ts
fpole    (4)
2π  Cout  Ro L1  Cout 

Advanced computational tools will be needed to calculate for the above equation. However, the simplified equation, listed below,
is a close approximation, by which the pole can be found quickly.

1
fp_approx  (5)
2π  Ro  Cout

The equation below is for the output capacitor zero

1
fzero  (6)
2π  Rc  Cout

The following equation is for the double pole, positioned at the half of the switching frequency:

f
fn  s (7)
2

AN028 © 2014 Richtek Technology Corporation 4

 Compensation Design for

Peak Current-Mode Buck Converters

With the equations above, a design example will be offered to describe the important characteristics of a peak current-mode buck
converter.

Figure 5 displayed the circuit diagram and the corresponding circuit parameters of a buck converter. The input voltage is 12Vdc,
the rated output current 3A, the output voltage 3.3V, the operating frequency 340kHz, the inductance 10μH, the output capacitance
44μF, and its ESR 5mΩ.

S2 L1 RL Iout

Rc
Vin Ro Vout
S2
Cout

Figure 5. The circuit diagram and the corresponding circuit parameters of a peak current-mode buck converter.

Substitute the above parameters to Equation (4) to obtain a more accurate low-frequency first-order pole, which is located at
4.3kHz.

1 
 mc  1  D   0.5  4.322  10
1 Ts 3
fpole   
2π  Cout  Ro L1  Cout 

Se
Slope compensation factor, mc, is defined as mc  1 , where Se is the slope of the added compensation
Sn
saw-tooth ramp and Sn the slope of the sensed current ramp when the switch is on.

Se 
507  10-3 , T  1 , S  Vin  Vout  R , R  1  192m
s n i i
Ts fs L1 5.2

By Equation (5), the first-order pole, 3.3kHz, can be readily calculated as below.

1 3
fp_approx   3.288  10
2π  Ro  Cout

AN028 © 2014 Richtek Technology Corporation 5

Compensation Design for

Peak Current-Mode Buck Converters

Substitute the above parameters to Equation (6), and the exact location of the output capacitor ESR zero can be found as 723kHz.

1 3
fzero   723.432  10
2π  Rc  Cout

Then, by Equation (7), the high-frequency double pole is obtained as 170kHz.

f
fn  s  170  103
2

Gain Plot
Gain
With all the parameters above plugged in, a Bode plot can be drawn by Mathcad as below.
20 Plot6, it can be seen that a pole
In Figure
occurs at low frequency (3.28kHz), and ESR zero (723kHz) occurs at20an even higher frequency than the double pole, since the
smaller ESR is used.
Gain Plot Phase Plot
0
20 Gain Plot 0 225 Phase Plot
Gain / dB

20 Dominate pole 45 180

Gain / dB

 20 0 135
0  20
Phase / degrees

0 90
Phase / degrees

 45
Gain / dB

Two
Gain / dB

45
 40  20 20  90 0 poles
Double pole  40
 45
 135
 40  90
 60  40  180
3 4 5 6  60  135 Control-to-output
1 100 110ut ESR
10 Control-to-outp 110 zero
110 110 3 4 5 6
 60
1 225 180
10 110 110 ut110
Control-to-outp
100 110
3 4 5 6
3 4 5 6 110 110 110 110
1 10 100 110 110 110
Frequency / Hz 110 1 225 10 100
 60 Frequency
100 / Hz
3 4 5 6
3 4 5 6 1 10 110 110 110 110
1 10 110
100 / Hz
Frequency 110 110 110 Frequency / Hz

Frequency / Hz Frequency / Hz
Figure 6. The Bode plot of the open-loop peak current-mode buck converter in the design example

AN028 © 2014 Richtek Technology Corporation 6

 Compensation Design for

Peak Current-Mode Buck Converters

2. Compensation Design of Peak Current-Mode Buck Converters

The previous section has described the characteristics of a peak current-mode buck. In this section, how to compensate peak
current-mode buck converters for system stability will be investigated. In Figure 7, the open-loop gain is plotted in red; at low
frequencies, the DC gain is low. Low DC gain at low frequencies can cause steady-state errors, which can be seen in Figure 10,
for which the frequency responses of two different DC gains with the same bandwidth and phase margin are displayed in Figure
9. For f > fc, the gain curve is at the slope of -40dB / decade, and the phase curve is at the slope of -90°/ decade, which often
results in insufficient phase margin, illustrated in Figure 8, which furthermore causes system instability. The optimal closed-loop
gain is drawn in blue. Compared with the open-loop gain, the closed-loop gain manifests the following advantages: higher DC
gain at low frequency so that the steady-state errors can be minimized as in Figure 10, and for f > fc, the gain is at the slope of -
20dB / decade, and the phase -45°/ decade, as shown in Figure 7, thereby to improve the phase margin (P.M.).
Gain Plot
100 Gain Plot
40
─ Open-loop
80 ─ Closed-loop
60 20High
DC gain
Gain / dB

40
Gain / dB

0 -20dB/decade
20
 20
0
Wide BW
 20 40

 40 -40dB/decade
 60 Noise3 Attenuation
4 5 6
 60 1 10 100 110 110 110 110
3 4 5 6
1 10 100 110 110 110 110
Frequency / Hz
Figure 7. The comparison of the open-loop
Frequency and closed-loop Bode plots
/ Hz

dB Single Pole dB Double Pole

40 First Order 40 Second Order

20 -20 dB/ decade -40 dB/ decade

20

0 ω 0 ω
fp/10 fp 10fp 100fp fp/10 fp 10fp
degree degree
180° 180o
System could oscillate.
135o 135o

90o 90o

45o P.M. > 45° 45o

P.M. < 45°
ω 0° ω
fp/10 fp 10fp 100fp fp/10 fp 10fp

Figure 8. Single pole vs. double pole

AN028 © 2014 Richtek Technology Corporation 7

Compensation Design for

Peak Current-Mode Buck Converters

Effect of DC Gain
Higher
80
DC gain

Phase(Loop Gain) / degrees Gain(Loop Gain) /

40

Gain / dB
0 BW
-40 The same bandwidth and phase margin,
-80 but the different DC gains.

Phase / degree
160
120
80
40
P.M.
-0
1 2 4 10 20 40 100 200 400 1k 2k 4k 10k 20k 40k 100k 400k 1M
Frequency / Hz
freq / Hertz

Figure 9. Different DC gains with the same bandwidth and phase margin

In Figure 10, it can be seen load regulation is better with higher DC gain, and worse with lower DC gain.

3
2.5
I(S3-P) / A

Dynamic Load
Iout / A

2
31.5
1
2.50.5
3.6
I(S3-P) / A

23.5
Vout / V

Vout / V

3.4
1.53.3
3.2
3.1
1 0
Control-to-Output
0.2 0.4
Gain
Control-to-Output Gain 0.6 0.8 1
120120
0.5 time/mSecs Control-to-Output Gain Time / mSec 200uSecs/div

100 w/ Higher DC Gain

100100
3.345
3.34 80
80 80
Vout / V

Vout / V

3.335
60 60
/ dB/ dB

60
Gain / dB

3.33
40 40
3.325 40 w/ Lower DC Gain
GainGain

3.32 20 20 0.2
0 0.4 0.6 0.8 1
20
0
time/mSecs0 200uSecs/div
Figure010. The effect of DC gains on load regulation
 20 20 Control-to-Output
Control-to-Output
40
20
 40 Loop Gain
Control-to-Outp
Loop Gain ut
Based on the above analysis of the circuit60parameters
40 on Gain
Loop system performance, what is needed for a compensator is a zero to
 60
3 3 4 4 5 5 6 6
cancel the low-frequency pole of a peak current-mode buck
 601 1 10 10 100110
1101
100converter, as1 in
10 110
10Figure 10
110 111,1so
10 that the gain curve will be at the slope
3 4 5 6
of -20dB / decade at the crossover frequency,1 thereby
10 to 100 110
achieve 110 phase
a better 110 margin.
110 At high frequencies, a high-frequency
Frequency / Hz
Frequency / Hz
compensator pole can help filter out high-frequency noises.Frequency / Hz
Compendator Gain
Compendator Gain
100100 Compendator Gain
100
80 80
80
60 60 -20dB/decade
/ dB
Gain / dB

60
/ dB

40 40
Gain

40
Gain

20 20 Pole
20
0 0 Zero
0 Compendator
Compendator Gain
Gain
 20 20 Compensator Gain
3 4 5 6
 201 1 1310110
10 10 100100110
4
1 5
1
10110 1610
10 110
3 4 5 6
1 10 100 110 110 110 110
Frequency
Frequency / Hz
/ Hz
Frequency / Hz
Figure 11. A compensator offers a zero and a pole

AN028 © 2014 Richtek Technology Corporation 8

 Compensation Design for

Peak Current-Mode Buck Converters

Take a GM-Type compensator below as an example. Since a GM-Type compensator has one zero and two poles, it is quite
suitable to compensate peak current-mode buck converters. First pole can be obtained from Rgm and Ccomp, the other pole from
Rcomp and Cgm, and a zero from Rcomp and Ccomp.

Figure 12. A GM-Type compensator

Compensator Design Procedure :

Step 1 :

Set the crossover frequency (i.e. the bandwidth). In the example above, the operating frequency is 340kHz, and the bandwidth is
usually set as 1/10 of the operating frequency.

3
fc  34  10 (8)

Step 2 :

Set the zero of the compensator to cancel the pole of the peak current-mode buck topology.

3
fz  fpole  4.322  10 (9)

Step 3 :

The compensator pole is set to the lower frequency among the ESR zero and 1/2 of the operating frequency. In this example, 1/2
of the operating frequency is lower than the ESR zero, so set the compensator pole to 1/2 of the operating frequency.

1
fp   fs  170  103
2 (10)

Step 4 :

By Mathcad, the phase margin of 48° can be obtained by the following equation. Usually for stability, the phase margin should be
greater than 45°.

ΦM  Φfc  180  90  atan  

fc 180
fz

π
f
 atan  c
 fp
 180
  π  48.918
 (11)

AN028 © 2014 Richtek Technology Corporation 9

Compensation Design for

Peak Current-Mode Buck Converters

Step 5 :

From Equation (12), the DC gain, increased by the compensator at the crossover frequency, can be calculated as17.4dB.

GA  Gfc  20  log   VREF

Vout


 f 
 20  log  ceil  c    20  log  ceil z   17.371 (12)
 fp   
f
fc   
Step 6 :

The parameters of the compensator in this example, such as Rcomp = 5.9kΩ, Ccomp = 6.23nF, Cgm = 158pF, can all be obtained
as follows.

3 6 VFB
g m  1.25 10 -3 Rgm  200 10 Vc
gm  1.25  10 gm
VREF
Rgm  200  106 GA Rcomp
Rgm Cgm
GA 20 1 3
Rcomp  101   5.911
3 10 Ccomp
Rcomp  10 20   5.911
gm  10
gm
1 1 -9  9
Ccomp Ccomp  2  f  R  6.23
 6.23
 10 10 fP1
2π  fz  Rcomp
z comp
fP2
1 1  158.393  10-12 12
Cgm  C   158.393 10 fZ
gm fp 2
2π Rcomp
f R p comp

Step 7 :

Substitute all the above numbers into Equation (13), then enter the equation into Mathcad, and the Bode plot of the compensator
can be drawn, seen in Figure 13.

ωp1 
1 ωp1 -3
Rgm  Ccomp  127.741 10
2π

ωz 
1 ωz
 4.322  103
Rcomp  Ccomp 2π

ωp2 
1 ωp2 3
Rcomp  Cgm  170  10
2π

A  gm  Rgm 
20  1
s
ωz  Gain Plot 20
Gain Plot
 (13)
s   s  Gain Plot
1 ω   1 ω 
Compensator Bode Plots: Phase Plot
0  
p120 p2 
Gain Plot
Gain Plot 0 Phase Plot Phase Plot
225
120 180
Gain / dB

120 180 180

fP1
Gain / dB

0 100 135
 20 100
Phase / degrees

 20 90
Gain / dB

Phase / Degrees
Phase / Degrees

80 135
80 135
45
Gain / dB
Gain / dB

 20
 40 60
60 0
 40
 45
40 90
40 90
 90
 40 fP2
 60 20
20
 60  135
3
1 10 100 110 fZ1104 110
5
110
6
1
3
 180 100 Control-to-outp
10 110 110 1ut
4
10
5
110
6
0 45
0
 60 0.01 0.1 1 10
3 100
4 5
3
110 110
6
4 45 6
5
110 110 0.1 225100
1
3 4 5
10 3 100 4 110 5 110 6 110 110
6
100 110 1103 110 1410 110 110 110 1103
0.01 0.1 1
Frequency
10
100 / Hz
5 0.1 6 1 10
1 Frequency / Hz 4 5 6
1 10 110 Frequency 1/ 10
Hz 110 110 10 100
Frequency / Hz 110 110 110 110
Frequency / Hz Frequency / Hz
Figure/13.
Frequency Hz The Bode plot of the compensatorFrequency / Hz

AN028 © 2014 Richtek Technology Corporation 10

 Compensation Design for

Peak Current-Mode Buck Converters

3. The Closed-Loop Analysis of Peak Current-Mode Buck Converters

In this section, the SIMPLIS tool is used to simulate the peak current-mode buck converter and to substantiate the closed-loop
frequency response analysis. The SIMPLIS schematic is displayed in Figure 14. The closed loop of this current-mode buck
converter incorporates a current sensor, a compensator, and a slope compensation circuit.

H1 Comp Vout FB Comp Vac Vout

192.3m
IN OUT IN OUT IN OUT
IC=1
S1
GND R4 =OUT/IN =OUT/IN =OUT/IN

VCS
Vout

12 Current Sensor 10m 10u

V1 R2 L1
10m 10m
Dynamic Load
U2 R10 R1
IC=1
S2 R3S3
R5 1.1
22u 22u V6
C5 C1 AC 1m 0
GND
V5

Vac
U3 VCS
X1
OSC
POP U1
U4
RT N
Scomp
Compensator
R9
Clock Q S
GND
Comp 1.25m
G1
FB 26.1k
QN R
Slope Comp. OSC

Scomp GND 6.23n

POP
GND Ccomp
V3 V2 158.39p Rgm 0.925 R8
Rcomp Cgm 200Meg V4 10k
5.91k
Current-Mode
Modulator

Figure 14. The SIMPLIS simulation shematic (the closed-loop peak current-mode buck converter)

In Figure 15, the equation from the previous section (red line) is drawn by Mathcad, which is verified with the simulation result
(blue dots) of the SIMPLIS schematic in Figure 14. It demonstrates that the simulation result closely aligns with the analytical
result, derived by Mathcad, and the bandwidth and phase margin are 34kHz and 48.9°, respectively.

Gain Plot Phase Plot

100 135
80
90
60
Phase / Degrees

48.9°
Gain / dB

40
45
20
BW 34kHz P.M.
0 0

 20
Predicted Curve  45 Predicted Curve
 40 Simulated Curve Simulated Curve
 60  90
3 4 5 6
1 10 100 110 110 110 110 1 10 100 110
3
110
4
110
5
110
6

Frequency / Hz 170kHz Frequency / Hz

Figure 15. The comparison of theoretical analysis with the Matchcad and the SIMPLIS simulation

AN028 © 2014 Richtek Technology Corporation 11

Compensation Design for

Peak Current-Mode Buck Converters

Figure 16 has exhibited the benefits a compensator can provide. First, a compensator (black dashed line) enhances DC gain in
the low frequency range. The open loop response (red line), combined with the compensator response (black dashed line), makes
the closed loop response (blue line). Second, a compensator increases bandwidth, as in Figure 16, the crossover frequency in
blue is greater than that in red. Third, a compensator adds one high-frequency pole, which improves high-frequency noise
immunity (at high frequency, the blue line drops faster than the red line). Fourth, the zero of a compensator helps achieve a
sufficient phase margin.
Gain Plot Gain Plot
20 Gain Plot 20
Phase Plot
20
100
100 180
180225
080
80 135 180
0135
0 135
/ dB/ dB

/ dB/ dB
6060 9090

Phase / degrees
90
Gain / dB
Gain / dB

Gain / dB
 20
4040 4545
 20
Gain

Gain
45
 20
20
20 000
Gain

0 0
 40 Gain  40
45
 4545
Open-loop
Open-loop Open-loop
Open-loop
 20 40
 20 90
9090
Closed-loop
Closed-loop  135
Closed-loop
Closed-loop
 40
 40 Compensator
Compensator  135
135 Compensator
Compensator
 60  60 180 Control-to-outp ut
1 60 10
3 4 5 6
 60
 60 100 110 1310 1410 5110 6 
 180
180 110
3 4
110 4 1105
5 6
1106
3 1310 4 1410 5 1510 6 1610 1225 10 100
3 4 3 5 6
1 1 1 1010 10100
100100 10
1110 10 1110
1110 10 1110
10 11 1 101010 100 10
100 1110
100 110
10
13110 1
110
10
4110 1
110
10
5110
110
6
Frequency / Hz Frequency / Hz
Frequency
Frequency
Frequency / Hz/ Hz
/ Hz Frequency/ Hz
Frequency / Hz
Frequency / Hz
Figure 16. The comparison between the open loop and the closed loop

An actual measurement setup is presented in Figure 17, and an AC perturbation signal is injected into point R. The gain and
phase plot can be obtained by measuring the output (point A) versus the input (point R). From the right-hand plot of Figure 17,
the measured result (green line) shows good agreement with the analytical result (red line). Gain Plot
20
Gain Plot
80

60 0
40
Gain / dB

L Iout A 20
Gain / dB

S
 20
0

Vin v̂ o
Perturbation
Injection Circuit
 20 Gain Plot
C Ro
20  40  40
D Vout
Predicted Curve
Simulated Curve
M easured CurvePhase Plot
50Ω  60

0  80  225
60 Phase Plot
Slope Ri Sensed Current Ramp 3 4 3 5 4 1106 5 6
Compensation Sn v̂ i 135
100 1
180
11010 10
1100 110
110 110 110 110
R
Gain / dB

0 Frequency / Hz
R1 135
90 Frequency / Hz
 20
/ degrees

d Q R
Duty Cycle 90
Phase / Degrees

gm
Q’S Clock VREF
Vc
Rcomp Cgm R2 45 45
Rgm
Ccomp
0
 40
Phase

0
 45
 90 Predicted Curve
 45
Simulated Curve
 60  135
M easured Curve 3 4 5 6
1 90 180
10 110 110 ut110
Control-to-outp
100 110
3 4 5 6
110 110 110 110
 225
100

1 Frequency
10 /1Hz
100/ Hz
Frequency 10
3
110
4
110
5
110
6

Frequency / Hz
Figure 17. The experimental results verify the closed loop frequency response

AN028 © 2014 Richtek Technology Corporation 12

 Compensation Design for

Peak Current-Mode Buck Converters

4. Conclusion

 At low frequencies, an open-loop peak current-mode buck converter is still a single-pole system since the loop control is
realized by injecting current signals into the loop only.

 Its compensator is easy to design. The compensator zero is designed to cancel the dominant pole of a buck converter for
system stability.

 In order to assure sufficient phase margin, the design goal is that the gain curve is at the slope -20dB / decade, when passing
the crossover frequency.

5. References

[1] V. Vorperian, “Simplified analysis of PWM converters using model of PWM switch part I:
continuous conduction mode,” IEEE Trans. on Power Electronics, vol. 26, no. 3, pp. 490-496,
May 1990.
[2] Raymond B. Ridley, A New Small-signal Model for Current-mode Control, Ph.D. Dissertation,
Virginia Polytechnic Institute and State University, Nov. 1990.

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AN028 © 2014 Richtek Technology Corporation 13