Design Techniques and Architectural Solutions For Low-Power

Design Techniques and Architectural Solutions for Low-Power
Analog Circuits Targeting IoT Applications

Current References, Voltage References, and Analog Temperature Sensors for IoT Applications
Thesis submitted in partial fulfillment

of the requirements for the degree of
Master of Science
in
Electronics and Communication Engineering
Abhishek Pullela
20171211
venkata.abhishek@research.iiit.ac.in
International Institute of Information Technology, Hyderabad

(Deemed to be University)
Hyderabad - 500 032, INDIA
May 2022
Copyright © Abhishek Pullela, 2022
All Rights Reserved
International Institute of Information Technology
Hyderabad, India
CERTIFICATE
It is certified that the work contained in this thesis, titled “Design Techniques and Architectural Solutions
for Low-Power Analog Circuits Targeting IoT Applications” by Abhishek Pullela, has been carried out
under my supervision and is not submitted elsewhere for a degree.
Date Advisor: Dr. Zia Abbas

To My Beloved Father and Mother
Acknowledgments
I would like to express my profound gratitude to my research advisor Dr. Zia Abbas for his invaluable
support and guidance throughout my dual-degree tenure. I am deeply indebted to him for not only his
role in making me a leading researcher, but also in encouraging and providing opportunities for me
to teach students and brainstorm sessions with leading industry and academia people. Apart from his
guidance in research, he also taught me how to be patient and considerate with people, deal with failures
and constructive criticism, thereby making me a better person apart from great researcher, teacher and
speaker.
My initial interest in analog circuit design was largely because of the online resources available,
which are highly intuitive and easy to understand. These resources include lectures by Dr. Shanthi Pavan
(IIT-Madras), Dr. Nagendra Krishnapura (IIT-Madras), Dr. Behzad Razavi (University of California,
LA), Dr. Ali Hajimiri (CalTech), Prof. K Radhakrishna Rao (IIT-Madras), Dr. Qadeer Ahmad Khan (IIT-
Madras), Dr. Saurabh Saxena (IIT-Madras), Prof. S Aniruddhan (IIT-Madras), Prof. Anant Agarwal
(MIT), Dr. Richard Feynman (CalTech), and Prof. Walter Lewin (MIT). I owe infinite gratitude to
these people for making the field of physics and analog very interesting. I would like to thank Mr.
Sunil Maddikatla (CEO, Bluesemi Research and Development), Texas Instruments and Dr. Inhee Lee
(University of Pittsburgh) for providing me an opportunity to design state-of-the-art analog blocks. I
am also grateful to many other pioneers in the field of analog, namely, Dr. David Blaauw (University
of Michigan), Dr. Behzad Razavi (University of California, LA), Dr. Patrick Mercier (University of
California, SD), Dr. Massimo Aliotto (National University of Singapore), and Prof. Yannis Tsividis
(Columbia University), for their ground-breaking research in their respective sub-domains of analog.
My university life is incomplete without my colleagues, mentors, seniors and my friends. I would like
to express my special thanks to my brothers, seniors and mentors, Ashfakh Ali and Arpan Jain for count-
less discussions over a wide range of topics. I also appreciate the momentary availability of other col-
leagues, seniors and mentors, namely, Koushik De, Deepthi Amuru, Balaji, Mounika, Hema, Shirisha,
Sai Kiran Lade, Praneeth, Adithya Banthi, Naveen Dasari, Gaurav Dixit, Surya Poondla, Ashutosh,
Samriddhi, Ashish Papreja and juniors, namely, Arnab, Abhinav Vajrala, Anubhab Banerjee, Bharad-
waj, Chetan Mittal, Dheekshith Akula, Sahishnavi, Sampath, and Jaishnav for short discussions. I am
grateful to my friends Sushanth, Jashwanth Kumar, Pavan Kalyan, Aravinda Sai, Surendra, Vijay Vard-
han, Sriteja, Yashwanth Balivada, Anudeep, Abhishek Reddy, Abhiram Kadiyala, Chinni Charan, Di-
nesh Bijjam, Haneeth, Haranadh, Dara Sai Charan, Pavan Pathakota, Shreya, Rupa, Pranathi B, Pranathi
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vi
Y, Sireesha, Meghana, Vishwath, Vivek, Surya Bheemala, Soorya Veeravalli, Snehith, Sai Jashwanth,
Raviteja, Srikar, Mayukha, Rasagna, Harshitha, Varsha, A S D Harsha, Jaydev, Krishna Mahesh Teja,
Kalyan Pajjuri, Pindi Pranay, Ruthwik Reddy, Sasi Kiran, Sunil, Ayush Singhania, Chaitanya Kharyal,
Siddharth Gaur, Nishanth Arcot, Nishanth Sharma, Supreeth, Bhanudeep, Harsha Vardhan, Pruthvi Tri-
nadh, Sampreeth, Aditya Vihari, Abhiram Ambadipudi, Sai Prakash, Sandy Sharma, Preetham Reddy,
Raghavendra Kaushik, S N Pranav, Sri Charan Raj, Sukruth, Sri Sai, Abhishek Srivastav, Tarun Tej,
Rishik, Shivam, Shrikar, Vishal, Siddhartha and Teja for their invaluable friendship, help and priceless
memories.
Lastly, I would like to thank my parents for educating me with their wisdom and forging my person-
ality with integrity, perseverance, and gratefulness. I am also thankful to my sister, grandparents and
other family members for their love and support.
Abstract
Decades of relentless efforts in manufacturing integrated circuits and reducing their cost has enabled
the design of almost every system which was thought impossible before. As the semiconductor industry
thrives to expand its market every year, a question keeps popping up every decade or so asking what
kind of technology will continue expanding the market. Previous technological waves include laptops
and smart-phones, however they are tending towards market saturation. The convergence of social and
technological trends suggest that there is a growing need to efficiently utilize the resources on earth and
create smart environments. This is possible when every object on earth, ex. cars, drones, buildings,
etc. share the appropriate data and provide suggestions for optimal usage of the resources and things
around us. It is evident that these objects need to be connected to the Internet to perform such tasks and
hence the term Internet-of-Things (IoT) rose into picture in 1999 [1]. The IoT is still in its technological
infancy and the growing IoT wave will soon dominate the semi-conductor market in the upcoming years.
The IoT application space is vast and includes wide variety of applications like biomedical, surveil-
lance, environmental, etc. These applications have stringent power and area constraints and hence the
circuits present in the IoT nodes need to comply with these conditions. The average power consump-
tion is a critical factor in deciding the system’s lifetime, which can be reduced to an extent by applying
the concept of duty-cycling. However, blocks which are always-on, are required for the application of
duty-cycling and they contribute to the sleep mode power consumption inevitably. Hence, they need to
be designed with extremely low power consumption. Apart from the power constraint, they are desired
to be process and supply invariant, and have low area. This thesis discusses the design of always-on
blocks that include voltage reference, current reference and analog temperature sensor.
Chapter 1 introduces the concept and evolution of IoT over the past few years, its applications, chal-
lenges that will be faced by it to dominate the semi-conductor market and its future. After understanding
IoT applications, we introduce voltage reference, current reference, analog temperature sensor and ex-
plain their functionalities in Chapter 2. With this background, we move on to the design of the always-on
blocks in the successive chapters.
The references and sensor incorporate thin-oxide devices to achieve pico-watt power consumption
while consuming low-area. Resistor based architectures are eliminated as their values should be in the
order of GΩs to achieve pico-watt power consumption. Other resistor-less architectures suffer from the
drawbacks as mentioned in the corresponding chapters. The thin-oxide devices or gate-leakage tran-
sistors serve as effective replacements for resistors. However, they have non-linear characteristics with
vii
viii
various parameters and hence cannot be directly visualized as resistors. The temperature dependencies
of gate-leakage current in inversion and accumulation region are studied in Chapter 3 and then exploited
in the designs of always-on blocks.
Chapter 4 discusses the design of pico-watt current reference using gate-leakage transistors in inver-
sion region while the design in Chapter 5 operates them in accumulation region to achieve a bandgap
reference. It is beneficial if the functionality of both voltage and current reference are included in a single
circuit. Chapter 6 deals with such an architecture by again exploting accumulation-mode gate-leakage
current characteristics. Chapter 7 deals with the design of a pico-watt process-invariant temperature
sensor using gate-leakage transistors in accumulation region.
PVT variations are inevitable in any kind of circuit and most of the circuits try to achieve PVT in-
variant designs. Design techniques for achieving process-invariant voltage reference and temperature
sensor are discussed in Chapters 5 and 7. Current references cannot usually be made process-invariant
and hence process-invariant current reference is out of scope of this thesis. Techniques for achieving
high supply noise invariance are discussed in Chapters 8 and 9. Chapter 8 proposes high PSRR volt-
age reference, current reference and temperature sensor in a single circuit while Chapter 9 deals with
achieving high PSRR in composite-pair based temperature sensors. Chapter 10 finally concludes the
thesis and mentions the scope of improvement for this work.
Contents
Chapter Page
1 Introduction to IoT Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Emergence of IoT from technological trends . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Applications of IoT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 IoT design space requirements and challenges . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Growth and future of IoT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Always-on Analog Blocks and their Functionality . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 PTAT voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2 CTAT voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Current Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Analog Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Analysis of Gate-Leakage Current in Inversion and Accumulation Regions . . . . . . . . . . 15

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Components of Gate-Tunneling Current . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 Gate-to-Substrate Current (Igb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2 Gate-to-Channel Current (Igc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.3 Gate-to-Source/Drain Currents (Igs /Igd ) . . . . . . . . . . . . . . . . . . . . 19
4 A 60pA Inversion-Mode Gate-Leakage Based Current Reference for IoT and IoT2 Applications 22
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Proposed Current Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.1 Design of the Current Reference . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.2 Proposed Trimming Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference for IoT Applications 33

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 Design and Analysis of the Proposed Bandgap Reference . . . . . . . . . . . . . . . . 34
5.2.1 Derivation for accumulation-mode gate-leakage current . . . . . . . . . . . . . 34
5.2.2 Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ix
x CONTENTS
5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6 Accumulation-mode gate-leakage based Voltage/Current References . . . . . . . . . . . . . 44

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2 First Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2.1 Circuit level architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2.3 Summary of the first configuration . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3 Second Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.1 4T voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.2 4T Vref with trimming and current reference . . . . . . . . . . . . . . . . . . 55
6.3.3 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.4 Summary of the second configuration . . . . . . . . . . . . . . . . . . . . . . 56
7 A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems . . . . . 61

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2 Design and Analysis of the Temperature Sensor . . . . . . . . . . . . . . . . . . . . . 62
7.2.1 Core of the temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.2 Beta-multiplier using gate-leakage . . . . . . . . . . . . . . . . . . . . . . . . 64
7.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8 Highly Supply Invariant Current/Voltage Reference and Temperature sensor . . . . . . . . . . 72

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.2 The Asymmetric Op-Amp Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.3 Proposed Current and Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.4 Proposed Voltage Reference/Temperature Sensor . . . . . . . . . . . . . . . . . . . . 74
8.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9 A 180o Phase Shift Biasing Based High PSRR Technique in Low-Power Temperature Sensors 82
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.2.1 Composite Transistor Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.2.2 Conventional Supply Rejection Technique . . . . . . . . . . . . . . . . . . . . 86
9.2.3 Proposed Supply Rejection Technique . . . . . . . . . . . . . . . . . . . . . . 88
9.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

List of Figures
Figure Page
1.1 Applications of IoT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Life-time vs avg power consumption of various batteries [1] . . . . . . . . . . . . . . 4
1.3 Concept of duty cycling [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Harvester size vs avg power consumption . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 The S-curve [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 Technology waves and annual sales of products over time [1] . . . . . . . . . . . . . . 7
2.1 Widely used method for Vref generation . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 (a) ∆VEB based approach (b) ∆VGS based approach . . . . . . . . . . . . . . . . . . 10
2.3 VP T AT generating architectures based on ∆VBE approach . . . . . . . . . . . . . . . 11
2.4 VP T AT generating architectures based on ∆VGS approach . . . . . . . . . . . . . . . 12
2.5 (a)VEB based approach (b)VGS based approach . . . . . . . . . . . . . . . . . . . . . 13
3.1 (a) Components of gate-tunneling currents (b) Connections of gate-leakage transistors . 16
4.1 Proposed current reference including W/L of transistors . . . . . . . . . . . . . . . . . 23

4.2 Proposed Trimming Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Post trim simulation of current Iref w.r.t temperature in different process corners . . . 29
4.4 Line sensitivity of Iref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 Post trim power consumption w.r.t temperature in different process corners . . . . . . . 30
4.6 Start-up time for Iref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.7 Load sensitivity of Iref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8 Montecarlo simulation of temperature coefficient . . . . . . . . . . . . . . . . . . . . 31
4.9 Layout of proposed current reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 Proposed Bandgap Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.2 % error between simulated and estimated results vs |Vsg | . . . . . . . . . . . . . . . . 36
5.3 Proposed bandgap reference in different corners . . . . . . . . . . . . . . . . . . . . . 39
5.4 Monte-Carlo simulation result for the BGR value w.r.t temperature . . . . . . . . . . . 39
5.5 Monte-Carlo simulation result for the TC of BGR . . . . . . . . . . . . . . . . . . . . 40
5.6 PSRR of the BGR at different process corners . . . . . . . . . . . . . . . . . . . . . . 40
5.7 Line sensitivity of the BGR in different process corners . . . . . . . . . . . . . . . . . 41
5.8 Current consumption of the circuit vs temperature . . . . . . . . . . . . . . . . . . . . 41
5.9 Current consumption of the circuit vs supply voltage . . . . . . . . . . . . . . . . . . 42
5.10 Start-up time of the BGR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
xi
xii LIST OF FIGURES
5.11 Layout of the BGR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1 Proposed current reference in chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.2 Proposed Voltage/Current Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3 Variation of Vbias voltage with process and temperature . . . . . . . . . . . . . . . . . 47
6.4 The ratio K10 /K0 w.r.t temperature in different corners . . . . . . . . . . . . . . . . . 48
6.5 Proposed voltage reference with trimming circuitry . . . . . . . . . . . . . . . . . . . 48
6.6 Post-trim results for Vref w.r.t temperature in diff. corners . . . . . . . . . . . . . . . 50
6.7 Post-trim results for line-sensitivity of Vref in diff. corners . . . . . . . . . . . . . . . 50
6.8 PSRR of Vref at different supply voltages . . . . . . . . . . . . . . . . . . . . . . . . 50
6.9 Monte-Carlo Simulation result for TC of Vref . . . . . . . . . . . . . . . . . . . . . . 51
6.10 Post-trim results for Iref w.r.t temperature in diff. corners . . . . . . . . . . . . . . . . 51
6.11 Post-trim results for line-sensitivity of Iref in diff. corners . . . . . . . . . . . . . . . 52
6.12 Monte-Carlo Simulation result for TC of Iref . . . . . . . . . . . . . . . . . . . . . . 52
6.13 Layout of the proposed Vref /Iref . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.14 Proposed Voltage/Current Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.15 ± 3σ variation of (a) Vref 1 and (b) Vref (MC) . . . . . . . . . . . . . . . . . . . . . . 57
6.16 (a) MC result for Vref TC (b) Vref post-trim results . . . . . . . . . . . . . . . . . . . 57
6.17 (a) MC result for Iref TC (b) Iref post-trim results . . . . . . . . . . . . . . . . . . . 58
6.18 Line-sensitivity of (a) Vref (b) Iref . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.19 (a) PSRR of Vref (b) Current w.r.t supply . . . . . . . . . . . . . . . . . . . . . . . . 59
6.20 Power consumption vs temp for (a) 4T Vref (b) total circuit . . . . . . . . . . . . . . . 59
6.21 Start-up time for (a) Vref (b) Iref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.22 Layout of the proposed voltage/current reference . . . . . . . . . . . . . . . . . . . . 60
7.1 Proposed Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.2 Conventional beta-multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.3 R2/R1 w.r.t temperature across different corners . . . . . . . . . . . . . . . . . . . . . 67
7.4 Monte-Carlo simulation for R2/R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.5 VP T AT 2 in different process corners . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.6 % non-linearity in different process corners . . . . . . . . . . . . . . . . . . . . . . . 69
7.7 MC simulation for slope of VP T AT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.8 Line sensitivity of VP T AT 2 in diff. corners . . . . . . . . . . . . . . . . . . . . . . . . 70
7.9 Start-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.10 Layout of the proposed temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . 71
8.1 Comparison between conventional and asymmetric op-amps . . . . . . . . . . . . . . 74

8.2 Proposed Voltage Reference, Current Reference and Temperature Sensor based on asym-
metric op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.3 100nA and 10uA current references in different process corners . . . . . . . . . . . . 77
8.4 Arch - 1 and Arch - 2 voltage references in different process corners . . . . . . . . . . 78
8.5 Temperature Sensor and its % non-linearity in different process corners . . . . . . . . 79
8.6 PSNRs of voltage references and temp sensor . . . . . . . . . . . . . . . . . . . . . . 80
8.7 Line Sensitivities of the five blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8.8 Monte-Carlo Simulation for the five blocks . . . . . . . . . . . . . . . . . . . . . . . 81
LIST OF FIGURES xiii
9.1 (a) Basic Composite Pair, (b) Self biased Composite Pair with supply insensitive current,
(c) Composite Pair biased with PMOS current source, (d) Composite Pair biased with
NMOS current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.2 Block diagram of conventional biasing technique (Vbias ) to generate supply independent
PTAT voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.3 VP T AT PSRR (composite pair) vs Vbias PSRR (0o phase SIVB) . . . . . . . . . . . . . 88
9.4 Block diagram of conventional biasing technique (Vbias ) to generate supply independent
PTAT voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.5 VP T AT PSRR (composite pair) vs Vbias PSRR (180o phase SIVB) . . . . . . . . . . . 90
9.6 Schematic of Temperature sensor using proposed biasing technique to achieve very high
supply insensitivity without additional circuitry . . . . . . . . . . . . . . . . . . . . . 92
9.7 Magnitude and Phase of PSRR for 180o SIVB circuit . . . . . . . . . . . . . . . . . . 93
9.8 PSRR of Temp. Sensor (VP T AT ) at extreme process corners . . . . . . . . . . . . . . 93
9.9 Line regulation of VP T AT for various temperature values . . . . . . . . . . . . . . . . 94
9.10 VP T AT with temperature for various process corners . . . . . . . . . . . . . . . . . . 94
9.11 Slope of VP T AT with temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.12 Monte Carlo Simulation of PSRR of Temperature Sensor and Layout . . . . . . . . . . 95
List of Tables
Table Page
3.1 Gate-Leakage Current Based Model Parameters . . . . . . . . . . . . . . . . . . . . . 20

3.2 Components of Gate-Leakage Current in Accumulation and Inversion Regions . . . . . 21
4.1 Comparison With State-of-the-Art Architectures . . . . . . . . . . . . . . . . . . . . . 32
5.1 Comparison with State-of-the-Art Architectures . . . . . . . . . . . . . . . . . . . . . 43
6.1 Comparison With State-of-the-Art Architectures . . . . . . . . . . . . . . . . . . . . . 53

6.2 Comparison with State-of-the-Art Architectures . . . . . . . . . . . . . . . . . . . . . 60
7.1 COMPARISON WITH STATE-OF-THE-ART ARCHITECTURES . . . . . . . . . . 71
9.1 PSRR comparison of different references/temperature sensor . . . . . . . . . . . . . . 91
xiv
Chapter 1
Introduction to IoT Applications
1.1 Emergence of IoT from technological trends
The year 1947 marks an important day in the history of electronics as the first transistor was ever
invented. Since then, there have been vertiginous improvements in the design of electronic systems,
which is enabled by relentless cost reduction per transistor, increased energy efficiency and aggressive
transistor scaling leading to giga scale integration. Enormous amount of tasks which were thought im-
possible decades ago are being done today within fraction of seconds only because of the exponential
improvement in computational capabilities of the systems integrated in a small volume. These phenom-
enal improvements have been predicted by some historical laws like Moore’s law, Bell’s law, Koomey’s
law, Gene’s law and Metcalfe’s law.
Moore’s law states that the number of transistors on a microchip doubles every 18 months, though
the cost of the computers is halved.
Bell’s law states that there will be 10-100x reduction in the computers’ size every decade, inventing
new class of computers with smaller form factor.
Koomey’s and Gene’s law state that the energy efficiency of a system doubles every 18 months.
These laws still hold true today and can be verified from the statistics of computer and electronic
systems evolution. There has been 40x decrement per decade in the cost per transistor [1]. Energy
efficiency systems has also increased drastically, with 10x-100x improvement per decade for computa-
tion and processing [1], 20x-30x for wireless communication based circuits and 20x in sensor interfaces
[1]. There has also been a inexorable system shrinkage by atleast 100x/decade, thereby approaching
sub-centimeter systems (with cost and power being the same). The convergence of these trends promise
the possibility of very small and yet highly capable systems, which are inexpensive and consume very
low power.
1
At the same time, various megatrends like accelerated urbanization and increasing human popula-
tion demand efficient usage of resources and smart environments. Pervasive sensing and sensemaking
are being required in many applications to relieve the humans from tedious and routine tasks. The
convergence of the social and technological trends created a new class of computing, known as the
‘Internet-of-Things’ (IoT). The concept of IoT first appeared in 1999 [1] and was defined in several
different ways since then. We can realize IoT as the ability of the computing devices to connect to
Internet. These devices may include smartphones, cars, smart buildings, etc. IoT can evidently bring
unprecedented benefits to the society, however it is currently in its technological infancy and need to
overcome stringent problems as mentioned in section 1.3.
1.2 Applications of IoT

The IoT encompasses a wide variety of applications such as:
• Agriculture
• Automotive
• Public transport
• Consumer electronics
• Energy management
• Health care
• Industrial processes
• Retail
• Smart infrastructures which includes smart homes, smart buildings, smart cities, smart homes,
etc.
• Nature preservation
Fig.1.1 summarizes the role of IoT in each application.
1.3 IoT design space requirements and challenges

The applications of IoT mentioned in the previous section impose stringent requirements on the
systems used in the IoT nodes. These include:
1) IoT nodes should have extremely low form factor to make their deployment non-intrusive. Their
volume can be as high as hundreds of mm3 or as low as few cubic millimeters (called Internet-of-tiny-
things (IoT2 ) [2]).
2
Figure 1.1: Applications of IoT
3
2) In few applications, the IoT nodes are purely powered by batteries. Due to the low form factor
requirement, the batteries used are also miniaturized. These miniaturized batteries have very low energy
storage volume and hence the average power of the IoT node must be small enough to achieve the
desired lifetime. Fig.1.2 shows the plot of lifetime vs avg. power consumption for various batteries.
Figure 1.2: Life-time vs avg power consumption of various batteries [1]
It can be seen from Fig.1.2 that smart-watch and button cell batteries have larger volumes and hence
their lifetime is more than a decade if the average power consumption is in the order of hundreds of nWs.
On the other hand, thin film batteries have very low form factor and energy storage volume, hence their
lifetime is orders of magnitude less. The lifetime of a battery can be given by tlif etime = Ebattery /Pavg ,
for a given energy capacity Ebattery . To achieve the desired life-time and functionality of the IoT nodes,
the average power consumption of the system must be very low. Note that battery replacement is not a
viable solution since the IoT nodes will be present at inaccessible locations where battery replacement
is either not possible or incurs large costs. It should also be noted that Fig.1.2 assumes optimistic
conditions such as negligible battery self-leakage and ageing.
4
Such stringent power budgets can be met only if the tasks performed by the IoT nodes, such as sens-
ing or processing, are infrequent. The system can be shutdown when its idle to reduce the average power
consumption. This method is called duty cycling and is depicted in Fig.1.3. An always-on sub-system,
generally a wake-up timer, is required to periodically wake-up the system and perform the active tasks.
Although duty-cycling can reduce the average power consumption, the always-on blocks contribute to
the sleep mode power consumption and hence are deciding factors for the system’s lifetime. It is imper-
ative to design the always-on blocks with near zero power consumption.
Figure 1.3: Concept of duty cycling [1]
3) If Pavg is still larger, then energy harvesters are required as they can indefinitely sustain the
power required by the system. Larger Pavg mandates a larger size energy harvester and Fig.1.4 shows
the harvester size required for a desired Pavg . While photo-voltaic or thermo-electric harvesters can
sustain power in the order of micro-watts, GSM radio-frequency energy harvesting can sustain only
10s to 100s of nWs. Energy harvesters are also used in conjunction with batteries to deliver the peak
power whenever it’s greater than Pavg . Although energy harvesters can deliver larger power while being
compact, they usually output voltages which can be as low as 0.3V. The systems incorporated in the IoT
nodes need to work for lower supply voltages if they are powered by energy harvesters.
1.4 Growth and future of IoT

To understand how the IoT market is developing, we refer to the S-curve [1] as shown in Fig.1.5.
It is usually a Gaussian-distributed curve, depicting the cumulative distribution of the time of adoption
of an invention. The distance from the mean µ in steps of standard deviation σ define the adoption
stages. It can be seen from the figure that innovators are very early adopters, accounting for 2.5% of
the total adopters and IoT is currently at this very early stage of adoption. On the other hand, the smart-
phone market is currently in the “laggards" phase, where the adoption tends to saturate and market
reaches maturity stage. After growing impetuously for 10 years, the smart-phone market wave is getting
saturated and the IoT wave, which has started to grow, is expected to dominate the semiconductor
5
Figure 1.4: Harvester size vs avg power consumption
market. Various technology waves that expanded the semiconductor market size by 11 billion dollars
per year steadily in the previous decades have been depicted in Fig.1.6. There will be a push towards the
next phase of adoption of IoT in the coming years. This push is inevitable considering the fundamental
challenges posed by the accelerated urbanization and increased human population, which demand more
efficient management of resources (like space, time, electricity, water, etc). The social mega-trends
converge to foster the growth of IoT and there will certainly be a boost in the semi-conductor market. In
the end, IoT nodes will be deployed in every application mentioned in the previous section and improve
the quality of peoples’ life on earth.
6
Figure 1.5: The S-curve [1]
Figure 1.6: Technology waves and annual sales of products over time [1]
7
Chapter 2
Always-on Analog Blocks and their Functionality
2.1 Introduction
The Internet-of-Things (IoT) application space is rapidly developing with many applications (as
mentioned in the previous chapter) garnering much interest in recent times. As discussed earlier, the
IoT nodes are typically operated under restricted energy storage capacity of micro-fabricated batteries
(ex. 1µAh [3]) due to their miniaturized size. This renders the power consumption a critical factor
in deciding the system’s lifetime. Due to the limited energy capacity of the battery, the system is
aggressively duty-cycled to reduce the average power consumption. However, the benefits of duty-
cycling can be retained only when the power consumption of the always-on blocks is greatly reduced.
This thesis discusses the design of three important always-on analog blocks, namely voltage reference,
current reference and analog temperature sensor. Prior to understanding how to design these blocks, it
is imperative to know about the functionality of them. The upcoming sections in this chapter discuss the
functionality of the aforementioned blocks.
2.2 Voltage Reference
A voltage reference is a block that outputs a voltage resilient to process, supply and temperature
(PVT) variations. Requirement of such a voltage is inevitable in any analog system such as ADCs/DACs,
voltage regulators, flash memories etc. However, no electrical quantity in any semi-conductor technol-
ogy is directly independent of PVT variations. A voltage reference is obtained by either adding two
quantities with opposite temperature dependencies or subtracting two quantities having similar tem-
perature dependencies. The analysis of such operations becomes easier if linear dependencies are
considered. Quantities increasing/decreasing w.r.t temperature are termed Proportional-to-absolute-
temperature (PTAT)/Complementary-to-absolute-temperature (CTAT) respectively. A voltage reference
8
can be expressed in terms of PTAT and CTAT quantities as:

 K V + K2 VCT AT
 1 P T AT


Vref = K1 VP T AT 1 − K2 VP T AT 2 (2.1)


K1 V − K2 V

CT AT 1 CT AT 2
VP T AT and VCT AT can be obtained directly as voltages or in terms of PTAT and CTAT currents as
VP T AT = IP T AT RCW T and VCT AT = ICT AT RCW T . Here, RCW T is a resistance whose value is
constant w.r.t temperature (CWT). The most commonly used approach to design a voltage reference is
by adding PTAT and CTAT voltages in appropriate amounts as shown in Fig.2.1. The state-of-the-art
consists of various approaches to generate PTAT and CTAT voltages. Of all those approaches, only two
of them, each for PTAT and CTAT voltage generation, are presented in this chapter.
Figure 2.1: Widely used method for Vref generation
2.2.1 PTAT voltage generation

The two approaches to generate a PTAT voltage are shown in Fig.2.2(a) and Fig.2.2(b). Fig.2.2(a)
shows the concept of PTAT generation using ∆VEB approach. The difference between base-emitter
voltages of BJTs is a PTAT voltage, derived as shown below:

I1 I2
VP T AT 1 = VEB1 − VEB2 = VT ln − VT ln (2.2)
IS1 IS2
Considering Q2 to be N1 parallel units of Q1, IS2 = N1 IS1 . If I1 = M1 I2 , eq.2.2 can be simplified as:
VP T AT 1 = VT ln(M1 ∗ N1 ) (2.3)
9
Vdd Vdd Vdd Vdd
I1 I2 I1 I2
V EB V
GS
Q1 Q2 M1 M2
(a) (b)
Figure 2.2: (a) ∆VEB based approach (b) ∆VGS based approach
The expression remains unaltered if PNP transistors are replaced with NPN transistors. In other
words, ∆VEB = ∆VBE . In most of the circuits, M1 is set to 1 to reduce power consumption. The slope
of the VP T AT 1 equals (k/q)ln(N1 ), and it can be observed that the voltage VP T AT 1 is independent of
process variations. The difference between base-emitter voltages can be generated using different cir-
cuits. Conventional architectures generating VP T AT using ∆VBE /∆VEB approach are shown in Fig.2.3.
Fig.2.2(b) shows the second approach to generate VP T AT , where the PNP diodes are replaced by
NMOS diodes and the difference is taken between gate-source voltages (VGS ) of the NMOS transistors.
Considering sub-threshold region of operation and currents I1 and I2 flowing through M1 and M2
respectively, the expression for VP T AT 2 can be given by:

I1 I2
VP T AT 2 = VGS1 − VGS2 = (Vth1 − Vth2 ) + ηVT ln − ηVT ln (2.4)
I01 I02
where η is the sub-threshold slope factor and I0 = µn Cox (W/L)(η − 1)VT 2 . Considering similar type
of transistors Vth1 = Vth2 . Eq.2.4 can be further simplified as:
VP T AT 2 = ηVT ln(M2 ∗ N2 ) (2.5)
where M2 = I1 /I2 and N2 = (W/L)2 /(W/L)1 . The term η is slightly susceptible to process variations
and hence VP T AT 2 deviates slightly due to process variations. Similar to the previous case, M2 is set to
1 in most of the circuits. Fig. 2.4 shows the most commonly used circuits for VP T AT generation using
∆VGS approach. The current in the circuit diagram of Fig.2.4(a) can be given by VP T AT /R1 . If R1 is
a resistance invariant to temperature, then the nature of current is a PTAT, which is widely used to bias
ring oscillators and OTAs. Note that eq.2.5 is accurate only when Vth1 = Vth2 . However, the circuits
shown in Fig.2.4 can show a mismatch in the threshold voltages if body-effect is present for one of the
10
Vdd Vdd
M1 M2 M1 M2
I1 I2 I1 I2
M3 M4
+
V V
R1 BE R1 BE
Q1 Q2 Q1 Q2
xN x1 xN
x1
(a) (b)
Figure 2.3: VP T AT generating architectures based on ∆VBE approach
transistors. In Fig.2.4(a), transistor M1 doesn’t have body effect and has a nominal threshold voltage
(VT H0 ), but M2 suffers from body effect and, consequently, its threshold voltage is given by:
p p
VT H2 = VT H0 + γ 2φF + VSB − 2φF (2.6)
where φF is the fermi potential and γ is the body factor coefficient. VSB is equal to VR . Considering
√
VR << 2φF , we can use binomial expansion to approximate the term 2φF + VSB as :
p p VP T AT 2
2φF + VP T AT = 2φF + √ (2.7)
2 2φF
From equations 2.6 and 2.7, we can simplify eq.2.4 as :

(W/L)2
η(kT /q)ln (W/L)1
VP T AT 2 = (2.8)
1+ √γ
2 2φF
From [4], we have :

γ
1+ √ =η (2.9)
2 2φF
Hence, the final expression for VP T AT 2 becomes :
VP T AT 2 = VT ln(N2 ) (2.10)
The presence of body-effect eliminates the term η, thereby making VP T AT 2 a process-invariant voltage.
Similar expression can be obtained for the circuit in Fig.2.4(b) considering body-effect for M1.
11
Vdd
Vdd Vdd
M3 M4
I
I VGS
I1 I2
V M1 M2
M1 X
I2
M1 M2 I1 I2
M2 VGS M3 M4
R1 VGS
(a) (b) (c)
Figure 2.4: VP T AT generating architectures based on ∆VGS approach
2.2.2 CTAT voltage generation

Similar to PTAT generation, CTAT voltages are also obtained using PNP and MOS diodes as shown
in Fig.2.5(a) and Fig.2.5(b) respectively. Instead of taking the difference between two base-emitter or
gate-source voltages, we take the voltage VEB or VGS , which behave as a CTAT voltage as explained
below.
The expression for VEB in a PNP transistor can be given by [5]:

kT IE
VEB = VG0 + ln (2.11)
q Tγ
where VG0 is the band gap of silicon extrapolated to absolute zero, E is a constant that depends on
fundamental quantities and processing variables (but not temperature) and γ = 2.5. The derivative of
VEB can be expressed as:

∂VEB VEB − VG0 γk kT 1 ∂I0
= − + · · (2.12)
∂T T q q I0 ∂T
If I is constant w.r.t temperature, the slope of VEB equals -2mV/o C, indicating that VEB is a CTAT
voltage. The slope of VEB decreases slightly if I is a PTAT current of linear nature and significantly if I
is a sub-threshold current with exponential nature. However, in all the cases, the nature of VEB remains
a CTAT.
Considering sub-threshold region of operation, VGS of NMOS transistor is given by :

I
VGS = Vth + ηVT ln (2.13)
µn Cox (η − 1)VT 2
12
Figure 2.5: (a)VEB based approach (b)VGS based approach
Vth is a CTAT voltage given by Vth0 − k1 T , where Vth0 is the nominal threshold voltage and k1 is
the slope of the threshold voltage. The term µn is proportional to T −3/2 , thereby making the term
ηVT ln(I/(µn Cox (η−1)VT 2 )) proportional to ln(T −1/2 ), considering I to be constant w.r.t temperature.
It is a weak function of temperature and the dominant CTAT nature of Vth makes VGS also a CTAT
voltage. It can also be deduced that even a PTAT current cannot turn the nature of the term VGS , thereby
preserving its CTAT nature.
In most cases, the PTAT voltage generated by the aforementioned approaches has a small slope,
while the CTAT voltages have larger slope. Hence, the PTAT voltage is amplified to compensate the
slope of CTAT and then directly cascaded to the CTAT voltage to obtain the voltage reference.
2.3 Current Reference
A current reference is a block that outputs a current resilient to PVT variations. Similar to voltage
reference, a current reference is also an essential block in many analog systems such as oscillators,
13
sensors, etc. A current reference can be expressed in terms of PTAT and CTAT quantities as:



 K1 IP T AT + K2 ICT AT


K1 IP T AT 1 − K2 IP T AT 2






1 CT AT 1 − K2 ICT AT 2

K I
Iref = (2.14)


 VP T AT /RP T AT


VCT AT /RCT AT






VCW T /RCW T

The circuit shown in Fig.2.4(a) can itself be realized as a current reference. The current in the circuit
(considering I1 = I2 ) can be given by VP T AT /R1 . If R1 is a resistor having a PTAT nature, then the
current Iref can be given by:
VP T AT V0 (1 + αT )
Iref = = (2.15)
RP T AT R0 (1 + βT )
where α and β are temperature coefficients of the voltage VP T AT and the resistor RP T AT respectively.
If α = β, the a temperature compensated current reference is obtained.
2.4 Analog Temperature Sensor

Fully-integrated temperature sensors are integral parts of any IoT system typically used for real time
thermal management. They usually employ a linear PTAT or a CTAT voltage generating circuit, which
is converted to a digital code using Analog-to-Digital Converter (ADC). In most cases, PTAT voltages
are used and we refer these PTAT generating elements as analog temperature sensors. Linearity of the
PTAT voltage is a crucial parameter that decides the accuracy of the temperature sensor. The PTAT
voltages described before have lesser slopes and need to be amplified to get a better resolution while
converting them to a digital code. The circuit shown in Fig.2.4(b) is cascaded and commonly used as
the analog temperature sensor.
14
Chapter 3
Analysis of Gate-Leakage Current in Inversion and Accumulation

Regions
3.1 Introduction
Advancements in semiconductor technologies have facilitated the aggressive down-scaling of tran-
sistor geometries over the past few decades. As process technology scales to small feature sizes, precise
control of the fabrication process becomes increasingly difficult [6]. Transistor parameters like thresh-
old voltage, gate width, oxide thickness, channel length etc., can vary with process variations [7]. As
the gate-oxide thickness is reduced to 3nm or below, there will be a significant impact of gate-leakage
current due to carrier direct tunneling in low power circuits [8]. This tunneling happens between the
gate and the silicon beneath the gate oxide, with the tunneling carriers being either electrons or holes, or
both. The gate-leakage current can vary from fA to nA depending upon the gate-source voltage applied.
Hence, the gate-leakage current should be taken into consideration while designing circuits operating at
currents which are comparable to the gate-leakage current. These devices, which have a leakage current
flowing through their gates, are referred to as thin-oxide devices or gate-leakage transistors, and are
available in lower technology nodes like 90nm, 65nm, 55nm, 28nm, etc. Although the gate-leakage
current is conventionally thought to be an error inducing and circuit impacting entity, and usually elim-
inated, it can be quite helpful in designing low power circuits with extremely low area. Many state-of-
the-art always-on circuits have exploited the gate-leakage current to achieve a good performance while
consuming low area [9–14]. However, they visualize the gate-leakage transistors as resistors to simplify
the circuit explanations. Although such a visualization eases the understanding of the proposed circuits,
it is important to understand the temperature characteristics of gate-leakage current in different regions
of operation so that it provides a better clarity from mathematical point of view and can help to devise
novel compensation/cancellation schemes. This chapter deduces simple expressions for the variation of
the gate-leakage current w.r.t temperature in inversion and accumulation regions of operation.
15
3.2 Components of Gate-Tunneling Current
The gate-tunneling current is divided into three components [8]:

1) Gate-to-Substrate Current (Igb )
2) Gate-to-Channel Current (Igc )
3) Gate-to-Source/Drain Currents (Igs and Igd )
Fig.3.1(a) shows the gate-tunneling current components and their flow in an NMOS transistor. The
component Igc is partitioned into Igcs and Igcd , which can be unequal if we consider the drain bias
effect. In this work, we limit our discussion to symmetric connections of the terminals in gate-leakage
transistors as shown in Fig.3.1(b). Since the drain, bulk and source terminals are shorted, Vds = 0 and
there is no drain bias effect, and Igs = Igd .
Figure 3.1: (a) Components of gate-tunneling currents (b) Connections of gate-leakage transistors
3.2.1 Gate-to-Substrate Current (Igb )
The gate-to-substrate current Igb is given by Igb = Igbacc + Igbinv [8], where the terms Igbacc and
Igbinv are significant in accumulation and depletion regions respectively. Igbacc for NMOS transistor is
determined by electron tunneling from conduction band and is given by eq.3.1. Note that the descrip-
tions/values of the terms appearing in all the upcoming equations are summarized in Table 3.1.
Igbacc = Wef f · Lef f · A · ToxRatio · Vgb · Vaux ·

exp[−B · T OXE · (AIGBACC − BIGBACC · Voxacc ) · (1 + CIGBACC · Voxacc )] (3.1)
The expressions for the terms ToxRatio , Vaux and Voxacc are given by eqs 3.2, 3.3 and 3.4 respectively :
N T OX
T OXREF 1
ToxRatio = · (3.2)
T OXE T OXE 2
16

Vgb − Vf bzb
Vaux = N IGBACC · vt · log 1 + exp − (3.3)
N IGBACC · vt
Voxacc = Vf bzb − VF Bef f (3.4)
The expressions for Vf bzb and VF Bef f are given by eqs 3.5 and 3.6 :
p
Vf bzb = Vth |zeroVbs andzeroVds − φs − K1 φs (3.5)
q
VF Bef f 2
= Vf bzb − 0.5 (Vf bzb − Vgb − 0.02) + (Vf bzb − Vgb − 0.02) + 0.08Vf bzb (3.6)
where φs is given by :
kB T N DEP
φs = 0.4 + ln + P HIN (3.7)
q ni
and ni is given by :
r
T N OM T N OM qEg (T N OM )
ni = 1.45e10 · · · exp 21.5565981 − (3.8)
300.15 300.15 2 · kB · T
Consider the expression Vgb − Vf bzb in the exponential term of eq.3.3. Substituting the values for
different terms at room temperature from table 3.1, we get ni = 1.7e10, which implies φs = 0.9276V .
The term Vth |zeroVbs andzeroVds is around 400mV at room temperature and typical corner. Substituting
the above values in eq.3.5, we get the value of Vf bzb to be -1V. In accumulation region, Vgb is negative
and its magnitude can vary from 0V to the maximum voltage permissible such that the transistor doesn’t
break down. This maximum voltage is usually around 1V for these thin oxide devices and are operated
well within that voltage. This implies that the expression in the exponential term of eq.3.3 will be a
large negative voltage, which makes Vaux = 0. Hence, Igb is theoretically zero in accumulation region.
In reality, it will possess some magnitude which is much less than the overall gate-leakage current. The
analysis performed above can be extended to different temperatures, different process corners or PMOS
transistors, with the end result being the same (Igbacc is theoretically zero).
Igbinv for NMOS transistor is determined by electron tunneling from valence band and is given by :
Igbinv = Wef f · Lef f · A · ToxRatio · Vgb · Vaux ·

exp[−B · T OXE · (AIGBIN V − BIGBIN V · Voxdepinv ) · (1 + CIGBIN V · Voxdepinv )] (3.9)
Vaux and Voxdepinv in the above equation are given by :

Voxdepinv − EIGBIN V
Vaux = N IGBIN V · vt · log 1 + exp (3.10)
N IGBIN V · vt
p
Voxdepinv = K1ox φs + Vgstef f (3.11)
Here, Vgstef f = Vgse − Vth . where Vgse is the effective gate-source voltage across the channel. In bulk
technologies, the difference between applied gate-source voltage and the effective gate-source voltage
17
across the channel is negligible due to the lower extracted series resistance [15]. Hence, Vgstef f =
Vgs − Vth . The exponential term in eq.3.10 will be negligible compared to 1 if Voxdepinv − EIGBIN V
is greater than atleast 3∗ N IGBIN V ∗ vt . At room temperature, the values of 3∗ N IGBIN V ∗ vt , EIG-
√
BINV and K1ox φs are 150mV, 1.1V and 0.4V respectively. Considering the maximum permissible
Vgs to be 1V (so that the transistor doesn’t break down) and Vth to be 400mV at room temperature and
typical corner, the maximum value of Voxdepinv is 1V. In this work, the maximum value of Vgs is 0.9V,
which implies that Voxdepinv − EIGBIN V is -200mV. This makes the value of Vaux extremely small,
and for even low values of Vgs , Igbinv becomes theoretically zero.
Apart from the argument that the exponential terms of Vaux tend to zero, the absolute values of
Vaux in accumulation and depletion regions are orders of magnitude less than the Vaux values in Igc
or Igs /Igd (refer next section). Even if the exponential term is significant compared to 1, the overall
magnitudes of Vaux in accumulation and depletion regions dwarf the total value of Igb in comparison to
the overall gate-leakage current. The analysis performed above for the overall gate-to-substrate current
(Igb ) supports the statement in [16], which mentions that in bulk technologies, the gate-to-substrate
current is several orders of magnitude less than gate-to-channel and gate-to-S/D currents. The analysis
can be extended to PMOS transistors also, with the result being the same.
3.2.2 Gate-to-Channel Current (Igc )

Igc for NMOS transistor is determined by electron tunneling from conduction band and at Vds = 0,
is given by :
Igc = Wef f · Lef f · A · ToxRatio · Vgse · Vaux · exp[−B · T OXE

(AIGC − BIGC · Voxdepinv ) · (1 + CIGC · Voxdepinv )] (3.12)
Mathematical expressions for Vaux and Voxdepinv are given below.

Vgse − VT H
Vaux = N IGC · vt · log 1 + exp (3.13)
N IGC · vt
p
Voxdepinv = K1ox φs + (Vgs − Vth ) (3.14)
Vgse equals Vgs in bulk technologies as explained before. Assuming gate leakage transistor to be in
strong inversion (Vgs −VT H is 150mV to 200mV) and taking NIGC = 1 from table 3.1, we get exp(Vgse −
VT H /N IGC.vt ) >> 1. Substituting this in eq.3.13, we approximate Vaux to get eq.3.14 :
Vaux = log(e) ∗ (Vgs − Vth ) (3.15)
The equation 3.12 can be further approximated considering few more assumptions and are discussed in
Chapter 4 where an inversion-mode gate-leakage based current reference is designed. In accumulation
region, Vgs is negative, which makes Vaux = 0 and in-turn Igc = 0 (evident from eq.3.12 and eq.3.13).
Thus, the term Igc is only dominant in inversion mode only.
18
3.2.3 Gate-to-Source/Drain Currents (Igs /Igd )
Igs /Igd represent the gate tunneling current between the gate and the source/drain diffusion regions.
For an NMOS transistor, they are determined by electron tunneling from conduction band. Since the
transistor connections are assumed to be symmetric with source, bulk and drain being equal to each
other, Igs = Igd . The expression for Igs is :
0
Igs = Wef f · DLCIG · A · ToxRatioEdge · Vgs · Vgs · exp[−B · T OXE·
0 0
P OXEDGE · (AIGS − BIGS · Vgs ) · (1 + CIGS · Vgs )] (3.16)
0 are given by eqs 3.17 and 3.18 respectively.

The terms ToxRatioEdge and Vgs
N T OX
T OXREF 1
ToxRatioEdge = · (3.17)
T OXE · P OXEDGE (T OXE · P OXEDGE)2
q
0
Vgs = (Vgs − Vf bsd )2 + 0.0001 (3.18)
where Vf bsd is calculated by the below expression :

kB T N GAT E
Vf bsd = log + V F BSDOF F (3.19)
q N SD
In accumulation region, only the gate-to-source/drain currents are dominant as Igc and Igb are negligible.
In inversion region, Igs and Igd do not tend to zero neither theoretically nor practically, instead they
contribute to atmost 5% error considering Igc as the dominant component in inversion region. This
error can be attributed to the difference in various terms of the two equations (eq.3.12 and eq.3.16),
the major being the error between Vgs 0 and V
oxdepinv in the exponentials of the respective equations. A
significant error in the exponential can cause orders of magnitude difference in the overall current and
can be verified by substituting the respective values of different terms. In the sub-nW inversion-mode
gate-leakage based current reference (refer Chapter 4), Igs and Igd contribute to 3% error to the overall
gate-leakage current, which is dominated by Igc . For ease of calculations and deeper insights into the
design of current reference, the error of 3% can be ignored.
Table 3.2 summarizes the dominant components of gate-leakage current in accumulation and deple-
tion regions.
19
Parameter Description Value Units
Wef f Effective width of the transistor Any Value nm
Lef f Effective length of the transistor Any Value nm
A Modelling Constant 4.972e-7 A/V 2
TOXE Electrical gate equivalent oxide thickness 3 nm
TOXREF Nominal gate oxide thickness 3 nm
NTOX Exponent for the gate oxide ratio 1 no units
NIGBACC Parameter for Igb in accumulation 1 no units
K1 First-order body bias coefficient 0.5 V1/2
NDEP Channel doping concentration at depletion edge 1.7e17 cm−3
PHIN Non-uniform vertical doping effect on surface potential 0 V
B Modelling Constant 7.457e11 (g/F − s2 )0.5
AIGBACC Parameter for Igb in accumulation 9.49e-4 (F − s2 /g)0.5 m−1
BIGBACC Parameter for Igb in accumulation 1.71e-3 no units
CIGBACC Parameter for Igb in accumulation 0.075 no units
NIGBINV Parameter for Igb in inversion 1 no units
EIGBINV Parameter for Igb in inversion 1 no units
AIGBINV Parameter for Igb in inversion 9.49e-4 (F − s2 /g)0.5 m−1
BIGBINV Parameter for Igb in inversion 1.71e-3 no units
CIGBINV Parameter for Igb in inversion 0.075 no units
Table 3.1: Gate-Leakage Current Based Model Parameters
20
Parameter Description Value Units
NIGC Parameter for Igc , Igs and Igb 1 no units
AIGC Parameter for Igc 1.32e-2 (F − s2 /g)0.5 m−1
BIGC Parameter for Igc 1.71e-3 no units
CIGC Parameter for Igc 0.075 no units
DLCIG Source/drain overlap length for Igs 0.075 no units
POXEDGE Factor for the gate oxide thickness in source/drain overlap regions 0.075 no units
NGATE Poly Si gate doping concentration 0.075 no units
NSD Source/drain doping concentration 0.075 no units
VFBSDOFF Flatband Voltage Offset Parameter 0.075 no units
AIGS Parameter for Igs 1.32e-2 (F − s2 /g)0.5 m−1
BIGS Parameter for Igs 1.71e-3 no units
CIGS Parameter for Igs 1.71e-3 no units
Components of Gate-Leakage Current Accumulation Region Inversion Region
Gate-to-Substrate Current (Igb ) Non-dominant Non-dominant
Gate-to-Channel Current (Igc ) Non-dominant Dominant
Gate-to-Source/Drain Currents (Igs /Igd ) Dominant Non-dominant
Table 3.2: Components of Gate-Leakage Current in Accumulation and Inversion Regions
21
Chapter 4
A 60pA Inversion-Mode Gate-Leakage Based Current Reference for IoT

and IoT2 Applications
4.1 Introduction
Internet of things forms a new class of computing, in that the data is driven by sensory interfaces, im-
proving data accuracy and reducing human effort [17]. The evolving trends in shrinking the IoT devices
and scaling down their power consumption led to a next class of computing, termed as Internet-of-Tiny-
Things (IoT2 )[18]. These ultra low power tiny devices, in conjunction with miniaturized batteries, open
windows for a wide range of applications including biomedical, environmental and surveillance due to
their lower form factor and longer lifetime.
Although active power consumption of these devices is taken care of by duty cycling, sleep mode
power is a major concern in scaling down the power consumption. This poses constraints on ‘Always on
references’ which occupy large portions of sleep mode power consumption. For eg. current references
in watchdog timers must work with pico-watt power budget to reduce the overall sleep mode power
consumption. Apart from ultra low power and low form factor requirements, these references are desired
to be immune to supply variations.
Conventional current references are either variants of beta multipliers or based on cancelling tem-
perature characteristics of voltage and resistance using an op-amp [19–21]. These architectures require
resistance of 1Gohm to scale down the power consumption to pico-watts, thereby occupying very large
area. [22] reports a 20pA current reference without using any resistance. However, they use the voltage
reference in [23] which suffers from the exponential increase in power consumption w.r.t temperature.
At typical conditions, [23] reports post trim power consumption of 29pW at 200 C, while at 800 C it con-
sumes 2.5nW (i.e 80x increase in power consumption). This power consumption gets worsened further
with process variations. Similarly, other state-of-the-art pico watt voltage references also suffer from
the power shoot up with temperature and process variations[24–26]. Though the current reference is
trimmed to source/sink constant current with process and temperature variations, the underlying disad-
vantage of the voltage biasing circuit shoots up the power consumption. This chapter proposes a current
22
reference whose power consumption including the trimming circuitry is constant w.r.t temperature and
process variations. The proposed current reference has been designed for 60pA, making it suitable for
biasing various circuits (e.g. for biasing op-amps [27, 28]). The total post-trim current consumption is
120pA which is constant with temperature, process and supply variations. To the best of the author’s
knowledge, this is the first pico-watt current reference to resolve the exponential power consumption
problem. Rest of the chapter is organized as follows. Section II shows the circuit level implementa-
tion of the proposed current reference including the proposed trimming circuitry. Results are shown in
section III. Finally, conclusions are drawn in section IV.
4.2 Proposed Current Reference
4.2.1 Design of the Current Reference
Figure 4.1: Proposed current reference including W/L of transistors
23
The proposed current reference is shown in Fig 4.1. Transistors M2, M4 - M7 are regular thick
oxide devices. M1 and M3 are native oxide devices and M0 is a thinner oxide device whose tunneling
based gate leakage characteristics are exploited by operating it in the strong inversion region. A detailed
explanation of the gate leakage is provided later.
A closer look at the circuit reveals that the proposed current reference is a modified version of the
conventional beta multiplier architecture. The two main modifications include the replacement of a
large physical resistor with a leakage transistor (thinner oxide device) and the use of native oxide device
instead of a thick oxide device. The leakage transistor helps in scaling down the power consumption
to pico-watts without compromising on area, since a large resistor (∼ 1Gohm) has been replaced by a
single transistor. The use of native oxide devices is associated with the elimination of start-up circuit
since the architecture is a self-biased arrangement of transistors. In modern foundries, native oxides are
widely available and do not incur additional mask steps [29]. Hence, the native oxide has been used as
it doesn’t incur any extra cost. The property of near-zero threshold voltage of the native oxide device
is used in eliminating the use of a start-up circuit. This is explained as follows. Even if the circuit is
struck at a degenerate bias point (M1 , M2 gates struck at ground and M6 , M7 gates struck at VDD ), the
native oxide device turns on (as its threshold voltage is almost zero) and restores the operating point.
Hence, the need of extra hardware and extra power consumption due to the start-up circuit is eliminated.
Other modifications in the circuit include addition of transistors M3 , M4 and M5 . Transistor M3 is used
as cascode device to enhance the supply rejection of the reference. Transistors M4 − M7 form a self-
cascode current mirror. This kind of a current mirror is chosen because of its high output impedance
and lower voltage headroom.
In an abstract way, the proposed current reference relies on the idea of obtaining a constant gate
leakage by applying a suitable bias voltage at the gate of the leakage transistor. Gate leakage unlike other
leakages increases marginally with temperature for a constant applied gate voltage [30]. So, if we apply
a CTAT voltage to the gate of leakage transistor, we get a constant gate leakage current. This CTAT
voltage is achieved by taking the difference between the threshold voltages of thick oxide and native
oxide devices. A detailed analysis of the gate leakage is provided along with rigorous mathematical
derivations to validate the abstract idea.
The gate tunneling current in the leakage transistor consists of Gate-to-Substrate Current (Igb ), Gate-
to-Channel Current (Igc ) and Gate-to-Source/Drain Currents (Igs and Igd )[31]. However, in bulk tech-
nologies, the gate-to-substrate current is several orders of magnitude less than gate-to-channel and gate-
to-S/D currents[16]. Hence, it is neglected. The currents Igs and Igd account for less than 3% change
in the total gate leakage. Hence, they are also neglected. The dominant component of gate tunelling
current is the gate-to-channel current (Igc ) given by [31]:
Igc = Wef f Lef f .A.ToxRatio .Vgse .Vaux .exp[−B.T OXE

(AIGC − BIGC.Voxdepinv ).(1 + CIGC.Voxdepinv )] (4.1)
24
Where Wef f , Lef f are effective width and effective length of the mosfet respectively. Vaux is a fitting
function of the tunneling carrier density and available states. Voxdepinv is the voltage across the gate
oxide in depletion/inversion region. Mathematical expressions for Vaux and Voxdepinv are given below.
The parameters A, ToxRatio , B, TOXE, AIGC, BIGC, CIGC, NIGC in eq.4.1 and eq.4.2 are constants
for a given technology and are independent of temperature.

Vgse − VT H
Vaux = N IGC.vt .log 1 + exp (4.2)
N IGC.vt
p
Voxdepinv = K1ox φs + (Vgs − Vth ) (4.3)
where φs is the surface potential equal to Vgs − Voxdepinv . The term Vgse in eq.4.1 and eq.4.2
is the effective gate-source voltage across the channel. In bulk technologies, the difference between
applied gate-source voltage and the effective gate-source voltage across the channel is negligible due
to the lower extracted series resistance [15]. So the term Vgse is equal to Vgs . Now, an emphasis is
made on the values of NIGC, AIGC, BIGC and CIGC to approximate eq.4.1 and eq.4.2. From [31],
the values of NIGC, AIGC, BIGC and CIGC for an NMOS transistor are 1, 0.0136, 0.00171 and 0.075
respectively. Assuming gate leakage transistor to be in strong inversion (Vgs −VT H is 150mV to 200mV)
and substituting NIGC = 1, we get exp(Vgse − VT H /N IGC.vt ) >> 1. Substituting this in eq.4.2, we
approximate Vaux as :
Vaux = log(e) ∗ (Vgs − Vth ) (4.4)
The variation of the exponential term in equation 4.1 is less than 10% assuming a 10% change in
Voxdepinv . This assumption is justified at the end of the section. Even though Voxdepinv changes by a
significant amount (i.e 10%), the overall variation in the exponential term is less because of the small
values of BIGC and CIGC. Hence, the exponential term in eq.4.1 can be approximated by a linear fit
curve given by f (Voxdepinv ) = K2 (1 + aVoxdepinv ), where a is a constant whose value is very small. So
eq.4.1 can be finally simplified as :
Igc = K ∗ K2 ∗ Vgs (Vgs − Vth )(1 + aVoxdepinv ) (4.5)
where K = Wef f ∗ Lef f ∗ A ∗ ToxRatio ∗ log(e). Eq.4.5 is differentiated w.r.t temperature to get the
temperature coefficient of the gate leakage current. The temperature coefficient is then equated to zero
to get a temperature compensated gate leakage current. The mathematical expression is given by :
∂Voxdepinv ∂Vgs
aVgs (Vgs − Vth ) + (Vgs − Vth )(1 + aVoxdepinv )
∂T ∂T
∂Vgs ∂Vth
+ Vgs (1 + aVoxdepinv ) − = 0 (4.6)
∂T ∂T
∂Voxdepinv
The expression for ∂T in eq.4.6 is obtained by differentiating eq.4.3 w.r.t temperature.
∂Voxdepinv ∂Vgs ∂Vth

= − ∗ K3 (4.7)
∂T ∂T ∂T
25
where K3 is given by : !
p
2 Vgs − Voxdepinv
K3 = p (4.8)
2 Vgs − Voxdepinv + k1ox
Substituting eq.4.7 into eq.4.6 and simplifying further, we get :
∂Vgs ∂Vth
= ∗ K4 (4.9)
∂T ∂T
where K4 is given by :
Vgs
aK3 Vgs + Vgs −Vth (1 + aVoxdepinv )
K4 = Vgs
(4.10)
aVgs + Vgs −Vth (1 + aVoxdepinv ) + (1 + aVoxdepinv )
From eq.4.9 and eq.4.10, we draw the following inferences. Since the temperature coefficient of Vth is
negative, the required temperature coefficient of Vgs should also be negative (K4 is a positive quantity
which is evident from eq.4.10). Hence, Vgs (equal to Vbias ) should be a CTAT voltage with a slope
which can be calculated from eq.4.9 and eq.4.10. Note that the slope should have a very less dependence
on process and temperature variations, because the dominant process and temperature dependent term
(Vgs /Vgs -Vth ) in K4 appears in both numerator and denominator. To summarize, the required Vbias (refer
Fig.4.1) should be a CTAT voltage whose slope can slightly vary with temperature and process to get a
current reference with process invariant temperature coefficient. The expression for Vbias in the circuit
can be deduced by equating the currents in transistors M1 and M2 which are collectively given by the
well known sub-threshold current equation[32]:

W1 VGS1 − Vth1
I = µ1 COX1 (m1 − 1)VT2 exp
L1 m1 VT

W2 VGS2 − Vth2
= µ2 COX2 (m2 − 1)VT2 exp (4.11)
L2 m2 VT
Here, the dependency of VDS on the currents is ignored by applying the condition VDS > 4VT . Taking
logarithm on both sides and simplifying equation 4.11, we get :

VGS2 VGS1 Vth2 Vth1 µ1 Cox1 W1 L2
− = − + VT ln (4.12)
m2 m1 m2 m1 µ2 Cox2 W2 L1
The observed values of m1 and m2 are 1.1 and 1.05 respectively. To avoid complications in solving
eq.4.12, we neglect the 5% error between m1 and m2 and consider them to be approximately equal (to
m). This leads to eq.4.13.

µ1 Cox1 W1 L2
VGS2 − VGS1 = Vth2 − Vth1 + mVT ln (4.13)
µ2 Cox2 W2 L1
Realizing that VGS2 - VGS1 = Vbias , we get eq.4.14

µ1 Cox1 W1 L2
Vbias = Vth2 − Vth1 + mVT ln (4.14)
µ2 Cox2 W2 L1
26
Considering the temperature coefficients of Vth1 to be k1 and Vth2 be k2 (k1 > k2 ), the temperature
dependency of Vbias can then be expressed as :

∂Vbias k µ1 Cox1 W1 L2
= k2 − k1 + m ln (4.15)
∂T q µ2 Cox2 W2 L1
From eq.4.15, it is evident that by properly sizing M1 and M2, a CTAT voltage of desired slope can
be achieved. As deduced earlier, this slope is independent of temperature and process variations. From
eq.4.14 and eq.4.15, we have calculated the maximum change in Vbias and consecutively Voxdepinv with
process and temperature variations. The maximum change in Voxdepinv is observed to be 7.7%, which
justifies the linear fit assumption of the exponential term in eq.4.5.
4.2.2 Proposed Trimming Circuit
b3 b2 b1 b0
W/L W3/L W2/L W1/L W0/L
Figure 4.2: Proposed Trimming Circuit
Although the temperature coefficient of current reference is less susceptible to process variations,
the absolute value of the current reference varies with process. We propose the trimming circuit (as
shown in Fig.4.2), where we switch on/off other leakage transistors depending on the trim bits, to bring
back the current to its nominal value. Regular NMOS thick oxide devices are used as switches in the
trimming circuitry due to their negligible gate leakage.
4.3 Results and Discussion

The proposed current reference is implemented in UMC 55nm technology. Post trim simulations of
the Iref in various corners is shown in Fig. 4.3. In typical corner, the proposed reference achieves an
27
accuracy of 19ppm, while in the worst corner FS, it achieves an accuracy of 85ppm. Fig. 4.4 shows
the plot of Iref with supply. The current reference works for a supply range of 1.2V - 4V with a very
good line sensitivity of 0.07%/V. Fig. 4.5 shows the post trim power consumption w.r.t temperature
and process variations. It can be deduced from Fig. 4.5 that the power consumption (2*VDD *Iref )
is constant w.r.t temperature and process as the circuit doesn’t involve any voltage biasing circuitry
which suffers from the exponential increase in power consumption. As explained earlier, the circuit
doesn’t require any start-up circuit. To validate this, we connected power down and power up signal
as in [33]. When power down signal is asserted, the circuit stays in idle state (i.e gate of M4 − M7
charged to VDD ) and gates of M1 − M3 discharged to ground). When power down signal is de-asserted,
the proposed current reference unlike conventional beta multipliers restores operating point without the
need of start up circuit. Fig. 4.6 shows the power down signal and Iref with time. A start up time
in the worst case process corner is observed to be 5ms for 100fF load capacitance. This is 10x times
smaller than [34]. Although, the start up time is of the order of milli seconds (ms), it is tolerable for
always on references since we don’t duty cycle them. Moreover, speed constraints are also relaxed
in ultra-low power applications. To evaluate load sensitivity, we copied the current through PMOS
self cascode current mirror (M4 − M7 ). A very good load sensitivity of 0.3%/V can be noticed from
√
Fig. 4.7 till 4V supply. Simulation results show a noise current of 5.4f A/ Hz at 1Hz and a noise
√
floor of 4.9f A/ Hz. Statistical performance of the current reference is validated through monte-carlo
simulation and the results are shown in Fig.4.8. The average temperature coefficient is observed to
be 73ppm, with a standard deviation of 50ppm. Fig. 4.9 shows the layout of the proposed current
reference from which the active area is estimated to be 0.0003mm2 , which is very low. Finally, Table
4.1 compares the proposed current reference with state-of-the-art current references.
4.4 Conclusion
The chapter presents an eight transistor (8T) pico-watt current reference with a novel method of
rectifying the problem of exponential power increase w.r.t temperature in traditional sub-nW references.
The proposed current reference is obtained by modifying the traditional beta-multiplier architecture
to scale-down the power consumption without sacrificing area. The constancy of power consumption
w.r.t temperature is achieved by exploiting the voltage-current characteristics of a leakage transistor in
the modified architecture. The proposed current reference, implemented in UMC 55nm technology,
occupies an area of 0.00035mm2 . It is designed for a current of 60pA and achieves an accuracy of
19 ppm/0 C over a wide temperature range of −550 C to 1250 C. The reported line sensitivity for the
current reference is 0.07%/V in the supply range of 1.2V - 4V.
28
60.8
60.6
60.4
Iref (pA)
60.2
60.0
FF
59.8 SF
SS
59.6 TT
FS
59.4
-60 -40 -20 0 20 40 60 80 100 120 140
temp(°C)
Figure 4.3: Post trim simulation of current Iref w.r.t temperature in different process corners
Figure 4.4: Line sensitivity of Iref
29
146.5
146
145.5
Power (pW)
145
144.5
FF
144 SF
SS
143.5 TT
FS
143
-60 -40 -20 0 20 40 60 80 100 120 140
temp(°C)
Figure 4.5: Post trim power consumption w.r.t temperature in different process corners
Figure 4.6: Start-up time for Iref
30
Figure 4.7: Load sensitivity of Iref
Figure 4.8: Montecarlo simulation of temperature coefficient
31
Figure 4.9: Layout of proposed current reference
Specifications This Work [22] [34] [35]
Technology 55nm 180nm 65nm 130nm
Supply Range 1.2V-4V 1.2V-4V 0.4V-1.2V 0.7V-2.5V
Reference Current (pA) 60 20 1.2 3.2
Accuracy (ppm/o C) 73 (avg from MC runs) 780 (measured) 469.3 (measured) 161 (measured)
Power (pW) @ tt & 27o C 144 23 3.4 6
Power w.r.t temperature constant exponential exponential exponential
Temperature Range (o C) -55 to 125 0 to 80 -20 to 60 0 to 85
Line sensitivity (%/V) 0.07 0.58 2.5 0.62
Load sensitivity (%/V) 0.3 0.25 NA NA
Area (mm2 ) 0.00035 0.048 0.008 0.00055
Table 4.1: Comparison With State-of-the-Art Architectures
32
Chapter 5
A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference

for IoT Applications
5.1 Introduction
The gaining popularity and rapid development of the Internet-of-Things (IoT) has spawned several
applications such as environmental, biomedical, military, smart homes, etc. The systems designed for
these applications are often powered by miniaturized batteries, which have limited energy storage vol-
ume. This limitation in the energy budget renders the power consumption of the system a critical factor
in deciding the system’s lifetime. Duty-cycling is a widely adopted strategy to reduce the average power
of the system, thereby effectively managing the energy provided by the battery. However, the system
mostly stays in sleep mode and hence the overall power consumption is limited by the blocks which
contribute to the sleep-mode power consumption. Voltage references are among such blocks which
are typically always turned on and contribute to the standby power consumption. Hence, it becomes
imperative for the voltage references to comply with the stringent power constraints, thus providing a
motivation to design pico-watt voltage references. Since bandgap references are the most reliable volt-
age references due to their robustness to process, supply and temperature, it is worthwhile to design
bandgap references for the sub-nW regime.
Conventional bandgap references have micro-watt power consumption [36–39] which precludes their
use in low-power IoT applications. To alleviate this issue, bandgap references whose static power con-
sumption is in the order of nano-watts [40–43] have been proposed in the state-of-the-art. However,
their power consumption is still high for the targeted applications. Moreover, large physical resistors
are used in [41–43] to scale down the power consumption to nano-watt level, thereby increasing the
silicon area. [44] proposes a sub-10nW BGR but again incorporates large resistors. [45] proposes a
dynamic BGR by adopting a sample-and-hold method for reducing the overall power consumption to
2.98nW. However, it uses large sampling capacitors in addition to large resistors, thereby increasing the
area drastically. The driving force to reduce the power consumption further has resulted in the design
of pico-watt bandgap reference voltage (∼1.2V) generators [46, 47]. They, however use native oxide
33
devices (NVT transistors) to generate the reference voltage, which are not provided by many foundries.
Moreover, [47] has significant process spread and requires trimming, thereby increasing the cost.
This chapter proposes a bandgap reference which consumes sub-nW power without using large phys-
ical resistors, native oxide devices or any other sophisticated techniques which increase either area or
power. It rather incorporates thin oxide devices which are made to operate in accumulation region and
the accumulation-mode gate-leakage current characteristics are used in generating the reference voltage.
Rest of the chapter is organized as follows. Section II deals with the design of the proposed bandgap
reference by deriving a simplified expression for the accumulation-mode gate-leakage current. Section
III shows the results for the designed reference and finally section IV concludes the chapter.
5.2 Design and Analysis of the Proposed Bandgap Reference

Fig.5.1 depicts the architecture of the proposed bandgap reference. Transistors M1-M6 and M7-M10
are regular thick oxide PMOS and NMOS devices respectively while M11-M15 are thin oxide PMOS
transistors. Due to the extremely small oxide thickness, tunnelling currents of the order of fA to pA
flow through the gate of these transistors [48]. They are made to operate in the accumulation region, in
which the simplified expression for the gate-leakage current can be derived as shown in the following
sub-section. Q1, Q2 and Q3 are vertical PNP transistors or parasitic BJTs. A capacitor implemented
using NMOS thick oxide transistor M16, is used at the output of the voltage reference to suppress the
supply noise at higher frequencies. A start-up circuit [49] has been used to avoid any degenerate bias
conditions in the circuit.
5.2.1 Derivation for accumulation-mode gate-leakage current
The simplified expression for accumulation-mode gate-leakage current can be deduced by using
the gate-tunnelling current model for the thin-oxide devices given in [8]. The gate tunnelling current
consists of four components, namely, gate-to-substrate current (Igb ), gate-to-channel current (Igc ) and
gate-to-source/drain currents (Igs and Igd ). Of these components, Igb can be ignored in bulk technolo-
gies, as it is negligible compared to the total gate-leakage current [50, 51]. The component Igc can also
be neglected as it is a function of Vsg − |Vth | (for PMOS), whose negative value (since the transistor is in
accumulation region) forces its magnitude to be several orders less than that of the overall gate-leakage
current. Owing to the symmetric connections of the source and drain of the transistor to its bulk, the
components Igs and Igd will be equal to each other. Hence the total gate-leakage current Itot can be
given as twice the gate-to-source/drain current (Igs /Igd ) [8] :
0 0 0
Itot = k1 .Vsg .Vsg .exp[−k2 .(AIGSD − BIGSD.Vsg ).(1 + CIGSD.Vsg )] (5.1)
where k1 = 2∗ Wef f .(DLCIG).A.ToxRatioEdge and k2 = B.(T OXE).(P OXEDGE). Here, Wef f

is the effective width of the transistor and DLCIG, A, ToxRatioEdge , B, TOXE, and POXEDGE are
34
Vdd
M1 M5
M2
Kstart M3 M6
M4
V ref
Start-up Circuit M7 M8
M12 M16
M9 M10
M13
Q1 M11 Regular Thick

M14 Oxide NMOS
Q2
Regular Thick
M15 Oxide PMOS
Q3 Thin Oxide
PMOS
Figure 5.1: Proposed Bandgap Reference

modelling constants for a given technology which are independent of temperature. The expression for
0 in the eq.5.1 is given by :
the term Vsg
q
0
Vsg = (Vsg − Vf bsd )2 + 0.0001 (5.2)
where Vf bsd is the flat-band voltage between gate and S/D diffusions calculated by :

kB T N GAT E
q N SD
Again, NGATE, NSD and VFBSDOFF are modelling constants. The values of NGATE, NSD and
VFBSDOFF in the designed technology node are observed to be 181.2E, 100E and 0 respectively.
Substituting their values in eq.5.3, the value of Vf bsd turns out to be 6.67mV at room temperature.
Considering the least |Vsg | across M11-M15 to be 40mV, Vf bsd cannot be neglected in comparison
35
with |Vsg |. However, the term 0.0001 can be neglected under these conditions for which Vsg0 becomes
equal to Vsg − Vf bsd . The values of AIGSD, BIGSD and CIGSD are observed to be 4.96m, 0.207m
and 4.264m respectively. From these values, it can be deduced that AIGSD >> BIGSD.Vsg0 and
CIGSD.Vsg0 << 1, considering the maximum value of |Vsg | across M11-M15 to be 350mV. Hence,
the terms BIGSD.Vsg0 and CIGSD.Vsg0 can be neglected as they contribute to a maximum error of
6% in Itot . Equation 5.1 can be finally approximated as :
Itot = KVsg (Vsg − Vf bsd ) (5.4)
where K = k1 .exp(−k2 .AIGSD). To validate this approximated equation, we plot the error between the
simulated gate-leakage current and the estimated current from eq.4 w.r.t magnitude of Vsg in different
process corners (shown in Fig.5.2). It can be observed that the maximum error is 6% w.r.t variation in
Vsg across all process corners.
Figure 5.2: % error between simulated and estimated results vs |Vsg |
5.2.2 Temperature Compensation

From Fig.5.1, Vsg across M11 is equal to VEB2 −V EB1 . Considering
the I-V characteristics of a BJT,
I I
Vsg across M11 can be further simplified as VT ln IS2 − VT ln IS1 . Here, transistor Q2 consists
‘n’ parallel units of Q1, which implies IS2 = nIS1 . So the Vsg across M11 can be written as VT ln n1

and from eq.5.4, current in the transistor M11 can be given by :
Itot = K1 VT ln(n)(VT ln(n) + Vf bsd ) (5.5)
36
where K1 is a function of effective width Wef f of M11. Current in the circuit can also be given by
the gate-leakage current flowing through transistors M12-M15 (same current through all the branches).
Note that M12-M15 have same widths and lengths but not equal to those of M11. The expression for
gate-leakage current in M12-M15 is given by :

Vref − VEB3 Vref − VEB3
Itot = K2 + Vf bsd (5.6)
4 4
where K2 is a function of effective widths Wef f of M12-M15. Since Vref is a higher voltage of value ∼
1.2V, Vf bsd in eq.5.6 can be neglected in comparison to the term (Vref − VEB3 )/4. Note that instead of
using four transistors (M12-M15), a single transistor can be used. However, the width of that transistor
should be kept very low, which will cause large effect on the output voltage due to mismatch of tran-
sistors. In some technology nodes, it is also not possible to decrease the width beyond a certain extent.
Hence, considering the area and mismatch trade-off, four transistors have been used. From eq.5.5 and
eq.5.6, the final expression for Vref can be given by :
Vref = VEB3 + 4K3 VT (5.7)
where K3 is a constant independent of temperature and is given by :

v
!
u K1 (ln(n))2 + K1 ln(n)log N GAT E
u
N SD
K3 = t (5.8)
K2
Here, VEB3 is a CTAT term while 4K3 VT is a PTAT term. To get a temperature compensated
voltage
∂Vref ∂VEB
reference, its derivative ∂T should be equated to zero. Using the expression for ∂T (for Q3)

∂V
from [52], the expression for ∂Tref can be given by :
Eg
VEB3 − (4 + mQ3 VT − q )

∂Vref kB
= + 4K3 (5.9)
∂T T q
From eq.5.9, it can be observed that by properly sizing the transistors M11-M15, a temperature com-
pensated voltage reference can be obtained. Transistor M11 is sized such that the current in each of the
branches is ∼100pA. M12-M15 are then sized according to eq.5.9.

The proposed bandgap reference is implemented in TSMC 65nm technology and various post-layout
and Monte-Carlo simulation results are shown in this section. Fig.5.3 shows the variation of the bandgap
reference voltage w.r.t temperature in extreme process corners. The observed TCs of the bandgap ref-
erence in these corners are 23ppm/o C, 41ppm/o C and 31ppm/o C in all TT, all SS and all FF corners
respectively. For statistical validation of the bandgap reference, Monte-Carlo simulations are run (1000
runs for both process and mismatch) for the reference voltage and the temperature coefficient (TC) of
37
the BGR. The results for these are shown in Fig.5.4 and Fig.5.5 respectively. Although the simulation is
run for 1000 samples, Fig.5.4 shows the variation of the reference value w.r.t temperature for 50 samples
(including the worst case corners) for the sake of clarity. The maximum inaccuracy (±3σ) considering
temperature, process and mismatch variations is observed to be 3%. Fig.5.5 shows the Monte-Carlo
simulation result for TC of the bandgap reference. The mean and standard deviation in the TC are
observed to be 23ppm/o C and 6.745ppm/o C respectively, with the maximum TC being 44ppm/o C.
From the results of Fig.5.4 and Fig.5.5, it can be concluded that the bandgap reference is process-
invariant and one-point calibration can be used for applications where the variations need to be further
reduced. Fig.5.6 shows the PSRR of the bandgap reference in different process corners. The observed
PSRRs at DC are -65dB, -64dB and -66dB in all TT, all SS and all FF corners respectively. At higher
frequencies, the PSRR is observed to be around -35dB. The supply rejection at higher frequencies can
be improved further by simply increasing the width and length of the MOS capacitor M16 at the cost
of increase in area. Fig.5.7 shows the line-sensitivity of the bandgap reference in different process cor-
ners. In a wide supply range of 1.5V - 3.8V, the line sensitivities are observed to be 0.063%/V, 0.12%/V
and 0.48%/V in all TT, all SS and all FF corners respectively. Fig.5.8 and Fig.5.9 show the current
consumption of the BGR w.r.t temperature and supply voltage respectively. The variation in the current
is observed to increase by only 2.338x times w.r.t temperature in the temperature range of −40o C to
100o C. On the other hand, it increases by only 1.006x times w.r.t supply voltage when the latter varies
from 1.5V - 3.8V. Fig. 5.10 shows the start-up time of the BGR. The observed settling times for 90%
and 95% of the steady state value are 45ms and 78ms respectively. Although the start-up time appears
to be high, it is quite comparable to the start-up times of state-of-the-art pico-watt self-biased blocks
[53]. Fig.5.11 shows the layout of the proposed bandgap reference from which the area is calculated
to be 0.009mm2 . Finally, Table 5.1 compares various specifications of the proposed bandgap reference
with the state-of-art bandgap references.
5.4 Conclusion
The chapter presents a sub-nW bandgap reference that exploits the temperature variation of gate-
leakage current in thin oxide devices operating in the accumulation region to generate the reference
voltage. The incorporation of gate-leakage transistors scales down the power consumption of the BGR
to pico-watt level without using any large physical resistors or sophisticated techniques, thereby making
it suitable for IoT applications. The BGR is designed in TSMC 65nm technology and occupies an area
of 0.009mm2 . Post layout simulation results show nominal and worst-case accuracies of 23ppm/o C
and 44ppm/o C respectively in the temperature range of −40o C to 100o C. Without any trimming,
an inaccuracy (±3σ) of 3% is observed for the reference voltage, showing its resilience to process
variations. It also exhibits a typical line sensitivity of 0.063%/V in a supply range of 1.5V-3.8V and
a PSRR of -65dB at DC and 1.8V supply. The power consumption is observed to be 443pW at 1.5V
supply and nominal temperature.
38
Figure 5.3: Proposed bandgap reference in different corners
Figure 5.4: Monte-Carlo simulation result for the BGR value w.r.t temperature
39
Figure 5.5: Monte-Carlo simulation result for the TC of BGR
Figure 5.6: PSRR of the BGR at different process corners
40
Figure 5.7: Line sensitivity of the BGR in different process corners
Figure 5.8: Current consumption of the circuit vs temperature
41
Figure 5.9: Current consumption of the circuit vs supply voltage
Figure 5.10: Start-up time of the BGR
42
Figure 5.11: Layout of the BGR
Specifications This Work [36] [41] [42] [44] [45] [46] [47]
Technology 65nm 160nm 90nm 180nm 180nm 180nm 180nm 180nm
Type BJT BJT BJT BJT CMOS BJT CMOS CMOS
Res/Cap/NVT devices Not Used Used Used Used Used Used Used Used
Vref (V) 1.245 1.0875 0.72 1.2 1.238 1.19 1.25 1.17
Temperature Range (o C) -40 to 100 -40 to 125 0 to 100 -45 to 125 0 to 110 -20 to 100 0 to 100 0 to 170
TC (ppm/o C) 23 (MC run) 5-12 (measured) 53.1 32.7 26 24.74 8-53 32-106
3σ Inaccuracy (@ 27o C) 1.5% ±0.75%/±0.15% 1.3% 0.51% 0.63% 0.432% 2.4%/0.8% 1.7%
Calibration Untrimmed Untrimmed/1-point Untrimmed 1-point Untrimmed 1-point Untrimmed/1-point 1-point
Supply Range 1.5V-3.8V 1.8±10% NA 2V-5V NA NA 1.4V-3.6V 1.8V-3.6V
Line sensitivity (%/V) 0.063 NA 0.3 0.058 0.08 0.062 0.31 0.09
PSRR -65dB @ DC -74dB @DC -51dB@DC -85dB@100Hz -46dB@100Hz -67dB@100Hz -41dB@100Hz -38dB@100Hz
Power Consumption 443pW @ 1.5V 99uW @ 1.8V 576nW @ 1.2V 192nW @ 2V 9.3nW @ 1.4V 2.98nW 33.6pW @ 1.4V 136.8pW @ 1.8V
Area (mm2 ) 0.009 0.12 0.028 0.063 0.055 0.98 0.0025 0.0081
Table 5.1: Comparison with State-of-the-Art Architectures
43
Chapter 6
Accumulation-mode gate-leakage based Voltage/Current References
6.1 Introduction
The advent of the Internet-of-Things (IoT) has led to the proliferation of feature-rich smart devices
like wearable medical devices and wireless sensor nodes. These systems are often powered by micro-
batteries, which supply less-than-ideal energy, demanding the usage of power-aware design. The serious
energy constraints, along with aggressive form factor, cost and lifetime targets entailed by such systems
has given a technological boost for the research efforts towards the design of ultra-low power and low
area circuits. Duty-cycling is a widely adopted strategy to reduce the average power consumption of
these systems. However, its benefits can only be retained when the power consumption of the always-on
blocks is greatly reduced. This motivates the aggressive power aware design of voltage and current
references, which are typically always-on and indispensable components in any such system.
Voltage references are conventionally realized using BJTs and are termed as bandgap references
(BGR) [36–39]. Although the generated voltage in BGRs is highly resilient to process, supply and tem-
perature (PVT) variations, their power consumption is in the order of µW, which can prove detrimental
to the targeted system’s lifetime. The state-of-the-art also comprises of nano-watt BGRs [40–45], with
[45] consuming power as low as 2.98nW. However, they are still not suitable for the targeted applica-
tions due to large area consumption (> 0.01mm2 ), and large power consumption (> 1nW). Moreover,
all these references require start-up circuits, whose presence along-side the core circuitry in ultra-low-
power systems demand their power consumption to be dwarfed and their implementation to be robust.
The sub-threshold region of operation in CMOS transistors has also been exploited to design voltage
references. [54–60] propose nano-watt voltage references, with the drawbacks of >1nW power con-
sumption, large area [55–60] and the requirement of start-up circuits [55–58, 60]. The emerging trend
in aggressive down-scaling of power consumption has led to the evolution of pico-watt voltage refer-
ences [61–68]. The power consumption in these references increases exponentially w.r.t temperature and
can reach nano-watts at high temperatures (∼100x greater compared to room temperature). [10] & [69]
propose 443pW bandgap reference and 114pW voltage reference respectively having non-exponential
44
increment in power w.r.t temperature but again incorporate start-up circuits which require a pulse signal
from external circuitry.
Current references are conventionally variants of the beta-multiplier or generated based on V/R prin-
ciple using op-amp and cancelling the temperature coefficients (TCs) of voltage and resistors [19–21].
However, such resistor based architectures are not suitable for designing pico-watt current references as
they would incur impractically large area. [12–14, 70] propose pico-watt current references, of which
[70] uses the voltage reference from [47] and hence suffers from exponential shoot-up in power con-
sumption. [12–14] contain self-biased configurations resulting in large start-up times, thereby requiring
start-up circuits. [9] proposes a 60pA current reference without start-up circuit and has constant power
consumption w.r.t temperature. It generates a CTAT bias voltage across the gate leakage device for ref-
erence current generation, hence this architecture cannot be used simultaneously as voltage and current
reference. [42, 44, 56, 71] propose voltage and current references in a single circuit but are unsuitable
for the targeted applications for the reasons mentioned above.
This chapter presents two accumulation-mode gate-leakage based voltage/current reference without
the use of resistors, external signals, and start-up circuits. The power consumption of these circuits do
not increase exponentially w.r.t temperature unlike conventional voltage and current references. This
enables the working of the circuit at negative temperatures like -40o C. The circuits retain the above ad-
vantages without compromising on other specifications like temperature range, accuracy, line sensitivity
and PSRR, thus making them suitable for the targeted applications. We chose accumulation-mode op-
eration of gate-leakage transistors over the inversion mode as we get a constant current in the circuit if a
constant voltage is applied to a gate-leakage transistor operating in accumulation mode (Refer chapters
3). Thus, both voltage and current reference can be realized in a single circuit. In inversion mode, a
constant current is realized only when a mild CTAT voltage (Chapter 4) is applied at the gate of thin
oxide transistors. Both voltage and current references cannot be realized in this case. The chapter deals
with two such voltage/current references using gate-leakage transistors in accumulation mode. The first
configuration requires slightly higher supply voltage than the second configuration.
6.2 First Configuration
6.2.1 Circuit level architecture

In chapter 4, a current reference has been proposed that incorporates gate-leakage transistor in inver-
sion region (Fig. 6.1). As discussed earlier, a mild CTAT voltage is required at the gate of the thin-oxide
transistor (Vbias ) to generate a current reference. If the NMOS gate-leakage transistor M0 is replaced by
PMOS transistor as shown in Fig.6.2, it operates in accumulation region since Vbias is a positive voltage,
making VSG of PMOS negative. The equations for gate-leakage current in accumulation region have
already been derived in Chapter 5. The final equation is written here :
45
Figure 6.1: Proposed current reference in chapter 4
Figure 6.2: Proposed Voltage/Current Reference
Itot = KVsg0 (Vsg0 − Vf bsd ) (6.1)
K = 2∗ Wef f .(DLCIG).A.ToxRatioEdge .exp(−B.T OXE.P OXEDGE.AIGSD) (6.2)

kB T N GAT E
q N SD
Here, Wef f is the effective width of the transistor, while DLCIG, A, ToxRatioEdge , B, TOXE, POXEDGE,
AIGSD, NGATE, NSD and VFBSDOFF are modelling constants [31], which are independent of tem-
perature variations. The term Vf bsd can be neglected in comparison to Vsg0 (= Vbias ) as its only 6.67mV
46
at 27o C and Vbias will be around 700mV. The expression for the current now becomes :
Ibias = K0 (Vbias )2 (6.4)
It can be seen from eq.6.4 that if Vbias is a reference voltage, then Ibias will be a reference current,
thereby allowing the presence of both voltage and current reference in a single circuit. The expression
for Vbias is the same as eq.6.5 :

µ1 Cox1 W1 L2
Vbias = Vth2 − Vth1 + mVT ln (6.5)
µ2 Cox2 W2 L1
Considering the temperature coefficients of Vth1 to be k1 and Vth2 be k2 (k1 > k2 ), the temperature
dependency of Vbias can then be expressed as :

∂Vbias k µ1 Cox1 W1 L2
= k2 − k1 + m ln (6.6)
It is evident from eq.6.6 that by properly adjusting the sizes of M1 and M2, ∂Vbias /∂T can be made
equal to zero, thereby making it a temperature compensated voltage. This further makes the current in
the circuit independent of temperature variations. However, due to the direct dependence of Vbias on the
threshold voltages on thick oxide and native oxide transistors which are uncorrelated with each other, a
large process spread will be observed for Vbias . Fig.6.3 shows the process variation (for 5 corners) of
Vbias after the adjustments in sizes of M1 and M2 for temperature compensation.
Figure 6.3: Variation of Vbias voltage with process and temperature
It can be seen from Fig. 6.3 that the overall deviation in Vbias in different corners is around 130mV
(17.5%), which is very large. Although this variation can calibrated by adjusting the sizes of M1 or
M2, the temperature coefficient will degrade drastically due to the presence of width and length terms
in the temperature coefficient of Vbias (eq.6.5). A two-point calibration will then ben required, thereby
increasing the cost. To alleviate this issue, the current is mirrored into another gate-leakage transistor
M10 which operates in accumulation region. The current can then be given by :
Ibias = K10 (Vref )2 (6.7)
47
From eqs.6.4 and 6.7, we get :
K10
Vref = Vbias (6.8)
K0
Here K10 /K0 = Wef f 10 /Wef f 0 . Eq.6.8 shows that Vref is a scaled version of Vbias and if this ratio is
independent of temperature variations, Vref replicates the variations in Vbias .
Figure 6.4: The ratio K10 /K0 w.r.t temperature in different corners
Vdd
M6 M8
M7
M4 M9
M5
Vref
M3
B0 B1 B2 B3 B4
M1 M2
Vbias
M0
Figure 6.5: Proposed voltage reference with trimming circuitry
Fig.6.4 shows the variation of the ratio K10 /K0 w.r.t temperature in different process corners. It can
be seen that the ratio is fairly constant w.r.t temperature variations, implying that the variations in Vref
will be the same as Vbias . The approximations used while deriving the equation can be accounted for
the degradation in the ratio, which are not expected in the ideal case. The presence of the ratio term
provides more controllability on Vref . Although Vref will have the large process spread similar to Vbias ,
48
the spread can be reduced by adjusting the widths (and thereby the ratio K10 /K0 ) without degrading the
temperature coefficient. Fig.6.5 shows the trimming setup for calibration of Vref . The current reference
Iref is calibrated similar to that shown in Chapter 4. The switches used in the circuit are implemented
using thick oxide NMOS transistors to avoid additional degradations like gate-leakage current flowing
through the gates of switches. B0-B4 are the trim bits to calibrate the voltage reference.
6.2.2 Results and Discussion
Fig.6.6 shows the results for the voltage reference Vref w.r.t temperature after calibration in five
different corners. The observed typical and worst case accuracies are 36ppm/o C and 120ppm/o C
respectively. It can be observed that without much degradation in the temperature coefficient, Vref has
been trimmed. This cannot be possible for Vbias and two-point calibration should be employed in that
case. Fig.6.7 shows the line sensitivity of Vref in different corners after calibration. The observed
line sensitivities in all tt, all ss and all ff corners are 0.063%/V, 0.12%/V and 0.048%/V respectively
in a supply range of 1.5V - 4V. Fig.6.8 shows the PSRR of the voltage reference at different supply
voltages. A best PSRR of -74dB is achieved at 2.4V supply. At 1.5V, 1.8V, 3V and 3.6V, the observed
PSSRs are -61dB, -69dB, -65dB and -62dB respectively. The designed voltage reference has also been
statistically validated through Monte-Carlo simulations and the corresponding plot is shown in Fig.6.9.
For 500 runs (both process and mismatch), the observed mean and standard deviation for the TC of
Vref are 43.3858ppm/o C and 28.1ppm/o C respectively, with the maximum TC (considering ±3σ
variations) being 130ppm/o C. Fig.6.10 shows post-trim results for Iref similar to Fig.6.6, with the
typical and worst case accuracies being 20ppm/o C and 71ppm/o C. Fig.6.11 shows the post-trim line-
sensitivities for the current reference (Iref ) and the observed line sensitivities are 0.09%/V, 0.18%/V,
and 0.072%/V in all ss, all ff and all tt corners respectively. Monte-Carlo simulation results for Iref are
shown in Fig.6.12. The observed mean and standard deviations for the current reference are 28 ppm/C
and 14ppm/C respectively. The layout of the proposed voltage/current reference is depicted in Fig.6.13
from which the area is calculated to be 0.0005mm2 . Finally, Table 6.1 compares the proposed voltage
reference and current reference metrics with the state-of-the-art.
6.2.3 Summary of the first configuration
A sub-nW voltage/current reference is proposed in a single circuit by exploiting the characteristics

of gate-leakage current in accumulation region. The proposed architecture is a modification of that
discussed in Chapter 4 and retains all the advantages of the circuit like constant power consumption
w.r.t temperature, no start-up circuit and low area. The other metrics are also comparable to the state-
of-the-art and not compromised while retaining these advantages. However, it requires a slightly high
supply voltage of 1.5V due to the high value of voltage reference and headroom due to current mirror.
To reduce the voltage headroom, a new architecture is proposed in the next section.
49
Figure 6.6: Post-trim results for Vref w.r.t temperature in diff. corners
Figure 6.7: Post-trim results for line-sensitivity of Vref in diff. corners
Figure 6.8: PSRR of Vref at different supply voltages
50
Figure 6.9: Monte-Carlo Simulation result for TC of Vref
Figure 6.10: Post-trim results for Iref w.r.t temperature in diff. corners
51
Figure 6.11: Post-trim results for line-sensitivity of Iref in diff. corners
Figure 6.12: Monte-Carlo Simulation result for TC of Iref
Figure 6.13: Layout of the proposed Vref /Iref
52
Specifications This Work [23] [26] [72] [22] [34] [35]
Technology 55nm 130nm 180nm 180nm 180nm 65nm 130nm
Supply Range 1.4V-4V 0.5V-3.5V 0.9V-3.3V NA 1.2V-4V 0.4V-1.2V 0.7V-2.5V
Voltage (V)/Current (pA) 0.6/12.2 0.175/- 0.74/- 1.19/- -/20 -/1.2 -/3.2
Accuracy (ppm/o C) 43/88 (avg from MC runs) 19.4 (measured)/- 27 (measured mean)/- 24.7/- -/780 (measured) -/469.3 (measured) -/161 (measured)
Power (pW) @ tt, 1.4V & 27o C 51 81.2 31.4 2980 23 3.4 6
Power w.r.t temperature constant exponential exponential exponential exponential exponential exponential
Temperature Range (o C) -55 to 100 -20 to 80 0 to 170 -20 to 100 0 to 80 -20 to 60 0 to 85
Line sensitivity (%/V) 0.063/0.07 0.036/- 0.27/- 0.062/- -/0.58 -/2.5 -/0.62
PSRR (dB) near dc -69 -55 NA -62 -62 -62 -62
Area (mm2 ) 0.0009 0.00135 0.0076 0.98 0.048 0.008 0.00055
Table 6.1: Comparison With State-of-the-Art Architectures
6.3 Second Configuration

The proposed voltage/current reference is shown in Fig. 6.14. MN1 and MN2 are native oxide
devices whose usage do not incur additional masks in modern foundries [47]. MN3-MN6 and MP2-
MP5 are regular thick oxide NMOS and PMOS transistors respectively. MP1 and MP6-MP10 are thin
oxide PMOS devices in which a prominent leakage current in the order of fA to nA flows through their
gates. These gate-leakage transistors have been extensively used in the state-of-the-art ultra-low power
designs [9–14]. Bulks of the devices are shorted to their S/D terminals to avoid bulk currents, so PMOS
devices are used to avoid additional area.
6.3.1 4T voltage reference

Transistors MN1-MN3 and MP1 form the four-transistor (4T) voltage reference. The expression for
Vref 1 can be given by the difference between Vgs of MN3 and Vgs of MN2:
Vref 1 = Vgs3 − Vgs2 (6.9)
Here, Vgs2 is negative since the threshold voltage of MN2 is ∼ 0V and it operates in sub-threshold
region. This further implies that MP1 is in accumulation region as its gate (Vref 1 ) is at a higher potential
than its source (Vgs3 ). Accumulation-mode gate-leakage transistors have been previously used in the
literature and [10] derives a generalised expression for the gate-leakage current in accumulation region
:
Itot = KVsg1 (Vsg1 − Vf bsd ) (6.10)
K = 2∗ Wef f .(DLCIG).A.ToxRatioEdge .exp(−B.T OXE.P OXEDGE.AIGSD) (6.11)

kB T N GAT E
q N SD
53
Figure 6.14: Proposed Voltage/Current Reference
Here, Wef f is the effective width of the transistor, while DLCIG, A, ToxRatioEdge , B, TOXE, POXEDGE,
AIGSD, NGATE, NSD and VFBSDOFF are modelling constants [31], which are independent of temper-
ature variations. Vsg1 (for MP1) = −Vgs2 (for MN2), and the term Vf bsd can be neglected in comparison
to −Vgs2 as its only 6.67mV at 27o C. The expression for the 4T structure current now becomes :
Ibias = K(Vgs2 )2 (6.13)
It can be seen from eq.6.13 that Ibias is related to Vgs by square law and is dependent only on the
temperature coefficient of Vgs (K is independent of temperature). In the conventional pico-watt voltage
references, the expression for current contains various temperature dependent terms and varies exponen-
tially with temperature. Since Vgs2 is a CTAT voltage, Ibias becomes a PTAT current which increases
by only 2.7x from -55-100o C.
The expression for Vref 1 can be solved by equating the sub-threshold current equations in MN2 and
MN3 :

W2 2 VGS2 − Vth2
I = µ2 COX2 (m2 − 1)VT exp
L2 m2 VT

W3 2 VGS3 − Vth3
= µ3 COX3 (m3 − 1)VT exp (6.14)
L3 m3 VT
Note that TC of Vgs2 & Vgs3 get adjusted such that the overall current varies by only 2.7x w.r.t tempera-
ture. m2 and m3 differ with an error of 5% and hence are considered equal to ‘m’ to avoid complications
in solving the equation. The final equation for Vref 1 can be derived similar to [9] :

µ2 Cox2 W2 L3
Vref 1 = Vth3 − Vth2 + mVT ln (6.15)
µ3 Cox3 W3 L2
54
Considering the TCs of Vth2 and Vth3 to be k2 and k3 respectively, (k2 > k3 ), the TC of Vref 1 can be
given by :
∂Vref 1 k µ2 Cox2 W2 L3
= k3 − k2 + m ln (6.16)
From eq.6.16, it can be deduced that by properly adjusting the aspect ratios of M2 and M3, a temperature
compensation can be achieved for Vref 1 . The transistor M1 is used for shielding the reference voltage
from supply variations, thereby improving the line sensitivity and the PSRR.
6.3.2 4T Vref with trimming and current reference

Due to the threshold voltage variations of MN2 and MN3 with process, the observed process spread
for Vref 1 is ±11%, while the temperature coefficient doesn’t degrade drastically (refer results section).
Reducing this process spread by trimming MN2 or MN3 would also result in accuracy degradation,
thereby necessitating two-point calibration or other sophisticated ways of trimming which can increase
the cost. This issue is alleviated by trimming Vref 1 using the ratio of widths of gate-leakage transistors
MP6 and MP7-MP10 as shown in Fig.6.14. Vref 1 is equalized at the drain of MP5 using a two stage
amplifier with differential amplifier as first stage, and transistors (MP4-MP5, MP6-MP10) forming a
common-source amplifier and acting as a second-stage. The loop gain is 60dB and a capacitance Cc
implemented using thick oxide NMOS is added as shown in Fig.6.14 for stability purposes. The dif-
ferential amplifier is biased from the PTAT current generated from 4T Vref structure and helps to avoid
any self-biased loops in the architecture. The desired voltage reference now becomes Vref instead of
Vref 1 , and is equal to 0.8*Vref 1 . Its process variations are trimmed by varying the effective width of
MP6 as shown in Fig.6.14, which in-turn varies the effective resistance ratio of MP6 to MP7-MP10.
Note that all the transistors MP6-MP10 have equal widths and lengths. Since the voltage across each of
MP6-MP10 equals Vref 1 /5, the expression for Iref can be given by :
2
Vref 1
Iref = K (6.17)
5
where the parameter K for all the transistors is equal. Since K is a temperature independent constant and
Vref 1 is temperature compensated by design, a current reference is also achieved in the same circuit.
The process variations in the current reference is trimmed by varying the effective widths of PMOS cur-
rent mirrors(as shown in Fig.6.14). The gate-leakage divider also provides different reference voltages
(Vref /4, Vref /2, 3Vref /4), making the voltage reference scalable.
6.3.3 Results and Discussion

The proposed voltage/current reference is implemented in 90nm technology. Fig.6.15(a) shows the
Monte-Carlo simulation result (process & mismatch, 1000 samples) for Vref 1 w.r.t temperature (in the
range of -55o C to 100 o C), from which a variation (± 3σ) of 21.82% can be observed. Since Vref is a
scaled down version of Vref 1 , its variation is also almost the same (21.92%) as seen from Fig.6.15(b).
55
Fig.6.16(a) shows the pre-trim MC simulation result (process & mismatch, 1000 samples) for the TC
of Vref . The observed mean and std.dev for the accuracy are 24.3ppm/o C and 4.05ppm/o C respec-
tively. From Fig.6.15(b) and Fig.6.16(a), it can be confirmed that only absolute value of Vref is more
susceptible to process & mismatch variations, while TC is observed to be fairly constant. This varia-
tion in absolute value can be trimmed by varying multipliers of MP6, as discussed in previous section.
Fig.6.16(b) shows the post-trim simulation results for Vref in all tt, all ss and all ff corners, with the
accuracies being 22ppm/o C, 42ppm/o C and 71ppm/o C respectively in a temperature range of -55o C to
100o C. It can be observed that a large process spread has been reduced without much degradation in the
TC.
Fig.6.17(a) shows pre-trim accuracies of Iref with random process and mismatch variations. Sim-
ilar to Vref , Iref TC (mean=104ppm/o C, std dev=14.9ppm/o C) is also fairly stable with process and
mismatch variations. However, to correct for the absolute value variation, multipliers of MP11 and
MP12 are varied as discussed in previous section. Post trim simulation of Iref show that the absolute
value of Iref can be brought within 2%, and the worst case TC is observed to be 78ppm/o C (ss corner,
Fig.6.17(b)). The line-sensitivities of Vref and Iref are shown in Fig.6.18(a) and Fig.6.18(b) respec-
tively in the typical corner and room temperature. In a supply range of 1V - 3V, the observed line sensi-
tivities are 0.029%/V and 0.059%/V for Vref and Iref respectively, which are quite low. The PSRRs at
DC for Vref at 1V, 2V and 3V supply voltages are observed to be -67dB, -98dB and -78dB respectively,
and are shown in Fig.6.19(a). The plot of current consumption w.r.t supply is shown in Fig.6.19(b),
from which it can be seen that the total current drawn by the circuitry increases by only 1.0006x times
in a supply range of 1V - 3V. As discussed in the previous section, the current in 4T Vref generator
is a PTAT and not exponential. The increment in the power consumption of 4T Vref is observed to be
only 2.7x w.r.t temperature (Fig.6.20(a)) while the overall circuit power consumption increases by only
2.1x w.r.t temperature (Fig.6.20(b)). The 99% settling times of Vref and Iref are observed to be 1.92ms
and 2.526ms respectively without any start-up circuit and the respective plots are shown in Fig.6.21(a)
and Fig.6.21(b). The layout of the proposed voltage/current reference is shown in Fig.6.22, from which
the area is calculated to 0.00157mm2 . Finally, Table 6.2 compares the specifications of the proposed
voltage/current reference with state-of-the-art references.
6.3.4 Summary of the second configuration

A pico-watt gate-leakage based voltage/current reference has been proposed without using any large
physical resistors, external signals or start-up circuits. A gate-leakage divider based trim methodology
proposed for uncomplicated trimming of the voltage reference also leads to current reference and further
makes the voltage reference scalable. The power consumption of the circuit increases by only 2.1x in
the operating temperature range and doesn’t blow up at higher temperatures. The absence of self-biased
loops eliminates the need for start-up circuits and reduces the start-up time.
56
Figure 6.15: ± 3σ variation of (a) Vref 1 and (b) Vref (MC)
Figure 6.16: (a) MC result for Vref TC (b) Vref post-trim results
57
Figure 6.17: (a) MC result for Iref TC (b) Iref post-trim results
Figure 6.18: Line-sensitivity of (a) Vref (b) Iref
58
Figure 6.19: (a) PSRR of Vref (b) Current w.r.t supply
Figure 6.20: Power consumption vs temp for (a) 4T Vref (b) total circuit
Figure 6.21: Start-up time for (a) Vref (b) Iref
59
Figure 6.22: Layout of the proposed voltage/current reference
Specifications This Work [42] [44] [56] [47] [? ] [10] [69] [70] [12] [13] [14]
Technology 90nm 180nm 180nm 180nm 130nm 180nm 65nm 130nm 180nm 65nm 65nm 40nm
Type Vref/Iref Vref/Iref Vref/Iref Vref/Iref Vref Vref Vref Vref Iref Iref Iref Iref
Vref (V) / Iref (pA) 0.53 / 43 1.2 / 51000 1.238 / 6640 0.368 / 9970 0.175 / - 0.74 / - 1.245 / - 0.56 / - - / 20 - / 1.2 -/5 - / 2.4
Temperature Range (o C) -55 to 100 -45 to 125 0 to 110 -40 to 125 -20 to 80 0 to 170 -40 to 100 -25 to 85 0 to 80 -20 to 60 0 to 100 0 to 85
TC (ppm/o C) 22 / 58 33 / 89 26 / 283 43 / 150 62 / - 27 / - 23 / - 18.4 / - - / 780 - / 469 - / 31 - / 19
Power Consumption 156pW 192nW 9.3nW 28nW 2.2pW 31.4pW 443pW 20pW 23pW 3.4pW 14.5pW 8.2pW
Power w.r.t temperature 2.1x ∼1.187x NA 1.017x ∼200x 23584x 2.338x ∼2.25x NA ∼30x NA NA
Start-up circuit Not used Used Used Used Not used Not used Used Used NA NA NA NA
Settling-time (ms) 1.92 / 2.526 NA NA NA 60 1040 78 NA NA 48 NA NA
Calibration 1-point 1-point 1-point 1-point 1-point None None 1-point 1-point 2-point 1-point 1-point
Supply Range 1V-3V 2V-5V 1.3V-1.8V 0.7V-2V 0.5V-3V 0.9V-3.3V 1.5V-3.8V 1V-3.3V 1.2V-4V 0.4V-1.2V 0.5V-1.8V 0.5V-2.5V
Line sensitivity (%/V) 0.029 / 0.059 0.058 / 1.76 0.08 / 1.16 0.027 / 0.6 0.033 / - 0.27 / - 0.063 / - 0.15 / - - / 0.58 - / 2.5 - / 0.95 - / 0.78
PSRR -77dB @ DC -85dB @100 -46dB @100 -65dB@DC -53dB@100 NA -65dB@DC -50dB@100 - - - -
Area (mm2 ) 0.00157 0.063 0.055 0.055 0.001 0.0076 0.009 0.003 0.048 0.008 0.000176 0.00025
Table 6.2: Comparison with State-of-the-Art Architectures
60
Chapter 7
A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power

Microsystems
7.1 Introduction
Ultra-low power wireless microsystems have demonstrated their feasibility in various IoT applica-
tions such as environmental monitoring, medical care and surveillance. These systems are often powered
by miniaturized batteries or energy harvesters, which limit their total power consumption to tens of µW .
Additionally, energy harvesters demand these systems to work for sub-1V supplies, while miniaturized
batteries demand usability in a wide supply range precluding the need for a voltage regulator. Tem-
perature sensors being an integral part of these systems, are desired to satisfy these demands. These
temperature sensors often use a proportional-to-absolute-temperature (PTAT) sensing element to trans-
duce the temperature to a voltage, which is then converted to a digital code. The overall system power
consumption pushes the power budget of the temperature sensor to less than 10nW. This further con-
strains the power budget of the PTAT sensing element to sub-nW levels. Apart from these constraints,
the PTAT sensing element is desired to be process-invariant to avoid multiple calibrations, thereby re-
ducing the cost.
The past few decades have witnessed various types of temperature sensors. Most of the conventional
temperature sensors incorporate Bipolar Junction Transistors (BJTs)[73–76] for generating a temper-
ature dependent voltage (usually a Proportional-To-Absolute-Temperature (PTAT)). This is done by
taking the difference between the base-emitter voltages (∆VBE ) of two vertical PNP transistors. Al-
though the obtained PTAT voltage is highly linear and process-invariant, the power consumption of the
PTAT generator is of the order of µW , which makes them unsuitable for ultra-low power microsystems.
Moreover, they do not work for lower supply voltages. As a result, MOSFET based temperature sen-
sors have been introduced [77–80] in which the subthreshold region of operation has been exploited to
generate PTAT voltages while consuming low power. Although the use of MOSFETs have facilitated
the working of circuits at lower supplies, the temperature dependent voltages show a significant devia-
tion w.r.t process variations (as in [77, 78]), demanding the need for one-point or two-point calibration
61
techniques. Moreover, the power consumption of the PTAT generators is still high for the targeted ap-
plications [81]. [79] and [80] use architectures which generate process independent PTAT voltages.
However, the architectures still consume nA currents and to scale down their current consumption to
pA, impractical resistances of the order of GΩs must be used. To alleviate these issues, novel pico-watt
PTAT sensing elements have been proposed in the literature [82–84]. Although these elements consume
power in the order of pW, they suffer from the effect of process variations as the PTAT voltages are a
function of threshold voltages of the transistors.
This chapter deals with a pico-watt BJT based temperature sensor that generates a process-invariant
PTAT voltage, thereby avoiding multi-point calibrations and reducing cost. The proposed sensor works
for a wide supply range of 0.7V-3V and consumes power in the sub-nW range, thereby facilitating its
usage with energy harvesters and miniaturized batteries. The rest of the chapter is organized as follows.
Section II discusses the circuit level implementation of the proposed sensor. Results are shown in section
III and conclusions are drawn in section IV.
Figure 7.1: Proposed Temperature Sensor
7.2 Design and Analysis of the Temperature Sensor
The proposed temperature sensor is shown in Fig. 7.1(a). T1 and T2 are vertical PNP transistors. M1,
M2 and M3 are regular thick oxide PMOS transistors while M4-M10 are thin oxide PMOS transistors.
These thin oxide devices are also known as gate-leakage transistors, as tunneling currents of the order
of fA to pA flow through the gate of these devices[85]. They can serve as effective replacements for GΩ
physical resistances due to their compact size and provision of sub-nA currents[53, 86, 87]. A single
stage differential amplifier (with 52dB open loop gain) has been used to ensure the negative feedback in
the loop (shown in Fig.7.1(b)). It is biased by a beta-multiplier circuit in which the physical resistance
62
is replaced by a gate-leakage transistor to ensure sub-nW power consumption. A start-up circuit [49]
has been used for the feedback loop and beta-multiplier (as shown in Fig.7.1) to avoid degenerate bias
points in the temperature sensor.
7.2.1 Core of the temperature sensor

The voltage VP T AT 1 at the gate of transistor M4 is given by the difference between the base-emitter
voltages of PNP transistors T1 and T2:
VP T AT 1 = VEB1 − VEB2 (7.1)
Considering the I-V relationship of a BJT, equation 7.1 can be re-written as :

I01 I02
VP T AT 1 = VT ln − VT ln (7.2)
IS1 IS2
Here, transistor T2 consists of n1 parallel units, each identical to T1 and current in T1 is n2 times that
in T2. This implies that I01 = n1 I02 and IS2 = n2 IS1 , which upon substitution in equation 7.2 leads to
equation 7.3:
VP T AT 1 = VT ln(n) (7.3)
where n = n1 ∗ n2 . The slope of VP T AT 1 is equal to (k/q)ln(n) and to achieve higher slope values,
n must be impractically large [88]. For acceptable values of n (in this case, n is chosen to be 20), the
PTAT voltage must be amplified in order to obtain higher slope values and thereby higher sensitivity to
temperature. Since gate-leakage transistors can be visualized as resistances, the amplified voltage can
be achieved by multiplying VP T AT 1 by a factor equal to the ratio of equivalent resistance of the series
combination of M5-M10 and resistance of M4. This is done as shown in Fig.7.1 where the expression
for the amplified voltage VP T AT 2 is given by :
R2
VP T AT 2 = (VT ln(n)) (7.4)
R1
where R1 is resistance of M4 and R2 is the equivalent resistance of the series combination of M5-
M10. The aspect ratio of M4 is set in order to achieve a desired bias current of 80pA in M2 and M3.
Transistors M5-M10 are replicated versions of M4 with all of them having same aspect ratios as that of
M4. Since same current is made to flow through M4 and the stack M5-M10, by symmetry arguments it
can be concluded that R2 = 6R1. Hence, VP T AT 2 is an upscaled version of VP T AT 1 by a factor of 6.
Considering the trade-off between area and power consumption, the values of n1 and n2 are chosen to
be 4 and 5 respectively. With these values, the slope of VP T AT 1 turns out to be 260µV /o C, which on
upscaling by a factor of 6 gives a slope of 1.56mV /o C for VP T AT 2 . The slope of VP T AT 2 can further
be amplified by adding more replicas of M4 to the series combination of M5-M10 with the trade-off of
area occupancy.
Although gate-leakage transistors can be visualized as resistances, the tunneling currents show a
significant variation w.r.t temperature depending upon the gate-source voltage[89]. From equation 7.4,
63
it can be seen that for VP T AT 2 to be an exact upscaled version of VP T AT 1 without any degradation in
its linearity, the ratio R2/R1 must be temperature and process invariant. This is theoretically true owing
to the symmetry arguments (voltage across each transistor from M5-M10 equals VP T AT 1 ). To validate
this argument, the ratio R2/R1 is simulated w.r.t temperature across different process corners and also
verified statistically through monte-carlo simulations. The results for these are shown in section 7.3.
Once R2/R1 becomes temperature and process invariant, VP T AT 2 inherits only the temperature and
process variation of the term VEB1 − VEB2 . Since the difference of base emitter voltages is highly
linear and independent of process variations, VP T AT 2 becomes a highly linear process-invariant PTAT
voltage.
7.2.2 Beta-multiplier using gate-leakage
Figure 7.2: Conventional beta-multiplier
Fig. 7.2 shows the standard architecture of beta-multiplier. Considering the transistors M1 and M2
to be operating in sub-threshold region, we can express their current equations as :

(VGS1 − VT H1 ) −VDS1
I1 = I2 = Is (W/L)1 exp 1 − exp =
(ηkT /q)) VT

(VGS2 − VT H2 ) −VDS2
Is (W/L)2 exp 1 − exp (7.5)
(ηkT /q)) VT
64
Here, IS is the weak inversion characteristic current given by :
Is = µn Cox (η − 1)VT2 (7.6)
VT is the thermal voltage equal to kT/q, η is the subthreshold slope factor in weak inversion (typically
1.3), and VT H is the threshold voltage. VDS is kept greater than kT/q so that the dependency of sub-
threshold current on VDS can be ignored.
It can be seen that the voltage across the resistor is VGS1 − VGS2 and from equation 7.5, we get :

ηkT (W/L)2
VR = VGS1 − VGS2 = ln + (VT H1 − VT H2 ) (7.7)
q (W/L)1
Transistor M1 doesn’t have body effect and has a nominal threshold voltage (VT H0 ), but M2 suffers
from body effect and, consequently, its threshold voltage is given by:
p p
VT H2 = VT H0 + γ 2φF + VSB − 2φF (7.8)
where φF is the fermi potential and γ is the body factor coefficient. VSB is equal to VR . Considering
√
VR << 2φF , we can use binomial expansion to approximate the term 2φF + VSB as :
p p VR
2φF + VR = 2φF + √ (7.9)
2 2φF
From equations 7.8 and 7.9, we can simplify eq.7.7 as :

(W/L)2
η(kT /q)ln (W/L)1
VR = γ (7.10)
1+ √
2 2φF
From [4], we have :

γ
1+ √ =η (7.11)
2 2φF
Hence, the final expression for VR becomes :

kT (W/L)2
VR = ln (7.12)
q (W/L)1
It can be seen from eq.7.12 that voltage across the beta-multiplier is a PTAT voltage. By using a re-
sistance with zero temperature coefficient, we can get a PTAT current (since I = VP T AT /R), which
can be used to bias the op-amp. However, for pico-ampere currents, an impractically large resistance
(∼ GΩs) is required to generate the bias current. To avoid the blow up in the area, we use gate-leakage
transistor which are available in lower technology nodes. A PMOS thin-oxide transistor is used so that
it is operated in accumulation region of operation. From Chapter 5, we already know the approximate
equation for gate-leakage current equation in accumulation region.
Itot = KVsg (Vsg − Vf bsd ) (7.13)
65
where K = k1 .exp(−k2 .AIGSD).
k1 = 2∗ Wef f .(DLCIG).A.ToxRatioEdge and k2 = B.(T OXE).(P OXEDGE). Here, Wef f is the
effective width of the transistor and DLCIG, A, ToxRatioEdge , B, TOXE, and POXEDGE are modelling
constants for a given technology which are independent of temperature. Vf bsd is the flat-band voltage
between gate and S/D diffusions calculated by the below expression :

kB T N GAT E
q N SD
Again, NGATE, NSD and VFBSDOFF are modelling constants whose values are mentioned previously.
Since the voltage across the gate-leakage transistor M15 (VR ) is given by VT ln(n) (eq.7.12) where
n = (W/L)2 /(W/L)1 , the current equation in the beta-multiplier architecture can be given by :
Itot = K1 VT ln(n)(VT ln(n) + Vf bsd ) (7.15)
where K1 is a function of effective width Wef f of M11. Eq.7.15 shows that the current in beta-multiplier
is a PTAT and follows square-law. This current can be used to bias the op-amp in the temperature sensor.

The temperature sensor is implemented in UMC 65nm technology. Fig.7.3 shows the ratio R2/R1
w.r.t temperature in typical and worst case corners while Fig.7.4 shows the Monte-Carlo simulations
results (both process and mismatch) for R2/R1 at 27o C. It can be seen from both these graphs that the
maximum error in R2/R1 due to temperature variation is 0.59% and that due to process and mismatch
variations (±3σ) is 0.8%. These errors are negligible, showing that the ratio R2/R1 is temperature and
process invariant. This justifies that VP T AT 2 inherits the linearity and process invariance of VP T AT 1 as
explained in section 7.2. Fig.7.5 shows the variation of VP T AT 2 w.r.t temperature in different corners
while Fig.7.6 shows the non-linearity error w.r.t temperature in typical and worst case corners. The
maximum non-linearity error is observed to be 0.025% (translates to 0.12o C) which indicates that the
temperature sensor is highly linear. Without any calibration, the deviations in the worst case corners
from the typical value are +0.1%/-0.5% (+0.36o C/−1.61o C). To further validate the process invariance
claim, monte-carlo simulations are run (both process and mismatch) for the slope of VP T AT 2 at 27o C
(shown in Fig.7.7). From the reported mean and standard deviations, it can be seen that the maximum
inaccuracy (±3σ) in the slope of the temperature sensor due to process and mismatch variations is 2.4%.
All the results from Fig.7.3 to Fig.7.7 depict that the temperature sensor is highly linear and process
invariant. Fig.7.8 shows the line sensitivity of the temperature sensor in different process corners. An
excellent line sensitivity of 0.56o C/V is achieved in a wide supply range of 0.7V-3V. Fig.7.9 shows the
start-up time of the temperature sensor, which is observed to be 15ms (considering that it has reached
95% of its steady state value). The reported start-up time is quite high, but comparable to the state-of-
the-art pico-watt self-biased circuits [53]. Fig. 7.10 shows the layout of the proposed temperature sensor
66
from which the area is calculated to be 0.005mm2 . Finally, Table 7.1 compares the state-of-the-art and
proposed sensor.
7.4 Conclusion
A sub-nW BJT based temperature sensor has been proposed which inherits the advantages of BJT
based PTAT voltage generation for process invariant nature and gate-leakage transistors for pico-watt
power consumption. The sensor is suitable for ultra-low power microsystems owing to its low area and
low power consumption. The sensor is based on amplifying the difference between base-emitter voltages
of BJTs using gate-leakage transistors, which is process-invariant. The claims of process-independent
nature of the temperature sensor are proven by various monte-carlo simulations. Implemented in UMC
65nm technology, the sensor occupies an area of 0.005mm2 . It achieves a maximum non-linearity error
of 0.12o C(3σ) over the temperature range of −55o C to 80o C. Without any trimming, a worst case
inaccuracy of +0.36o C/ − 1.61o C is observed w.r.t process variations, depicting the process-invariant
nature of the temperature sensor. Apart from being process invariant, the sensor works for a wide
supply range of 0.7V-3V, achieving a low supply sensitivity of 0.56o C/V . The power consumption of
the sensor is 419pW at 27o C and 0.7V supply.
Figure 7.3: R2/R1 w.r.t temperature across different corners
67
Figure 7.4: Monte-Carlo simulation for R2/R1
Figure 7.5: VP T AT 2 in different process corners
68
Figure 7.6: % non-linearity in different process corners
Figure 7.7: MC simulation for slope of VP T AT 2
69
Figure 7.8: Line sensitivity of VP T AT 2 in diff. corners
Figure 7.9: Start-up time
70
Figure 7.10: Layout of the proposed temperature sensor
Specifications This Work [73] [74] [79] [80] [? ] [? ]
Technology 65nm 160nm 160nm 180nm 180nm 180nm 65nm
PTAT Generation BJT BJT BJT CMOS CMOS CMOS CMOS
Fully Integrated No Yes Yes No No Yes Yes
Temperature Range (o C) -55 to 80 -55 to 125 -30 to 125 -55 to 125 -55 to 125 0 to 100 -20 to 40
Sensing Accuracy1 (3σ) +0.1o C/ − 0.02o C NA NA ±0.4o C ±0.4o C NA NA
Process Spread (3σ) +0.36o C/ − 1.61o C ±0.6o C/ ± 0.15o C ±0.2o C ±0.6o C NA +1.5o C/ − 1.4o C ±1.93o C
Calibration No Untrimmed/1-point 1-point No 1-point 2-point NA
Supply Range 0.7V-3V 1.5V-2V 1.6V-2V 1.1V-3.5V 0.7V-3.6V 1V-1.4V NA
Line sensitivity 0.56o C/V 0.5o C/V 0.1o C/V 0.11%/V 0.23o C/V 11.25o C/V NA
Power Consumption2 419pW 5.1uW 7.36uW 108uW 47nW 71nW 113pW
Area (mm2 ) 0.005 0.08 0.12 0.002 0.82 0.09 0.15
1 Sensing Accuracy - error due to non-linearity in sensing

2 Power Consumption calculated at least supply voltage
Table 7.1: COMPARISON WITH STATE-OF-THE-ART ARCHITECTURES
71
Chapter 8
Highly Supply Invariant Current/Voltage Reference and Temperature

sensor
8.1 Introduction
The enhanced capability of the smart devices in connecting to the internet has led to the ever-
increasing demand for the deployment of low-power IoT systems in various applications such as biomed-
ical, environmental monitoring and surveillance. Thin-film batteries with miniaturized size and large
internal resistances, often power these systems. The miniaturized size results in limited energy ca-
pacity which puts the average power consumption of the system as the bottleneck. The large internal
resistance limits the maximum instantaneous current that can be drawn from the battery. Addition-
ally, for very long life time in certain applications, these systems are desired to be powered by energy
harvesters that often give lower supply voltages. Hence, these systems are also desired to work for
lower supply voltages. Process, supply and temperature stabilized voltage and current references are
essential to any analog circuit design. The desired temperature characteristic may be either constant
with temperature (C.W.T), proportional to absolute temperature (PTAT) or complementary to absolute
temperature (CTAT) depending upon the desired application. Supply insenstivity of these references
are usually improved by either ‘cascoding’ or ‘using op-amp in negative feedback’. While cascoding
is not a favourable technique for low supply voltages (especially sub-1V), op-amp based architectures
incur additional design complexities in terms of power, bandwidth and noise [90], [91]. To avoid these
complications for achieving high supply insensitivity, we analyze the structure proposed in [92], which
achieves high PSRR without using op-amps or cascoding. We analyze this structure as a circuit that
mimics the characteristics of an op-amp with much reduced design complexity. We hereafter refer this
structure as ‘Asymmetric Op-amp’, for reasons to be discussed later. The structure proposed in [92]
discusses its advantage only in achieving high PSRR. In this chapter, we use this asymmetric op-amp to
propose voltage reference, current reference and temperature sensor which are highly supply invariant
and have excellent temperature stabilities.
72
8.2 The Asymmetric Op-Amp Architecture
Fig. 8.1(a) & 8.1(b) shows the conventional two stage op-amp and the proposed asymmetric op-
amp respectively. Assuming all the transistors to be operating in saturation region, the common source
amplifiers with resistive and active loads act as gain stages for the asymmetric opamp. C2 is a com-
pensation capacitor and is used for achieving stability. A closer look at the input-output characteristics
of conventional and asymmetric op-amps (as shown in Fig.8.1(c)) reveals that their characteristics are
similar except that the output transition points are different (0 and Vf inite respectively). i.e conventional
op-amps are desired to have zero offset, while the asymmetric op-amp is desired to have non-zero well
designed offset. This indicates that asymmetric voltages have to be applied at the inputs for biasing the
proposed op-amp and hence it has been named “asymmetric op-amp". Considering the positive terminal
(Fig. 8.1(b)) to be the supply voltage, the negative terminal must follow the positive terminal for any
noise overriding the supply so that a supply independent current flows through the resistor to generate
a supply independent voltage . Hence, the op-amp is connected in unity gain feedback as shown in
Fig. 8.1(d). ISI and VSI denote the supply independent current and voltage respectively. Note that the
number of gain stages in the asymmetric op-amp should be odd to ensure the negative feedback. Using
this op-amp architecture, current/voltage reference and voltage reference/temperature sensor circuits are
proposed.
8.3 Proposed Current and Voltage Reference
The architecture in Fig.8.1(d) can itself be visualized as a current reference. It is depicted along with
a start-up circuit in Fig. 8.2(a). The expression for current in the circuit is given by I = VGS1 /R and
assuming all the transistors to be operating in saturation region, VGS1 can be expressed as :
s
2ID
VGS1 = Vth1 + (8.1)
µn Cox (W1 /L1 )
where Vth and µn have temperature dependencies given by
3
T0 2
Vth1 = Vth10 − k1 T, µn = µ0 (8.2)
T
To obtain a temperature compensated current reference, a CTAT resistance is chosen and its tem-
perature coefficient is cancelled out by making VGS1 a CTAT voltage. From equations 8.1 and 8.2, it
can be inferred that by properly adjusting the aspect ratio of M1, a CTAT voltage of desired slope can
be achieved to cancel out the temperature dependency of the resistor. The same circuit can also be de-
signed as voltage reference by cancelling temperature dependencies of threshold voltage and mobility
in equation 8.1.
73
Figure 8.1: Comparison between conventional and asymmetric op-amps
8.4 Proposed Voltage Reference/Temperature Sensor

Fig. 8.2(b) shows the modified version of asymmetric op-amp by replacing a resistance with the
series combination of a diode (M1) and a resistance (R1). This reduces the voltage across the resistance,
thereby scaling down the power consumption and reducing area. Using this modified architecture, a
voltage reference and a temperature sensor are proposed in the same circuit. The mathematical expres-
sion for Vref is given as :
VGS2 − VGS1
Vref = R2 + VGS5 (8.3)
R1
All the transistors are biased with 100nA currents and accordingly, M 5 operates in the saturation
region while rest of them operate in the sub-threshold region depending on their aspect ratios. The
current through transistor M1, M2 is given by well known sub-threshold equation [32].

W 2 VGS − Vth −VDS
I = µn COX (m − 1)VT exp 1 − exp (8.4)
L mVT VT
Where µn is the mobility, Cox is oxide capacitance and m is sub-threshold slope factor. The dependence
of Vds on sub-threshold current is ignored with the assumption Vds > 4VT .
74
Figure 8.2: Proposed Voltage Reference, Current Reference and Temperature Sensor based on
asymmetric op-amp
Equating the currents in M1, M2 and simplifying further, we get:

kT W1 /L1
VGS2 − VGS1 = Vth2 − Vth1 + m ln (8.5)
q W2 /L2
Using the above result, the expression for Vref can be further simplified as a sum of two terms ’A’ and
’B’ (Vref = A + B) which have dominantly CTAT and PTAT temperature dependencies respectively.
The expressions for ’A’ and ’B’ are given by :
R2
A = (Vth2 − Vth1 ) + Vth5 (8.6)
R1
s
kT W1 /L1 R2 2ID
B = m ln + (8.7)
q W2 /L2 R1 µn Cox (W5 /L5 )
75
It can be seen from above equations that by properly adjusting the aspect ratios of M1, M2 and M5,
a temperature compensated voltage reference can be obtained. The temperature sensor can also be
visualised in the same architecture by generating a PTAT voltage (VP T AT ). The expression for VP T AT
can be obtained by equating currents through M3 and M4 . The detailed expression for VP T AT is derived
in [93], [94] and the final result is included here.

kT W4 /L4
VP T AT = ln (8.8)
q W3 /L3
From eq. 8.8, It is evident that VP T AT is independent of threshold voltages of M3 and M4 , which are
major sources of process variation. Hence, less process spread can be achieved for VP T AT .
8.5 Results
A total of five blocks are designed using the simple and modified asymmetric op-amp architectures in
TSMC 180nm techonology. Of these five blocks, 100nA, 10uA current references and a 625mV voltage
reference are based on simple asymmetric op-amp architecture (hereby referred to as ’Architecture - 1’).
The remaining two blocks are a 600mV voltage reference and a temperature sensor, which are based on
modified asymmetric op-amp architecture (referred to as ’Architecture - 2’). Fig.8.3 and Fig.8.4 display
the accuracies w.r.t temperature for the current and voltage references based on both the architectures.
As seen from the figures, the references are highly accurate w.r.t temperature in the worst case process
corners even without any trimming, which depicts their excellent temperature stabilities in different
process corners. Fig.8.5 shows the temperature sensor and its non-linearity variation w.r.t temperature
in different process corners. A maximum non-linearity of 0.2% is observed for the temperature sensor.
Fig.8.6 depicts the PSNRs of voltage references and the temperature sensor while Fig.8.7 shows the line
sensitivities of all the five blocks. As the figures indicate, the strong negative feedback of the asymmetric
op-amp helps in rejecting the supply noise to a large extent and also makes the circuit insensitive to its
operation at different supply voltages from 0.8V - 4V. Statistical performances of all the five blocks are
validated through Monte-Carlo simulations for both process and mismatch. The simulation is run for
accuracies w.r.t temperature (in ppm/o C) for the current and voltage references, and slope (in uV /o C)
for the temperature sensor (refer Fig. 8.8). All the results depicted from Fig.8.4 - Fig.8.8 have been
summarized in Table - I.
8.6 Conclusion
A novel architecture which mimics the negative feedback of a conventional op-amp has been an-
alyzed and named as "asymmetric op-amp". It has been named so because unequal voltages have to
be applied at is terminals unlike the conventional op-amp. Due to its strong negative feedback, a high
supply noise rejection is achieved without using any cascoding techniques or sophisticated op-amps.
76
Using this architecture, two current references and a voltage reference have been proposed having high
PSNR and excellent temperature stabilities. To further reduce the area occupancy while scaling down
the power consumption, the asymmetric op-amp has been slightly modified and used for designing a
voltage reference and a temperature sensor as a single block without any degradation in specifications
compared to the previous architecture.
Figure 8.3: 100nA and 10uA current references in different process corners
77
Figure 8.4: Arch - 1 and Arch - 2 voltage references in different process corners
78
Figure 8.5: Temperature Sensor and its % non-linearity in different process corners
79
Figure 8.6: PSNRs of voltage references and temp sensor
Figure 8.7: Line Sensitivities of the five blocks
80
Figure 8.8: Monte-Carlo Simulation for the five blocks
81
Chapter 9
A 180o Phase Shift Biasing Based High PSRR Technique in Low-Power

Temperature Sensors
9.1 Introduction
In modern semiconductor technologies, SoC (system-on-chip) designs, ultra low power circuits such
as implantable medical devices, energy harvesting based wireless sensor nodes have analog and digital
building blocks embedded on the same die. Together with high switching digital circuit, switched
capacitor and noisy RF circuit, noise may override the power supply and therefore power supply fails
to provide a constant supply voltage. This supply noise distorts the output node of analog blocks [95]
which significantly decreases the performance of whole SoC, especially in high precision systems.
A typical method for providing clean power supply is using the low dropout voltage regulator (LDO)
[96]. An LDO requires an op-amp having high open loop gain and a large bandwidth to achieve high
PSRR over a wide frequency range. However, using such an op-amp will increase the power dissipation
and silicon area.
Another method for achieving supply insensitive output is to design a circuit which itself rejects the
supply noise. In analog circuits, three techniques are frequently used to achieve high PSRR [97]. a)
Long channel transistor and Cascoding technique which decreases the gain of supply variation on the
output node. b) Negative feedback technique which considerably improves PSRR. It is further divided
into two, 1) with op-amp, which ensures that output follows the input and reject any other external
disturbance and 2) without op-amp, which needs a high gain feedback loop to nullify the effect of
supply variation. c) An additional circuitry which provides a negative gain path from the Vdd to the
output node to restrict the noise of power supply.
Temperature sensors, voltage and current references are the key building blocks used in analog,
mixed-signal and RF designs. Negative feedback technique is often employed in these circuits to obtain
high PSRR. Applications of low power, supply insensitive references are found in portable systems,
energy harvesters, implantable medical IoT [98, 99], etc. Supply insensitive temperature sensors find
82
application in instrumentation and control systems, microprocessor heat monitoring, military and space
applications, smart sensor network, etc[100, 101].
Considering the high supply rejection constraint, many temperature sensors, voltage and current
references are proposed in the literature. Voltage reference (VR) in [102] uses long channel transistors
and achieves PSRR of -82dB with the disadvantage of a high supply voltage of 4.25V. VR presented in
[103] uses cascoding technique with an extra op-amp to achieve PSRR of -85dB and consumes a power
of 86µW. Many references require an additional amplifier to make output more immune to supply noise
[104–108] and achieve maximum PSRR of -110dB. Similarly, the temperature sensors presented in
[109–111] can achieve maximum PSRR of -70dB and consume power in tens to hundreds of µW.
For low power applications, Composite pair [112, 113] is the most common choice to generate a
highly linear PTAT or CTAT voltage which is used in temperature sensors, current and voltage ref-
erences. Many low power temperature sensors and references presented in [105–109, 114–117] use
composite pair or BJT for robust linear PTAT/CTAT voltage generation. Temperature sensors and Ref-
erences presented in [105–109, 114–116] use composite pair and consume very low power.
References in [105–107] achieve PSRR from -70dB to -100dB but use additional op-amp. Refer-
ences in [108, 114–116] are self regulating circuits but can only achieve a PSRR from -50dB to -80dB.
Similarly, a low power temperature sensor presented in [118] achieves max. PSRR of -70dB. Note that
the PSRR reported in papers are at a fixed temperature, it can simply decrease by -20dB to -30dB at
extreme temperatures (-55o C or 125o C). Therefore, a high PSRR is required to compensate supply noise
for a temp. range of -55o C to 125o C.
The circuit in this chapter uses an NMOS transistor to obtain supply independent current in the
composite pair. In addition, a 180o phase shift technique is introduced at the gate of NMOS transistor
to obtain a high PSRR which cannot be achieved by the conventional circuits having a PMOS transistor
or an NMOS transistor with 0o phase shift. The temperature sensor biased using the 180o phase shift
technique can conveniently attain PSRR from -80dB to -100dB. The technique achieves high supply
noise rejection and does not require extra circuitry, i.e Op-amp or LDO. Therefore it is area and power
efficient. To prove the concept, a CMOS-only temperature sensor consuming 6µW power is designed
which achieves a PSRR of -80dB ±1.5dB over 3σ variation in process and mismatch.
9.2 Methodology
The proposed technique is based on introducing 180o phase shift biasing (w.r.t supply voltage) at
the gate of NMOS transistor to get a supply independent current in the composite pair. Conventional
biasing uses a PMOS [105, 106, 115, 116] or an NMOS [108, 109] transistor with 0o phase shift voltage
biasing. The maximum PSRR that can be achieved at the output of temperature sensor using this con-
ventional biasing is -70dB to -80dB (with the constraint of requiring very high PSRR at the bias voltage,
as explained in section 2.B). The 180o phase shift technique can easily achieve the PSRR of -80dB (or
greater) at the output of the composite pair without the need of any complex designing or extra circuitry.
83
It can be applied to any voltage/current reference or PTAT/CTAT voltage reference (temperature sensor)
which uses composite pair [105–109, 114–116]. To understand this technique first, the basic working
of the composite pair and its behaviour with supply voltage is explained in section 9.2.1. Then, con-
ventional and the proposed supply rejection technique are explained in Section 9.2.2 and Section 9.2.3
respectively.
9.2.1 Composite Transistor Pair

Composite pair [112] is the connection of two MOS transistors in cascode whose gates are coupled
to the same potential (Fig. 9.1(a)). A self-biased composite pair connected with supply independent
current is shown Fig. 9.1(b). This configuration will provide high supply rejection at output (VP T AT )
because of the constant current with respect to supply. This supply independent current can be obtained
by using either a PMOS transistor or an NMOS transistor (Fig. 9.1(c) and Fig. 9.1(d)). The composite
pair outputs a linear PTAT voltage when both the transistors are in sub-threshold region (explained and
proved in [112, 113]). Therefore, the supply insensitive current used to bias the self-biased composite
pair must be of the order of nano-amperes to ensure that the transistors are operating in the sub-threshold
region. Thus, it is an ultra-low-power circuit having a high output impedance. It can be used for two ap-
plications, a) Current mirror, because of having a very high output impedance and b) An ultra low power
temperature sensor because the resultant output is linear PTAT voltage [113]. Hence, the composite pair
is used to generate highly linear PTAT voltage for low power temperature sensing applications[109, 113]
and in voltage references to cancel PTAT and CTAT voltages[108, 114–116].
The functioning of the composite pair in self-biasing configuration is discussed in two parts, PTAT
voltage generation and its supply rejection. The basic working of the composite pair as PTAT voltage
generator is described as follows. The transistors MCP 1 and MCP 2 are biased with a supply independent
current I0 (as shown in Fig.9.1(b)). Considering the sub-threshold operation of the transistors MCP 1
and MCP 2 , a process invariant PTAT voltage (VP T AT ) is obtained. The mathematical justification for
this is given in [113], and the direct result is shown here.

KT (W1 /L1 )
VP T AT = ln (9.1)
q (W2 /L2 )
Where W1 /L1 and W2 /L2 are the geometric aspect ratio of MCP 1 and MCP 2 respectively.
From equation 9.1, VP T AT is independent of the threshold voltages of MCP 1 and MCP 2 which are
a major source of process variation. Further, the dependence of VP T AT on the ratio of W1 /L1 and
W2 /L2 is logarithmic and hence VP T AT can be considered almost process invariant. Also note that
VP T AT has very less dependence on the current in the composite pair. So the current can vary with
temperature and will not disturb linear characteristic of VP T AT as long as the transistors are operating
in the sub-threshold region. The temperature coefficient (TC) of VP T AT (α) is given as:

dVP T AT K (W1 /L1 )
α= = ln (9.2)
dT q (W2 /L2 )
84
Figure 9.1: (a) Basic Composite Pair, (b) Self biased Composite Pair with supply insensitive current,
(c) Composite Pair biased with PMOS current source, (d) Composite Pair biased with NMOS current
source
85
From equation 9.2, it can be observed that the TC of VP T AT can be adjusted by changing the aspect
ratio of the composite pair. Therefore, a process invariant temperature sensor with an application-
specific slope can be achieved by using the composite pair.
The supply rejection of the composite can be understood as follows. The current in the MCP 1 and
MCP 2 must be supply independent so that the output voltage VP T AT is also supply insensitive. This
supply independent current is generated from a PMOS or an NMOS transistor which are biased with
Vbias . In the case of the PMOS transistor (Fig. 9.1(c)), if the supply changes by some amount, Vbias
should also change by the same amount so that the gate-source voltage of PMOS transistor remains
constant, thereby getting a constant current with supply. Thus, the SIVB circuit should generate a
highly supply insensitive current so that it can be mirrored into the composite pair. In the case of NMOS
transistor (Fig. 9.1(d)), Vbias shouldn’t change with supply so that the gate to source voltage of MN M OS
remains constant, hence current in MN M OS , MCP 1 & MCP 2 also remains constant. So for both the
cases, a supply independent biasing circuit with high PSRR is required to get a high supply rejection at
the output of composite pair.
9.2.2 Conventional Supply Rejection Technique

As mentioned earlier, for a supply independent VP T AT , the composite pair should be biased with
a supply independent current. It can be done using an NMOS or a PMOS transistor. In conventional
biasing circuits, the phase difference between Vbias and Vdd is 0o i.e. if Vdd increases by ∆V due to
some noise, then the gate voltage Vbias must also increase. For PMOS transistor the gate voltage will
|P SRR|
increase by same ∆V and for NMOS the gate will increase by ∆V/AP SRR , where AP SRR = 10 20
and PSRR is the supply rejection ratio of the biasing circuit. As AP SRR should be very high, change
at the gate of NMOS transistor is very small i.e. current remains insensitive to supply. The NMOS
current transistor is chosen over PMOS as the NMOS topology gives much better supply insensitive
current than the PMOS topology. It is because the VGS of NMOS transistor is independent of the supply
connection (i.e. drain) and for large lengths of the transistor (reducing channel length effect), current is
independent of the drain voltage (i.e. supply voltage).
Fig. 9.2 shows the composite pair with NMOS topology [109] where the gate of the transistor M0
is biased with voltage Vbias . This Vbias is obtained from a conventional supply independent voltage
biasing (SIVB) circuit which gives a high PSRR with 0o phase shift. Now, to understand the limitation
of conventional 0o phase shift, consider the current equation of the NMOS transistor M0 operating in
sub-threshold region [119]:

VGS − VT H + ηVDS −VDS
IM 0 = Is .exp 1 − exp (9.3)
n.VT VT
Where Is = µn Cox (W/L)(n − 1)VT2 , n = sub-threshold slope factor = (1 + [CD /Cox ]), η = linearized
drain-induced barrier lowering (DIBL) coefficient and VT = thermal voltage = kT/q. In self-biased
composite pair, transistor M0 has VDS = 0.8V to 1V and VT = 0.025V at room temperature.
86
Figure 9.2: Block diagram of conventional biasing technique (Vbias ) to generate supply independent
PTAT voltage
As VDS >> VT , (1-exp[-VDS /VT ]) ≈ 1. Then, eqn 9.3 can be rewritten as:

VGS − VT H + ηVDS
IM 0 = Is .exp (9.4)
n.VT
Here VGS = Vbias - VS and VDS = Vdd - VS . As supply increases by ∆V, VDS increases ∆V and VGS
increases by ∆V/AP SRR due to the 0o phase shift biasing. Since both these terms increase, current in
transistor M0 increases which can be clearly understood from equation 9.4. Now, to decrease the effect
of supply on the current, the effect of supply on VGS must be decreased (the effect of VDS is neglected
due to the small factor η). In other words, ∆V/AP SRR should be very small which further implies that
AP SRR must be very high.
87
Figure 9.3: VP T AT PSRR (composite pair) vs Vbias PSRR (0o phase SIVB)
The above concept is proved in the Fig.9.3 where the effect of PSRR of Vbias (conventional SIVB)
on the PSRR of VP T AT (composite pair) is plotted. The graph is plotted for LM 0 = 4µm and the
maximum PSRR achieved at the output is -80dB. This PSRR can further be increased by choosing
the larger length of the transistor M0 . The graph also shows that the minimum PSRR of SIVB circuit
required to achieve the maximum PSRR of VP T AT is around -110dB. Considering the effect of process
and mismatch variations on the PSRR of SIVB circuit, the SIVB circuit should be designed for a PSRR
much greater than -110dB so that PSRR of VP T AT must remain at -80dB. This requires a high supply
insensitive biasing circuit which is difficult to design.
9.2.3 Proposed Supply Rejection Technique
The proposed biasing technique is exactly opposite from the conventional biasing in-terms of phase
i.e. composite pair with NMOS transistor should be biased with 180o phase shift. This 180o phase shift
concept can be understood using the current eqn 9.4. The current in the transistor M0 can be constant
only if the change in VDS due to supply is compensated by the counter change in VGS due to Vbias . In
other words, if VDS increases, VGS must decrease in order to keep the current constant. Therefore, a
180o phase shift biasing is required to compensate the supply variation at the output VP T AT to achieve
high PSRR. The block diagram of 180o phase shift concept has been shown in Fig. 9.4.
88
Figure 9.4: Block diagram of conventional biasing technique (Vbias ) to generate supply independent
PTAT voltage
To understand the compensation relation between VGS and VDS , eqn 9.4 has been rearranged and
written as:

IM 0
VGS = n.VT .ln + VT H − ηVDS (9.5)
Is
Realizing that VGS = Vbias - VX0 and VDS = Vdd - VX0 , equation 9.5 is differentiated w.r.t supply (Vdd ) to
obtain equation 9.6:
dVbias
= −η (9.6)
dVdd
Note that the above relation between Vbias and Vdd is derived by assuming that VX0 is constant, which is
the case for obtaining an infinite PSRR at the output. Negative sign in eq.9.6 shows the 180o phase shift
between Vbias and Vdd . The above concept has been proved by plotting the effect of PSRR of Vbias on
the PSRR of VP T AT for 180o phase shift (Fig. 9.5). The graph is plotted for LM 0 = 4µm and a stable
PSRR of VP T AT is achieved at -80dB requiring only -50dB or greater PSRR of SIVB circuit. Also note
that there is a peak region in the graph near -40dB at which PSRR of VP T AT jumps to -140dB or greater.
This is due the maximum compensation between Vbias and Vdd as proved in equation 9.6 by assuming
no change at VX0 i.e. Vbias is cancelling the complete effect of Vdd , thereby achieving a constant current
IM 0 and very high PSRR (ideally infinite PSRR).
89
Figure 9.5: VP T AT PSRR (composite pair) vs Vbias PSRR (180o phase SIVB)
Now, this peak region is very small and depends on the η factor. The complex modeling of η (DIBL
coefficient) in [120] shows that it is process sensitive and hence varies from chip to chip. Therefore,
designing an SIVB circuit to bias it in the peak region requires precise PSRR which is not practical
considering process and mismatch. Hence, the PSRR of the SIVB circuit must be chosen such that the
PSRR of VP T AT is stable i.e. PSRR of VP T AT does not vary with PSRR of SIVB circuit due to process.
In this case, PSRR of SIVB circuit should be greater than -50dB.
The 180o phase shift voltage biasing circuit is taken from [121]. The circuit diagram of the proposed
temperature sensor is shown in Fig. 9.6. Although the circuit in [121] was originally proposed for ‘node
a’ to achieve good PSRR, another ‘node b’ is selected in the circuit which gives 180o phase and good
PSRR. It is well explained in [121], that the node ‘a’ will increase with supply (0o phase) due to which
the node ‘b’ have to decrease with supply (180o phase).
This SIVB circuit is simply designed for -55dB PSRR at ‘node b’ to achieve stable PSRR at the
output (as explained earlier). This PSRR can be easily achieved and adjusted by sizing the length of
transistor ‘N2’. W/L ratios of MCP 1 and MCP 2 have been chosen to achieve maximum slope (eqn 9.2)
while preserving linearity with temperature. Rnpoly of 250kΩ resistance is used as resistor. The bias
voltage at ‘node b’ is chosen around 650mV so that all the transistors of composite pair will remain
in the sub-threshold region. This voltage can be simply adjusted by varying the W/L of N1. All the
3 branches in SIVB circuit have approximate 2µA current while PTAT voltage generator have 50nA
90
of current, therefore consuming 6µW power at 1V supply. The outcomes have been discussed in the
following results section.

The temperature sensor (shown in Fig. 9.6) is biased using the 180o phase shift SIVB circuit to
achieve a high PSRR. As shown in Fig. 9.7, the SIVB circuit is designed in the safe region achieving
-55.13dB with 180o phase shift. A stable PSRR (with process) of -80dB is obtained at the output of
temperature sensor (VP T AT ) as shown in Fig. 9.8. It deviates by ±1.5dB at extreme process corners.
The plots in Fig. 9.9 shows the line sensitivity of the temperature sensor for supply range of 1V to 2.5V
at extreme temperature values. It achieves a max. line sensitivity of 0.031%/V and min. of 0.012%/V
which is very good due of 180o phase shift of Vbias . Fig. 9.10 shows the variation of the output voltage
VP T AT with temperature for various process corners. The slope of this VP T AT (as shown in Fig. 9.11) is
1mV/o C ±60µV/o C i.e. inaccuracies of ±0.1o C from -55o C to 125o C. The Monte Carlo Simulation of
the temperature sensor including process and mismatch and its layout are shown in Fig. 9.12. It shows
that the PSRR of the sensor will always be close to -80dB. Finally a table (table 9.1) is made comparing
PSRR and other parameters of different references.
9.4 Conclusion
A 180o phase shift biasing technique to achieve a high PSRR has been proposed. This technique
eliminates the need for high PSRR SIVB circuit which requires complex designing methods or so-
phisticated circuitry (opamp or LDO). A low power composite pair based temperature sensor has been
designed using the proposed technique. A PSRR of -80dB is easily achieved when the SIVB circuit is
biased in the stable region. This PSRR can further be enhanced to -120dB to -140dB when the circuit
is biased in the peak region, with a drawback of small safe margin. This proposed 180o biasing tech-
nique can further be improved by using ultra low power SIVB circuits for biasing and can be applied to
composite pair based voltage or current references.
PSRR (dB) Paper Extra circuit Area(mm2 ) Power(µW)
-80 @ 100Hz This work No 0.006 6
-71 @ 50Hz [105] op-amp 0.0084 0.08
-59 @ 10Hz [106] opamp 0.021 0.01
-87 @ 10Hz [107] opamp 13 0.011
-70 @ 100Hz [109] No 0.002 103
-45 @ 100Hz [110] oscillator 0.009 18
Table 9.1: PSRR comparison of different references/temperature sensor
91
Figure 9.6: Schematic of Temperature sensor using proposed biasing technique to achieve very high
supply insensitivity without additional circuitry
92
Figure 9.7: Magnitude and Phase of PSRR for 180o SIVB circuit
Figure 9.8: PSRR of Temp. Sensor (VP T AT ) at extreme process corners
93
Figure 9.9: Line regulation of VP T AT for various temperature values
Figure 9.10: VP T AT with temperature for various process corners
94
Figure 9.11: Slope of VP T AT with temperature
Figure 9.12: Monte Carlo Simulation of PSRR of Temperature Sensor and Layout
95
Chapter 10
Conclusion and Future Work
This work presents the design techniques and architectural solutions for always-on blocks, which
constitute an important sub-system in IoT nodes. The always-on blocks presented in this thesis include
voltage reference, current reference and analog temperature sensor. In cubic millimeter sensor nodes
where the battery size is very small, the sleep-mode power consumption is expected to be in the pico-
watt range. Conventional resistor based architectures cannot be used as the value of resistance required
for achieving pico-watt power consumption would be in the order of GΩ. This would occupy imprac-
tically large area and hence is not a feasible solution. Other resistor less architectures suffer from the
drawbacks as mentioned in the previous chapters.
We use an element called thin-oxide device or gate-leakage transistor, present in lower technology
nodes like 130nm, 90nm, 65nm, 55nm, etc. In these devices, a leakage current of the order of fA -
nA flow through the gates of these devices and can be used as replacements for resistors. Since the
gate-leakage current is non-linear, the transistors cannot be directly visualized as resistors and hence
we model the temperature dependencies of gate-leakage current in inversion and accumulation regions.
The temperature dependencies are exploited to achieve pico-watt current reference, voltage reference
and analog temperature sensor. A design which incorporates both voltage and current reference in a
single circuit is also presented to achieve the functionality of the two blocks in a single circuit.
PVT variations are inevitable in any circuit and it is imperative to make most of the designs resilient
to these PVT variations. Design techniques have already been proposed in Chapters 5 and 7 to achieve
process-invariant nature for voltage reference and temperature sensor. Current references cannot usually
be made process-invariant and are trimmed to reduce the process spread. The last two chapters deal with
techniques to achieve high PSRR in the always-on blocks. In applications where slightly higher average
power is tolerable, voltage reference, current reference and temperature sensor are presented in a single
circuit. The design is chosen such that it achieves a high PSRR for all the three blocks, with other
metrics comparable to the state-of-the-art. The last chapter presents a unique 180o phase shift biasing
technique which can achieve PSRR > 80dB with ease in temperature sensors. Temperature variations
are usually suppressed by adding PTAT and CTAT voltages and are already dealt with in the design of
voltage and current references.
96
The scope of improvement for the presented work includes:
• Design of always-on blocks for supply voltages down to 0.3V so that they can be powered by
energy harvesters.
• Design of always-on blocks for a temperature upto 170o C so that they can be used in applications
such as down-hole monitoring [26].
• Proposing self-calibration techniques for designs which vary with process.
• Designing other always-on blocks such as wake-up timers or other oscillators.
• Proposing novel methods to duty cycle the always-on blocks.
• Design process-invariant current references.
97
Related Publications
Conference Papers (Published/Accepted)

[1] A. Ali, A. Pullela, A. Jain and Z. Abbas, "A Sub-nW, 8T Current Reference Consuming Constant
Power w.r.t Process Temperature," 2020 IEEE 63rd International Midwest Symposium on Circuits and
Systems (MWSCAS), 2020, pp. 730-733, doi: 10.1109/MWSCAS48704.2020.9184679.
[2] A. Pullela, A. Ali, A. Jain, A. Banthi and Z. Abbas, "A 419pW Process-Invariant Temperature
Sensor for Ultra-Low Power Microsystems," 2021 IEEE International Symposium on Circuits and Sys-
tems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401763.
[3] A. Pullela, A. Ali, S. Reddy, A. Jain and Z. Abbas, "A 443pW Accumulation-Mode Gate-Leakage
Based Bandgap Reference for IoT Applications," 2021 IEEE International Midwest Symposium on
Circuits and Systems (MWSCAS), 2021, pp. 986-989, doi: 10.1109/MWSCAS47672.2021.9531737.
[4] A. Pullela, A. Ali, A. Jain, I. Lee and Z. Abbas, "A 156pW Gate-Leakage Based Voltage/Current
Reference for Low-Power IoT Systems," 2022 IEEE International Symposium on Circuits and Systems
(ISCAS) (Accepted)
[5] A. Jain, A. Pullela, A. Ali and Z. Abbas, "A 180o Phase Shift Biasing Technique for Realizing
High PSRR in Low Power Temperature Sensors," 35th International Conference on VLSI Design (Ac-
cepted)
Conference Papers (to be submitted with silicon results in collaboration

with University of Pittsburgh)
[1] Ashfakh Ali, Abhishek Pullela, Arpan Jain, Inhee Lee, and Zia Abbas, “A 3.2nW, 241Hz, −40o C −
170o C Relaxation Oscillator Using Switch Leakage Supression Scheme for Low-Power High-Temperature
IoT Systems" in International Solid-State Circuits Conference (ISSCC) 2023.
98
[2] Arpan Jain, Ashfakh Ali, Abhishek Pullela, Inhee Lee, and Zia Abbas, “ A Novel Nano-watt Re-
laxation Oscillator Using Resistance Amplification Scheme" in International Solid-State Circuits Con-
ference (ISSCC) 2023.
Journals (to be submitted with silicon results in collaboration with Uni-

versity of Pittsburgh)
[1] Abhishek Pullela, Ashfakh Ali, Arpan Jain, Inhee Lee, and Zia Abbas, “ A Review of State-of-
the-art Sub - 1µW Voltage References" in Transactions on Circuits and Systems - I (TCAS - I).
[2] Arnab Dey, Ashfakh Ali, Arpan Jain, Abhishek Pullela, Inhee Lee, and Zia Abbas, “ A Resistance-
to-Digital Converter Using Novel Comparator Delay and Offset Cancellation Schemes" in Transactions
on Circuits and Systems - II (TCAS - II).
Patents (Filed)
[1] Abhishek Pullela, Ashfakh Ali, Arpan Jain, and Zia Abbas, “CONSTANT REFERENCE VOLT-
AGE/CURRENT GENERATING CIRCUIT" (Indian Patent application status - complete application
filed)
[2] Abhishek Pullela, Ashfakh Ali, Arpan Jain, and Zia Abbas, “PROPORTIONAL TO ABSOLUTE
TEMPERATURE (PTAT) SENSING ELEMENT" (Indian Patent application status - provisional appli-
cation filed)
99
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Design Techniques and Architectural Solutions for Low-Power

Analog Circuits Targeting IoT Applications

Thesis submitted in partial fulfillment

International Institute of Information Technology, Hyderabad

Date Advisor: Dr. Zia Abbas

1 Introduction to IoT Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Always-on Analog Blocks and their Functionality . . . . . . . . . . . . . . . . . . . . . . . 8

3 Analysis of Gate-Leakage Current in Inversion and Accumulation Regions . . . . . . . . . . 15

5 A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference for IoT Applications 33

6 Accumulation-mode gate-leakage based Voltage/Current References . . . . . . . . . . . . . 44

7 A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems . . . . . 61

8 Highly Supply Invariant Current/Voltage Reference and Temperature sensor . . . . . . . . . . 72

10 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

1.1 Applications of IoT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Widely used method for Vref generation . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 (a) Components of gate-tunneling currents (b) Connections of gate-leakage transistors . 16

4.1 Proposed current reference including W/L of transistors . . . . . . . . . . . . . . . . . 23

5.1 Proposed Bandgap Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.11 Layout of the BGR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.1 Proposed current reference in chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.1 Proposed Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.1 Comparison between conventional and asymmetric op-amps . . . . . . . . . . . . . . 74

3.1 Gate-Leakage Current Based Model Parameters . . . . . . . . . . . . . . . . . . . . . 20

4.1 Comparison With State-of-the-Art Architectures . . . . . . . . . . . . . . . . . . . . . 32

5.1 Comparison with State-of-the-Art Architectures . . . . . . . . . . . . . . . . . . . . . 43

6.1 Comparison With State-of-the-Art Architectures . . . . . . . . . . . . . . . . . . . . . 53

7.1 COMPARISON WITH STATE-OF-THE-ART ARCHITECTURES . . . . . . . . . . 71

9.1 PSRR comparison of different references/temperature sensor . . . . . . . . . . . . . . 91

Introduction to IoT Applications

1.1 Emergence of IoT from technological trends

1.2 Applications of IoT

Fig.1.1 summarizes the role of IoT in each application.

1.3 IoT design space requirements and challenges

Figure 1.2: Life-time vs avg power consumption of various batteries [1]

Figure 1.3: Concept of duty cycling [1]

1.4 Growth and future of IoT

Always-on Analog Blocks and their Functionality

2.2 Voltage Reference

Figure 2.1: Widely used method for Vref generation

2.2.1 PTAT voltage generation

VP T AT 2 = ηVT ln(M2 ∗ N2 ) (2.5)

Figure 2.3: VP T AT generating architectures based on ∆VBE approach

From equations 2.6 and 2.7, we can simplify eq.2.4 as :

From [4], we have :

Hence, the final expression for VP T AT 2 becomes :

(a) (b) (c)

Figure 2.4: VP T AT generating architectures based on ∆VGS approach

2.2.2 CTAT voltage generation

2.3 Current Reference

2.4 Analog Temperature Sensor

Analysis of Gate-Leakage Current in Inversion and Accumulation

The gate-tunneling current is divided into three components [8]:

3.2.1 Gate-to-Substrate Current (Igb )

Igbacc = Wef f · Lef f · A · ToxRatio · Vgb · Vaux ·

Voxacc = Vf bzb − VF Bef f (3.4)

Igbinv = Wef f · Lef f · A · ToxRatio · Vgb · Vaux ·

Vaux and Voxdepinv in the above equation are given by :

3.2.2 Gate-to-Channel Current (Igc )