Professional Documents
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Synchronization
Synchronization
SRAN5.0
Feature Parameter Description
Issue 01
Date 2010-10-15
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Contents
1 Introduction ................................................................................................................................1-1
1.1 Scope ............................................................................................................................................ 1-1
1.2 Intended Audience ........................................................................................................................ 1-1
1.3 Change History.............................................................................................................................. 1-1
2 Overview .....................................................................................................................................2-1
2.1 Clock Synchronization ................................................................................................................... 2-1
2.2 Time Synchronization .................................................................................................................... 2-1
2.3 Frequency Synchronization........................................................................................................... 2-2
2.4 Difference Between Time Synchronization and Frequency Synchronization ............................... 2-3
6 Parameters .................................................................................................................................6-1
7 Counters ......................................................................................................................................7-1
8 Glossary ......................................................................................................................................8-1
9 Reference Documents .............................................................................................................9-1
1 Introduction
1.1 Scope
This document describes the synchronization feature of GSM and WCDMA, consisting of the basic
principles of clock synchronization, the main clock synchronization techniques, and the SingleRAN clock
solutions. The SingleRAN clock solutions consist of the clock solution on the MBSC side, the clock
solution on the MBTS side, and the common clock solution on the MBTS side.
MBSC is a GSM+UMTS (GU) multi-mode base station controller of Huawei. In this document, the BSC refers to the
MBSC performing the functions of a GSM base station controller, the RNC refers to the MBSC performing the functions
of a UMTS base station controller.
MBTS is a GU, GSM+LTE (GL), or UMTS+LTE (UL) multi-mode base station of Huawei. In this document, the GSM
BTS refers to the MBTS performing the functions of a GSM base station, the NodeB refers to the MBTS performing the
functions of a UMTS base station, and the LTE eNodeB refers to the MBTS performing the functions of a LTE base
station.
Document Issues
The document issues are as follows:
01 (2010-10-15)
Draft (2010-05-15)
01 (2010-10-15)
This is the document for the first commercial release of SRAN5.0.
Compared with issue Draft (2010-05-15) of SRAN5.0, this issue optimizes the description.
Draft (2010-05-15)
This is the draft for SRAN5.0.
2 Overview
2.1 Clock Synchronization
Synchronization of clocks in the network is a critical issue for the digital communication network.
Synchronization of clocks means that the frequencies or phases of clock signals maintain a precise
relation. The purpose of synchronization is to ensure that the frequency or time difference between the
devices in a network is kept within an acceptable margin of error. This can prevent the transmission
performance in a digital communication system from deterioration, such as bit error and jitter, because
data is not correctly transmitted or received.
Clock synchronization consists of time synchronization (also known as phase synchronization) and
frequency synchronization.
The principle of clock synchronization is that a lower-level device is required to synchronize its clock with
the clock of an upper-level device. The base station controller needs to synchronize its clock with the
clock of the Core Network (CN), and the base station needs to synchronize its clock with the clock of the
base station controller.
Phase time, also called phase, is the time delay between the actual signal and the ideal signal at a
significant instance (generally, a rising edge or a falling edge), as shown in Figure 2-2.
Only frequency synchronization is required in GSM and WCDMA systems. The accuracy requirement is
0.05 per million (ppm).
As shown in Figure 2-4, the difference between time synchronization and frequency synchronization is
as follows:
In phase synchronization, Watch A and Watch B always have the same time.
In frequency synchronization, Watch A and Watch B have different times, but the time difference
between the two is always the same, for example, six hours.
3 Synchronization Techniques
In a traditional clock synchronization solution, PDH and SDH networks are used to provide clocks for
GSM and WCDMA systems. After all-IP evolution, IP networks replace PDH and SDH networks to
provide clocks for GSM and WCDMA systems.
The Ethernet ports of the MBSC do not support line clock recovery.
Line clock synchronization provides a high-accuracy reference clock for the radio access network
without requiring additional equipment. Thus, the cost of network construction is greatly reduced. Line
clock is the most widely used synchronization technique.
Disadvantages
The GPS clock synchronization solution requires each base station to be equipped with a GPS
reference receiver, which increases the overall CAPEX.
The GPS antenna requires the field angle of 45ºof the centrum to be clear from obstacles. Thus, the
antenna site selection becomes limited.
Feeders need to be installed between the GPS antenna and the base station. In the case of a
complicated construction venue or building, feeder installation can be difficult. In addition, feeder
installation requires the consent of both the house owners and the property management authorities,
and thus the negotiation may be challenging.
A BITS device can synchronize its clock with the primary reference clock and provide various timing
signals for the digital devices to be synchronized. The types of reference clock of a BITS device can be
the E1 link, 10 MHz, 5 MHz, 1 MHz, or 2048 KHz.
A BITS device may have different configurations based on the importance of the site. A high-end
configuration of the BITS device is rubidium clock + GPS or OXCO + GPS. The GPS module locks the
phase and frequency of the GPS 1PPS clock signals to ensure the long-term stability of the clock. The
rubidium clock or the OXCO ensures the short-term stability of the clock. In this manner, the stability of
the clock is guaranteed.
If a BITS device is not configured with GPS + crystal oscillator, it can lock the upper-level reference clock
through an E1 link.
BITS clocks are generally layered according to the clock quality. A clock synchronization network adopts
a top-down design and provides master and slave synchronization clocks. The clock signals in the clock
synchronization network are distributed through transmission links in a layered and hierarchical manner.
Figure 3-2 shows the BITS clock synchronization solution.
The BITS of the PRC/LPR stratum generally uses the rubidium clock + GPS satellite synchronization
mode. A cesium or hydrogen clock can be used to replace the rubidium clock.
The BITS of the Synchronization Supply Unit (SSU) stratum can be the Transmit Network Clock (TNC)
or the Local Network Clock (LNC).
− BITS of the TNC stratum uses a rubidium clock as the local clock.
− BITS of the LNC stratum uses an OXCO as the local clock.
The BITS of the SDH Equipment Clock (SEC) stratum usually uses a constant-temperature crystal
oscillator as the local clock. SEC specifies a requirement for the transmission device that carries the
source clock signals.
Transmission devices are usually deployed in ring topology. To prevent an upper-level clock device from
tracing the reference clock of a lower-level clock device in ring topology, the strata of reference clocks
are specified by the Synchronization Status Message (SSM) and are ranked in descending order of PRC,
TNC, LNC, and SEC. A BITS device will not choose a reference clock whose stratum is lower than the
stratum of itself.
Disadvantages
BITS clock signals are transmitted through coaxial cables or differential cables, and thus the
transmission distance is relatively short. Therefore, a BITS device provides reference clock signals only
for the communication devices in the same telecommunication equipment room.
The Ethernet clock synchronization technique is a type of IP network clock solution. See the IP Network
Clock Feature Parameter Description of RAN for details.
Disadvantages
There is a restriction on the deployment of a synchronous Ethernet. Clock signals are transmitted on
links. Therefore, all the links on the clock transmission path are required to support synchronous
Ethernet in principle.
Clock extraction is not supported by all ports.
This solution does not provide time synchronization.
According to the IEEE1588 V2 protocol, the clocks in the entire network are classified into TC, BC, and
Ordinary Clock (OC):
The TC is used to transparently transmit clock signals in the network. It processes the delay generated
on the path transmitting IEEE1588 V2 packets.
The BC is an intermediate clock device in the network. A BC has multiple IEEE1588 V2 ports. One
IEEE1588 V2 port of the BC works in slave mode and synchronizes the time and frequency of the
system clock with an upper-level device. Other IEEE1588 V2 ports of the BC work in master mode and
transmit synchronization information level by level.
The OC is an initial device or a terminal device. Such a device has only one IEEE1588 V2 port and
works in slave or master mode. The MBTS functions only as an OC.
The IEEE1588 V2 frequency synchronization does not require a TC or BC, as shown in Figure 3-5.
Disadvantages
The IEEE1588 V2 clock synchronization solution requires an IEEE1588 V2 server.
If an IEEE1588 V2 server provides time synchronization, all the devices on the clock transmission path
are required to support the IEEE1588 V2 protocol. Deploying devices supporting the IEEE1588 V2
protocol on a large scale in the network is challenging.
4.1.1 Overview
The clock synchronization subsystem of the MBSC provides system clock for the MBSC and provides
reference clocks for base stations.
The clock synchronization subsystem of the MBSC consists of the clock board and the clock processing
units of each subrack. The clock board of the MBSC can be the GCUa or GCGa board. Users can run
the SET CLKTYPE command to set the type of a clock board.
The number of MBSCs is greater than the number of CN devices, and many MBSCs are not located in
the central telecommunications room. Therefore, an MBSC generally obtains the reference clock from
an upper-level CN device through the transmission links. The accuracy of the local clock of an MBSC is
generally 4.6 ppm.
The parameters BACK8KCLKSW1 and BACK8KCLKSW2 are used to enable the switch of the line
clock on the backplane.
GPS clock
The GPS clock provides 1PPS clock signals for the MBSC. The MBSC receives the GPS signals at
the ANT port on the GCGa board that is configured with a GPS satellite card. If the MBSC is
configured with the GCUa board that is not configured with a GPS satellite card, the GPS clock is not
applicable to the MBSC.
Local oscillator
If the MBSC fails to obtain any external clock, the MBSC obtains its working clock signals from the
local oscillator.
You can run the MML command ADD CLKSRC to configure the parameter SRCT to set the clock source
type.
The reference clock has three operating modes:
Automatic mode
Users need not specify the reference clock. The MBSC can automatically select the reference clock
with the highest priority.
Manual mode
Users need to specify the reference clock. The MBSC cannot change the reference clock even when
the current specified reference clock is faulty.
Self-oscillation mode
The self-oscillation mode is the initial operating mode of the MBSC clock.
Users can run the SET CLKMODE command to set the clock mode.
The active and standby clock boards in the MPS are connected to the active and standby SCUa boards
in the EPS through the Y-shaped clock signal cables. This connection mode ensures that the system
clock of the MBSC works properly in the case of a single-point failure of the clock board, Y-shaped clock
signal cable, or SCUa board. In addition, the Y-shaped clock signal cables ensure the proper working of
the SCUa boards during the switchover of the active and standby clock boards.
In the MPS, the clock board transmits clock signals to the SCUa boards through the backplane channel. Therefore, the
Y-shaped clock signal cable is not required.
In BM/TC separated configuration mode, the TransCoder (TC) subrack extracts the line clock signals from the A interface
and then the clock board in the BM subrack extracts the clock signals from the Ater interface.
The MPS and the EPS are collectively known as Basic Module (BM) subrack, and the TCS is known as TC subrack.
As illustrated in Figure 4-3 and Figure 4-4, the process of clock synchronization in the MPS/EPS is as
follows:
1. The clock signals are obtained from the external reference clock.
If an external clock is used, external clock signals travel to the clock board through the port on the
panel of the clock board. If the GPS clock is used, clock signals travel to the clock board through the
GPS antenna port. When the external reference clock is the line clock, the clock signals travel to the
clock board through the backplane channel after extracted by the MPS or through clock signal cables
after extracted by the EPS.
2. The reference clock is phase-locked in the clock board to generate clock signals.
3. The clock board in the MPS transmits the clock signals to the SCUa board in the MPS through the
backplane and in each EPS through the clock signal output ports on the clock board.
4. The SCUa board in the MPS/EPS transmits the clock signals to the other boards in the same subrack
through the backplane.
The clock synchronization subsystem of the MBSC transmits reference clock signals to a base station through the Iub or
Abis interface board.
1. The TCS extracts line clock signals from the A interface. Then, the line clock signals are processed
by the A interface board to generate the required clock signals.
2. In the TCS, the A interface board transmits the clock signals to the SCUa board through the
backplane channel. Then, the SCUa board transmits the clock signals to the other boards in the TCS.
In A over IP over Ethernet mode, the MBSC can extract only external clock signals.
In A over IP over E1/T1 mode, the MBSC can extract only line clock signals.
The clock board in the MPS sends the 1PPS signals and synchronization time packets to the SCUa
board in each subrack. The SCUa board in each subrack then transmits the 1PPS signals and
synchronization time packets to the other boards in the same subrack. The boards generate the required
RFN signals based on the received 1PPS signals and synchronization time packets. The 1PPS signals
can be generated by the clock board.
4.2.1 Overview
In GSM and WCDMA networks, base stations do not need to be synchronized with each other. Each
base station can obtain the reference clock from the MBSC. The clock accuracy requirement of a base
station is generally 0.05 ppm.
Clock synchronization provides the reference clock for the normal operation of the MBTS and generates
NodeB Frame Number (BFN) or GSM FN (GFN). The BFN or GFN is the basis for frame synchronization.
The MBTS obtains the reference clock through the clock synchronization for the internal frame
synchronization.
Iub/Abis Clock
The MBTS is synchronized with the line reference clock of its upper-level NE such as the MBSC.
The synchronization with the Abis clock (also known as the BSC tracing clock) can be enabled by setting
ClkType to TRCBSC_CLK, and the synchronization with the Iub clock can be enabled by setting
CLKSRC to LINE. In line clock synchronization, the MBTS receives the clock signals from an
upper-level NE through the E1/T1/Ethernet port. Clock signals must be available on the E1/T1/Ethernet
link for the MBTS to obtain the line reference clock.
GPS Clock
If there is no upper-level clock or the upper-level clock is unstable, the GPS clock can be used as the
reference clock of an MBTS.
The synchronization with the GPS clock for a BTS can be enabled by setting ClkType to TRCGPS_CLK,
and the synchronization with the GPS clock for a NodeB can be enabled by setting CLKSRC to
GPSCARD. In GPS clock synchronization, the GPS clock serves as the reference clock of the MBTS
and a GPS satellite card is required. In the case of a DBS3900/BTS3900/BTS3900A, the Universal
Satellite card and Clock Unit (USCU) needs to be configured.
For a BTS, the parameter CFGFLAG must be set to YES. The parameters relevant to this clock
synchronization mode are listed below:
GPSORGLONASS: specifies whether the GPS clock or the Glonass clock works as the reference
clock when two satellite cards are used.
ANTENNALONG: specifies the length of the feeder cable, which connects the GPS satellite card to
the antenna. The actual delay of the signals transmitted on the feeder can be calculated based on the
length of the feeder cable, thus improving the timing accuracy of the GPS satellite card.
ANTENNAPOWERSWITCH: specifies whether to supply power to the GPS antenna. When the GPS
antenna requires power supply, this parameter needs to be set to SENDPOWER. When the GPS
antenna does not require power supply, this parameter needs to be set to NOPOWER.
The GPS clock signals are processed and synchronized as follows:
The GPS antenna receives and transmits the GPS satellite signals to the GPS satellite card for
processing. The GPS satellite card then forwards the signals from the USCU to the main control board.
The main control board synchronizes the clock signals with the MBTS clock signals.
A GPS antenna can simultaneously trace up to eight satellites.
BITS Clock
The synchronization with the BITS clock for a BTS can be enabled by setting ClkType to EXTSYN_CLK,
and the synchronization with the BITS clock for a NodeB can be enabled by setting CLKSRC to BITS. In
BITS clock synchronization, the external BITS clock works as the reference clock of the MBTS. In the
case of a DBS3900/BTS3900/BTS3900A, the USCU must be configured.
The BITS clock signals are processed and synchronized as follows:
The BITS clock output port is connected to the BITS clock input port on the USCU. The master clock
module of the MBTS performs phase-locking and frequency division on the received clock signals to
generate clock signals required by the MBTS.
IP Clock
The MBTS supports IP clock synchronization. In an all-IP network, the MBTS can obtain clock signals
from the IP network. IP clocks can be classified into the synchronous Ethernet clock and the IEEE1588
V2 clock.
The IP network clock signals are processed and synchronized as follows:
The MBTS obtains clock signals from the FE/GE link. After local selection or frequency division, the
signals are sent to the clock module in the main control board as the reference clock. The clock module
in the main control board then converts the signals through phase-locking to generate clock signals
required by the MBTS. The 10 Mbit/s FE port of the MBTS does not support synchronization with the
Ethernet clock.
Internal Clock
The internal clock of the MBTS is generated by the main control board. The internal clock of the MBTS
can work in free-run mode to keep the MBTS running if the external reference clock is disabled or lost.
The enhanced stratum 3 OCXO with high accuracy works as the system clock of the MBTS. The OCXO
can ensure the normal operation of the MBTS for up to 90 days.
As shown in Figure 4-7, the process of clock synchronization in the NodeB is as follows:
1. The clock signals are obtained from the external reference clock.
If the external reference clock is the line clock, the WMPT extracts the clock signals from the
transmission links over the Iub interface. If the external reference clock is the GPS clock, the GPS
antenna receives and transmits the GPS clock signals to the GPS satellite card for processing before
forwarding them to the WMPT. If the external reference clock is the BITS clock, the BITS port on the
USCU receives and forwards the clock signals to the WMPT.
2. The WMPT delivers the clock signals to its clock module.
3. In the WMPT, the clock module performs phase-locking and frequency division on the clock signals,
and then generates various clock signals required by the NodeB.
4. The WMPT distributes the clock signals to the other boards of the NodeB. Note that the clock signals
are forwarded to the MRRU/MRFU through the WBBP.
Figure 4-8 BTS clock synchronization process
As shown in Figure 4-8, the process of clock synchronization in the BTS is as follows:
1. The clock signals are obtained from the external reference clock.
If the external reference clock is the line clock, the GTMU extracts the clock signals from the
transmission links over the Abis interface. If the external reference clock is the GPS clock, the GPS
antenna receives and sends the GPS clock signals to GPS satellite card for processing before
forwarding them to the GTMU. If the external reference clock is the BITS clock, the BITS port on the
USCU receives and forwards the clock signals to the GTMU.
2. The GTMU delivers the clock signals to its clock module.
3. In the GTMU, the clock module performs phase-locking and frequency division on the clock signals,
and then generates various clock signals required by the BTS.
4. The GTMU distributes the clock signals to the other boards of the BTS.
If the MBTS is configured with the Universal BaseBand Radio Interface Board (UBRI), the clock signals are forwarded to
the MRRU/MRFU through the UBRI.
The common clock solution enables two base stations using different radio access technologies (RATs)
to share the same clock source. In a common clock scenario, only one set of clock equipment is required.
After the base station using a RAT obtains the reference clock, this base station shares its reference
clock with the base station using a different RAT. For example, a BTS can share its reference clock with
an eNodeB, and an eNodeB can also share its reference clock with a BTS. If the base station using a
RAT uses the reference clock shared by the base station using a different RAT, the reference clock of the
former base station needs to be configured as the peer reference clock. For example, if a BTS uses the
reference clock shared by an eNodeB, the parameter ClkType of the BTS needs to be set to
PEER_CLK.
The GU/GL/UL common clock solution is supported by Huawei MBTSs that share a common baseband
unit (BBU). The common clock solution corresponds to the features MRFD-221601 Multi-mode BS
Common Reference Clock (NodeB) and MRFD-211601 Multi-mode BS Common Reference Clock
(GBTS).
When the base stations using different RATs share a BBU, the boards of the base stations are installed in the same BBU.
To use a common E1/T1 reference clock, the following conditions must be met:
The base station using a RAT needs to be connected to the transport network through an E1/T1 link,
on which clock signals are transmitted.
This base station obtains the E1/T1 reference clock through the Abis/Iub/S1 interface.
The base station using a different RAT can use this synchronous E1/T1 reference clock through the
backplane channels of the multi-mode BBU.
Table 4-1 describes the typical deployment scenarios of a common E1/T1 reference clock.
Table 4-1 Typical deployment scenarios of a common E1/T1 reference clock
Deployment Scenario Description
Common E1/T1 When TDM over E1/T1 transmission is used over the Abis interface and IP
reference clock on the over FE/GE transmission is used over the S1 interface, the eNodeB can
BTS side obtain the reference clock from the E1/T1 link of the Abis interface.
When TDM over E1/T1 transmission is used over the Abis interface and IP
over FE/GE transmission is used over the Iub interface, the NodeB can obtain
the reference clock from the E1/T1 link of the Abis interface.
Common E1/T1 When TDM over E1/T1 transmission is used over the Iub interface and IP over
reference clock on the GE transmission is used over the S1 interface, the eNodeB can obtain the
NodeB side reference clock from the E1/T1 link of the Iub interface.
When the Iub and Abis interfaces use common transmission (co-transmission)
based on IP over E1/T1 or IP-based hybrid transmission on the MBTS side,
the BTS can obtain the reference clock from the E1/T1 link of the Iub interface.
The Universal Transmission Processing unit (UTRP) in GSM mode does not support E1/T1 clock synchronization.
The UTRP in LTE/UMTS mode supports E1/T1 clock synchronization.
For details about co-transmission, see the Common Transmission Feature Parameter Description of the SingleRAN
The multicast IEEE1588 V2 clock is not supported in GU, GL, and UL co-transmission through FE port interconnection.
A BTS supports the common IEEE1588 V2 clock only when it has a GTMUb board.
Table 4-2 describes the typical deployment scenarios of a common IEEE1588 V2 reference clock.
Table 4-2 Typical deployment scenarios of a common IEEE1588 V2 reference clock
Deployment Description
Scenario
Common IEEE1588 When the Abis and S1 interfaces use IP-based co-transmission on the MBTS
V2 reference clock on side and the IP network supports IEEE1588 V2 clock synchronization, the BTS
the eNodeB side can obtain the reference clock from the LMPT through the backplane channels
of the multi-mode BBU.
When the Iub and S1 interfaces use IP-based co-transmission on the MBTS
side and the IP network supports IEEE1588 V2 clock synchronization, the
NodeB can obtain the reference clock from the LMPT through the backplane
channels of the multi-mode BBU.
Common IEEE1588 When the Iub and Abis interfaces use IP-based co-transmission on the MBTS
V2 reference clock on side and the IP network supports IEEE1588 V2 reference clock, the BTS can
the NodeB side obtain the reference clock from the WMPT through the backplane channels of
the multi-mode BBU.
Table 4-3 describes the typical deployment scenarios of a synchronous Ethernet reference clock.
Network synchronization is responsible for the distribution of clocks and allows the clocks to operate at
the same frequency in different network nodes.
Node synchronization is responsible for the measurement of phase difference between the RNC and the
NodeB. Node synchronization is the basis for the numbering of frames between the RNC and the NodeB
and for frame timing. The correct operation of node synchronization is dependent on the proper
operation of network synchronization.
Frame synchronization is responsible for the numbering and transmission of frames between the RNC
and the NodeB at the correct time, thus compensating for transmission delay and processing delay on
the RNC-NodeB path. The correct operation of frame synchronization within the radio network
subsystem (RNS) is dependent on the proper operation of node synchronization.
Radio interface synchronization is responsible for the alignment of frames between the NodeB and the
UE.
For the synchronization process in the UTRAN, see 3GPP TS 25.402.
The network synchronization modes shown in Figure 5-2 are described as follows:
Plesiochronous synchronization
In a plesiochronous network, each node has an independent clock.
Master-slave synchronization
Master-slave synchronization is the most commonly used synchronization mode. A master-slave
synchronization network has a single PRC, to which all other clocks on the network are locked.
Mutual synchronization
In a mutual synchronization network, there is no PRC. Each clock can receive the clock signals from
another.
The RNC and NodeB need to synchronize the frequencies of their internal timing units (TUs) with a
common and traceable reference clock. The TU generates accurate and stable clock signals, distributes
them within the RNC or NodeB, and provides them for the outgoing PDH/SDH links or the radio interface.
In IP over Iub transmission mode, the RNC also generates time stamped IP packets.
In the downlink, the RNC needs to perform frame synchronization before sending data frames on the
radio interface. With frame synchronization, a common data frame reference, that is, a Connection
Frame Number (CFN), is provided between a transport channel on the UTRAN side and a transport
channel on the UE side to identify the transmission sequence of a Transport Block Set (TBS).
Each TBS has a CFN. The CFN at the transmission end must be the same as that at the reception end.
This consistency is ensured through the mapping between the CFN and the System Frame Number
(SFN) of the cell, considering that the CFN is not transmitted on the radio interface whereas the SFN is
transmitted on the broadcast channel.
Parameter Description
tproc Specifies the time taken to process a data frame by the physical layer of the
NodeB before transmission on the air interface.
LTOA Specifies the latest time that the RNC can send a data frame to the NodeB.
5. After the RNC receives the RADIO LINK SETUP RESPONSE message from the NodeB, the RNC
completes Iub synchronization. Then, the NodeB starts downlink transmission.
6. The RNC sends the DOFF and the frame offset to the UE through an RRC CONNECTION SETUP
message.
7. Based on the DOFF, the UE calculates the frame offset and chip offset, which are used for
calculating the offset of the CFN relative to the SFN. Then, the UE performs downlink chip
synchronization and frame synchronization based on the information received on the P-CCPCH.
After the downlink synchronization is complete, the UE starts uplink transmission.
8. The NodeB performs uplink chip synchronization and frame synchronization. After the uplink
synchronization is complete, the NodeB notifies the RNC of uplink synchronization completeness
through a RADIO LINK SETUP RESTORE INDICATION message. After the radio link
synchronization is complete, the radio link is available for use.
6 Parameters
Table 6-1 MBSC Parameter description
Parameter NE MML Description
ID
REF2MCL BSC6900 SET Meaning: Switch of panel BITS1(2M)
KSW1 CLK(Optional)
GUI Value Range: OFF(OFF), ON(ON)
Actual Value Range: OFF, ON
Unit: None
Default Value: OFF
REF2MCL BSC6900 SET Meaning: Switch of panel BITS2(2M)
KSW2 CLK(Optional)
GUI Value Range: OFF(OFF), ON(ON)
Actual Value Range: OFF, ON
Unit: None
Default Value: OFF
BACK8KC BSC6900 SET Meaning: Switch of backplane LINE1
LKSW1 CLK(Optional)
GUI Value Range: OFF(OFF), ON(ON)
Actual Value Range: OFF, ON
Unit: None
Default Value: OFF
BACK8KC BSC6900 SET Meaning: Switch of backplane LINE2
LKSW2 CLK(Optional)
GUI Value Range: OFF(OFF), ON(ON)
Actual Value Range: OFF, ON
Unit: None
Default Value: OFF
SRCT BSC6900 ADD Meaning: Type of the clock source.
CLKSRC(Mandat
ory) GUI Value Range: BITS1-2MHZ(2MHZ
Building Integrated Timing Supply
system 1), BITS2-2MHZ(2MHZ
Building Integrated Timing Supply
system 2), BITS1-2MBPS(2MBPS
Building Integrated Timing Supply
system 1), BITS2-2MBPS(2MBPS
Building Integrated Timing Supply
system 2), 8KHZ(8KHZ), GPS(Globe
Positioning System),
LINE1_8KHZ(8KHZ line1),
LINE2_8KHZ(8KHZ line2),
BITS1-1.5MBPS(1.5MBPS Building
Integrated Timing Supply system 1),
BITS2-1.5MBPS(1.5MBPS Building
Integrated Timing Supply system 2)
Actual Value Range: BITS1-2MHZ,
BITS2-2MHZ, BITS1-2MBPS,
BITS2-2MBPS, GPS, 8KHZ,
7 Counters
There are no specific counters associated with this feature.
8 Glossary
For the acronyms, abbreviations, terms, and definitions, see the Glossary.
9 Reference Documents
[1]. IP Network Clock Feature Parameter Description of RAN
[2]. Synchronization in UTRAN, 3GPP TS 25.402.