GND 1 40 VCC

AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7 MN/MX’ –
logic 1
AD8 8 33 MN/MX (Minimum
AD7 9 32 RD mode)
AD6 10 31 HOLD RQ/GT0
8086 MN/MX’ –
AD5 11 30 HLDA RQ/GT1 logic 0
29 WR LOCK (Maximum
AD4 12
mode)
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Address bus

 BITS Pilani

ADDRESS & DATA signals are MULTIPLEXED

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani

ADDRESS & DATA signals are MULTIPLEXED

De-multiplexed externally using latch

ALE
BITS Pilani

Indicates that address/data bus contains address

information
The address can be for addressing a memory or
an I/O device.
 BITS Pilani

74LS273

Octal Latch
G OE

ALE
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
ALE/BHE’
BITS Pilani

Indicates that address/data bus contains address

information
The address can be for addressing a memory or
an I/O device.

The BHE’ pin enables data bus bits (D15–D8)

during a read or a write operation.
 A16-A19
S6-S3 A16-A19
BITS Pilani
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 BITS Pilani
Signal Address Status

AD16/S3 AD16 S3 Segment

Access
AD17/S4 AD17 S4

AD18/S5 AD18 S5 Interrupt Flag

bit
AD19/S6 AD19 S6 0

BHE’/S7 BHE S7 1
 A16-A19
S6-S3 A16-A19
BITS Pilani
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Data bus

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Buffered Systems
BITS Pilani

Buffering of control/data/addr busses  signals

sufficiently strong to drive various IC chips
Bus buffering  Boosting the bus signals to increase the
FANOUT
Unidirectional Buffer - 74LS244
Bidirectional Buffer - 74LS245
Unidirectional Buffer
BITS Pilani

A Bus B Bus
Input Output

0
Bidirectional Buffer
BITS Pilani

A Bus
B Bus

E DIR

0 0
1
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Bidirectional Buffer – 8086 Data bus
BITS Pilani

A Bus B Bus
Inputs/Outputs Inputs/Outputs

E DIR

DEN DT/R
 BITS Pilani
8086

AD8-AD15 LS245 D8-D15

DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V

System Bus of 8086(Data)

 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Control bus

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani

M/IO’- Indicates that microprocessor address bus

contains memory/IO address
WR’ – Low indicates that the bus contains valid
data for Memory or I/O

RD’- Processor is ready to receive data from

Memory or I/O
M/IO’ IOR’ BITS Pilani

RD’
M/IO’ RD’ WR’ Bus cycle

1 0 1 MEMR’

M/IO’ IOW’ 1 1 0 MEMW’

WR’ 0 0 1 IOR’

0 1 0 IOW’

M/IO’ MEMR’
RD’

M/IO’ MEMW’
WR’
 RD
MEMR
BITS Pilani

LS244 LOGIC MEMW

WR
CIRCUIT IOR
IO/M OE’
IOW

MN/MX’ 5V

System Bus of 8086( Control)

 A16-A19
S6-S3 A16-A19
BITS Pilani
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 RD
MEMR
BITS Pilani

LS244 LOGIC MEMW

WR
CIRCUIT IOR
IO/M OE’
IOW

8086
AD8-AD15 LS245 D8-D15
DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V

System Bus of 8086(Data + Control)