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22ETL305 A and D Question Bank
22ETL305 A and D Question Bank
2 Design a fullwave rectifier with Capacitor filter for the following 22ETL305
specification. VDC=10.8V,IDC=30mA, ripple factor ≤ 0.06.
3 Design a double side clipper which slice the input at 2V in the + half cycle 22ETL305
and -2V in the negative half cycle. Obtain its transfer characteristic.
4 Design an independent level clipper which slice the input at 4V and 22ETL305
1V in the + half cycle and obtain its transfer characteristic.
5 Design a shunt diode clipper and series diode clipper which slice the 22ETL305
input at -2V.Obtain its transfer characteristic.
6 Design a clamper circuit to clamp the negative peak at 3V for an input 22ETL305
signal of 1 KHz.
7 Design a clamper circuit to clamp the positive peak at -3V for an input 22ETL305
signal of 1 KHz.
8 Design an RC coupled single stage BJT amplifier and plot the frequency 22ETL305
response. Find Zi, Zo and gain bandwidth product.
9 Design and set up a crystal oscillator and determine its frequency of 22ETL305
oscillation.
10 Obtain the Drain and Transfer characteristic of a given FET and 22ETL305
determine its parameters.
11 Design and implement a half adder circuit using basic gates and only 22ETL305
Nand gates
12 Design and implement a full adder circuit using basic gates (Two half 22ETL305
adders) and only Nand gates
13 Design an adder circuit using Op-Amp 22ETL305
21 Realize shift register operation SISO and SIPO using IC 7495 22ETL305
22 Realize shift register operation PIPO and PISO using IC 7495 22ETL305
2 Design a fullwave rectifier with Capacitor filter for the following 22ETL305
specification. VDC=10.8V,IDC=30mA, ripple factor ≤ 0.06.
3 Design a double side clipper which slice the input at 2V in the + half cycle 22ETL305
and -2V in the negative half cycle. Obtain its transfer characteristic.
4 Design an independent level clipper which slice the input at 4V and 22ETL305
1V in the + half cycle and obtain its transfer characteristic.
5 Design a shunt diode clipper and series diode clipper which slice the 22ETL305
input at -2V.Obtain its transfer characteristic.
6 Design a clamper circuit to clamp the negative peak at 3V for an input 22ETL305
signal of 1 KHz.
7 Design a clamper circuit to clamp the positive peak at -3V for an input 22ETL305
signal of 1 KHz.
8 Design an RC coupled single stage BJT amplifier and plot the frequency 22ETL305
response. Find Zi, Zo and gain bandwidth product.
9 Design and set up a crystal oscillator and determine its frequency of 22ETL305
oscillation.
10 Obtain the Drain and Transfer characteristic of a given FET and 22ETL305
determine its parameters.
11 Design and implement a half adder circuit using basic gates and only 22ETL305
Nand gates
12 Design and implement a full adder circuit using basic gates (Two half 22ETL305
adders) and only Nand gates
13 Design an adder circuit using Op-Amp 22ETL305
21 Realize shift register operation SISO and SIPO using IC 7495 22ETL305
22 Realize shift register operation PIPO and PISO using IC 7495 22ETL305