BUFFER LAB 1

DIGITAL DESIGN CSET 105

SIDDHI BHARDWAJ E23CSEU2200
BATCH 74 G10

1.Implement the Boolean function F(A, B, C) = Σ(3, 5, 6, 7) with a 4:1 multiplexer. Write a Verilog
code for the above design.
DESIGN CODE:
module mux4to1 (input [1:0] S, input [3:0] D, output F);
assign F = S == 2'b00 ? D[0] :
S == 2'b01 ? D[1] :
S == 2'b10 ? D[2] : D[3];
endmodule
TESTBENCH CODE:
module top;
reg [1:0] S;
reg [3:0] D;
wire F;

mux4to1 m1 (.S(S), .D(D), .F(F));

initial begin
$dumpfile("test.vcd");
$dumpvars(0, top);
#0 S = 2'b00; D = 4'b0111; #10
#10 S = 2'b01; D = 4'b1011; #10
#20 S = 2'b10; D = 4'b1101; #10
#30 S = 2'b11; D = 4'b1110; #10
#40 $finish;
end
endmodule
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2. Write truth table and Verilog code to implement 3:1 Multiplexer using 2:1 MUXes.

DESIGN CODE:
module mux2to1 (input S, input D0, input D1, output Y);
assign Y = S ? D1 : D0;
endmodule

module mux3to1 (input S1, input S0, input D0, input D1, input D2, output Y);
wire Y0, Y1;
mux2to1 m0 (.S(S0), .D0(D0), .D1(D1), .Y(Y0));
mux2to1 m1 (.S(S0), .D0(D0), .D1(D2), .Y(Y1));
mux2to1 m2 (.S(S1), .D0(Y0), .D1(Y1), .Y(Y));
endmodule

TESTBENCH CODE;

`timescale 1ns / 1ps

module tb;
 reg S1, S0;
reg D0, D1, D2;
wire Y;

mux3to1 uut (.S1(S1), .S0(S0), .D0(D0), .D1(D1), .D2(D2), .Y(Y));

initial begin
$dumpfile("test.vcd");
$dumpvars(0, tb);

S1 = 0; S0 = 0; D0 = 1; D1 = 0; D2 = 0; #10
S1 = 0; S0 = 1; D0 = 0; D1 = 1; D2 = 0; #10
S1 = 1; S0 = 0; D0 = 0; D1 = 0; D2 = 1; #10
S1 = 1; S0 = 1; D0 = 0; D1 = 0; D2 = 0; #10
#10 $finish;
end
endmodule

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3. Write truth table and Verilog code to implement 3:8 Binary decoder Dataflow Modeling.

DESIGN CODE;
module decoder_3to8 (input [2:0] A, output [7:0] Y);
assign Y[0] = ~A[2] & ~A[1] & ~A[0];
assign Y[1] = ~A[2] & ~A[1] & A[0];
assign Y[2] = ~A[2] & A[1] & ~A[0];
assign Y[3] = ~A[2] & A[1] & A[0];
assign Y[4] = A[2] & ~A[1] & ~A[0];
assign Y[5] = A[2] & ~A[1] & A[0];
assign Y[6] = A[2] & A[1] & ~A[0];
assign Y[7] = A[2] & A[1] & A[0];
endmodule
TESTBENCH CODE:
module tb_decoder_3to8;

reg [2:0] A;

wire [7:0] Y;

decoder_3to8 uut (
.A(A),
.Y(Y)
);

initial begin

A = 3'b000;

#100;

A = 3'b000; #10;
A = 3'b001; #10;
 A = 3'b010; #10;
A = 3'b011; #10;
A = 3'b100; #10;
A = 3'b101; #10;
A = 3'b110; #10;
A = 3'b111; #10;

end

initial begin
$monitor("At time %dns, Inputs A = %b, Outputs Y = %b", $time, A, Y);
end

initial begin

$dumpfile("decoder_3to8.vcd");
$dumpvars(0, tb_decoder_3to8);
end

endmodule

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4. Write truth table and Verilog code to implement 8:3 Binary Encoder Dataflow Modeling
DESIGN CODE;
module encoder_8to3 (input [7:0] Y, output [2:0] A);
assign A[0] = Y[1] | Y[3] | Y[5] | Y[7];
assign A[1] = Y[2] | Y[3] | Y[6] | Y[7];
assign A[2] = Y[4] | Y[5] | Y[6] | Y[7];
endmodule
TESTBENCH CODE’;
module tb_encoder_8to3;
reg [7:0] Y;

wire [2:0] A;

encoder_8to3 uut (
.Y(Y),
.A(A)
);

initial begin
Y = 8'b00000001;
// Wait 100 ns for global reset to finish
#100;

Y = 8'b00000010; #10;
 Y = 8'b00000100; #10;
Y = 8'b00001000; #10;
Y = 8'b00010000; #10;
Y = 8'b00100000; #10;
Y = 8'b01000000; #10;
Y = 8'b10000000; #10;

end

initial begin
$monitor("At time %dns, Inputs Y = %b, Outputs A = %b", $time, Y, A);
end

initial begin
$dumpfile("encoder_8to3.vcd");
$dumpvars(0, tb_encoder_8to3);
end

endmodule

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