Electronic Circuits

Dr. R. Malmathanraj

National Institute of Technology, Trichy

February 7, 2023

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1 Overview

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Overview

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MOSFET BIASING

Discrete MOSFET
IC MOSFET

Enhancement Mode
Depletion Mode

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Biasing in MOSFET Amplifiers

There are two different environments in which MOSFET amplifiers are found,
(1) discrete circuits and (2) integrated circuits (ICs). The methods of biasing
transistor amplifiers are different in these two environments.

Why? Primarily because it’s ”expensive” to fabricate resistors (and large

capacitors) on ICs. Of course, this is not a problem for discrete component
circuits.

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Biasing in MOSFET Amplifiers

Zero bias: The gate is shorted to the source, so drain current (by definition)
equals IDSS the rating of the component. (Remember: IDSS is the
shorted-gate drain current.

Depletion mode: The negative gate-source voltage forces free electrons away
from the gate, forming a depletion layer that cuts into the channel. As a
result, ID < IDSS .

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Biasing in MOSFET Amplifiers

Enhancement mode: The positive gate source voltage attracts free electrons
in the substrate toward the channel while driving valence-band holes (in the
substrate) away from the channel. As a result, the material to the right of
the channel effectively becomes n-type material.

This results in a wider channel, and ID > IDSS

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Depletion Mode and Enhancement mode of MOSFET

Figure: Symbols of Depletion Mode and Enhancement Mode MOSFET

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Enhancement Mode and Depletion Mode of MOSFET

Enhancement Mode Depletion Mode

It is Normally OFF device at zero
Gate to Source voltage
At OFF condition it cannot con-
duct electrical current.
Positive gate voltage (more than
source voltage) is required to turn
on this type of MOSFET
In this type of MOSFET, the gate
voltage directly proportional to the
Drain Current.
Table: Difference between Enhancement Mode and Depletion Mode MOSFET
It is Normally ON device at zero
Gate to Source voltage
At OFF condition it can conduct
electrical current.
Negative gate voltage(less than
threshold voltage) is required to
turn off this type of MOSFET
In this type of MOSFET, the gate
voltage Inversely proportional to
the Drain Current.

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Enhancement Mode and Depletion Mode of MOSFET

Enhancement Mode Depletion Mode

There is no permanent channel;
a temporary channel is produced
when a voltage applied across it.
Enhancement MOSFET has leak-
age current and diffusion current
concept.
The advantage of Enhancement
MOSFET is ultra-fast switching
capability with high current con-
duction.
Table: Difference between Enhancement Mode and Depletion Mode MOSFET
There is a permanent fabricated
channel available. Generally, the N-
Type channel
Depletion MOSFET does not have
any leakage current and diffusion
current concept.
The advantage of Depletion MOS-
FET is, it can be used as a variable
resistive load.

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Enhancement MOSFET regions of operation

Figure: Regions of Operation

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Enhancement MOSFET regions of operation

Depending upon the relative voltages of its terminals, MOS is said to operate
in either of the cut-off, linear or saturation region.

Cut off region – A MOS device is said to be operating when the

gate-to-source voltage is less than Vth . Thus, for MOS to be in cut-off
region, the necessary condition is
0 < VGS < Vth for NMOS
0 > VGS > Vth for PMOS
Cut-off region is also known as sub-threshold region.
In this region, the dependence of current on gate voltage is exponential. The
magnitude of current flowing through MOS in cut-off region is negligible as
the channel is not present. The conduction happening in this region is known
as sub-threshold conduction.

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Enhancement MOSFET regions of operation

Linear or non saturation region – For an NMOS, as gate voltage increases
beyond threshold voltage, channel is formed between source and drain
terminals. Now, if there is voltage difference between source and drain,
current will flow. The magnitude of current increases linearly with increasing
drain voltage till a particular drain voltage determined by the following
relations
VGS ≥Vth
VDS < VGS − V th
The current is, then, represented as a linear function of gate-to-source and
drain-to-source voltages. That is why, MOS is said to be operating in linear
region. The linear region voltage-current relation is given as follows:
VGS −V th−VDS
ID (Linear) = µCox W L 2 VDS

Similarly, for P-MOS transistor, condition for P-MOS to be in linear region is

represented as:
VGS < Vth
VDS > VGS − V th
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Enhancement MOSFET regions of operation

Saturation Region – For an NMOS, at a particular gate and source voltage,

there is a particular level of voltage for drain, beyond which, increasing drain
voltage seems to have no effect on current. When a MOS operates in this
region, it is said to be in saturation. The condition is given as:

VGS ≥ Vth
VDS > VGS − Vth

The current, now, is a function only of gate and source voltages:

2
ID (Sat) = 12 µCox W
L (VGS − V th)

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Biasing in MOSFET Amplifiers

Biasing: Creating the circuit to establish the desired DC voltages and

currents for the operation of the amplifier
Four common ways:

1. Biasing by fixing VGS

2. Biasing using Voltage Divider arrangement

3. Biasing using a Drain-to-Gate Feedback Resistor

4. Biasing Using a Constant-Current Source

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Biasing in MOSFET Amplifiers

Biasing by fixing VGS using Voltage divider bias

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Biasing in MOSFET Amplifiers

Biasing using a Drain-to-Gate Feedback Resistor

Figure: Using Feedback Resistor

IG = 0
since Gate connected to drain, VGS = VDS
So the MOSFET will be in saturation since VDS > VGS − Vth
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Figure: Caption

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Biasing in MOSFET Amplifiers

Biasing using a constant current source

Figure: Using constant current source

I=IREF = ID
This is used in Integrated Circuits

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Biasing in MOSFET amplifiers

Figure: Current mirror

A MOSFET circuit rigged up as a current mirror used as a current sink

(source). Here, VO is chosen to ensure both transistors are in saturation
A MOSFET is always operating in the saturation regime when the drain is
shorted to its gate
VDS > VGS − Vth
implying saturation always.
2
ID1 = 12 µCox W
L 1 (VGS − V th)

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Biasing in MOSFET amplifiers

The drain current is supplied by VDD through R. The gate currents are zero,
and hence, by KVL or Ohm’s law,
−VGS
ID1 = IREF = VDDR

This is also a reference current, and hence named as IREF . Varying R

changes this reference current.
Now if Q2 is also made to operate in saturation by the appropriate choice of
VO, then the drain current of Q2 is
2
IO = ID2 = 12 µCox WL 2 (VGS − V th)
Hence, assuming that the transistors have the same threshold voltage Vth ,
one gets
IO (W/L)2
IREF = (W/L)1

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Thank you!

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