FPGA Design for Embedded Systems

(EE-4213)

Lecture-1 & 2

Electrical Engineering Department

Introduction
• Design and Development of Digital Circuits using HDL
• Xilinx FPGA
• Verilog HDL will be used
• The focus will be at behavioral level/RTL

Books:
1. Pong P. Chu, “FPGA Prototyping by Verilog Examples: Xilinx Spartan-3,” Wiley-Inter science, 1st
Edition, 2008, ISBN-10: 0470185325.
2. Charles Roth, “Digital Systems Design using Verilog”.
Integrated Circuits
• The integrated circuits are classified in to
• Analog circuits
• Oscillator
• Amplifier
• FM Transmitter and Receiver

• Digital Circuits
• Multiplexer, Decoder, Adder
• Processor, Memory

• Analog Mixed Signal

• Combination of Analog and Digital
Digital IC Design Methodology
Digital Circuits
• Digital Circuits or systems can be designed on
• Application Specific Integrated Circuit (ASIC)
• Programmable Gate Arrays

• The ASIC is formed after the fabrication of circuit on a chip. After the fabrication, the circuit
inside the ASIC cannot be changed.
• Circuit/Physical level

• A digital system can be realized on Programmable Gate Arrays

• Only Gate level
Programmable Logic Devices (PLDs)
• The Programmable Logic Devices are the integrated circuits which allows to
make/implement any digital circuit/function.

• The two types of PLDs are

• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

• PLDs have multiple AND OR planes with

programmable fuses. The connection are formed
by programming the fuses.

• The user defines the logic function to be

implemented by the PLD by programming
the input and output configurations into the device.
What is an FPGA?
• The Field Programmable Gate Array (FPGA) is an integrated circuit designed to be
configured after the manufacturing.

• Any digital system can be designed/implemented on FPGA using Hardware

Description Language (HDL)
• Processor
• Memory
• Decoders

• FPGA is an important platform to design an Embedded Systems

• Only digital system

• The leading FPGA manufacturers are

• Xilinx (now AMD)
• Altera
Inside the FPGA
• The FPGA consists of
• Logic Blocks/Cells
• Programmable Interconnects
• Programmable Input/output Blocks

• The logic Block/Cell allows to make any logic

gate/function inside it.

• The programmable Interconnects allows to

connect different logic blocks with each
other.
Inside the Logic Block/Cell
• The logic block/cell on FPGA contains
• Look Up Table (Memory)
• D-Flip Flop
• Multiplexer

• Multiple logic cell are connected with each

other with the help of programmable
Interconnects.
Hardware Description Language
• Hardware Description Language (HDL) is used to design complex digital
circuits.
• High-level programming constructs

• The most widely used HDLs are

• Verilog (Verification Logic) HDL
• VHDL (Very High Speed Integrated Circuit Design) HDL
• System Verilog

• HDL provides sequential and concurrent flow

Levels of Abstractions
The levels of abstractions to design digital circuits:
a) Switch level: A model that describes the transistors and the interconnect
between them (circuit level). The lowest level of abstraction is switch or transistor
level modeling.
b) Gate Level: A model that describes the logic gates and the interconnections
between them. The code at gate level is built from HDL primitives. These
primitives are built in gate level models of basic functions, including AND, OR,
NOT, NAND etc.
c) Data Flow Level: Describes the flow of data between input and output. It uses
concurrent assign statements. This level of abstraction is higher than the gate
level. Expressions, operands and operators characterize this level
d) Structural Level: The model uses module initiation, combining different HDL
modules. Describes the structure of a circuit with different modules (functions)
e) Behavioral Level: A model that uses the high level logic constructs of HDL e.g if
else, case, for and procedural blocks and statements. Describes what the circuit
does at a higher level of abstraction.
FPGA Design Flow
Design Entry:
There are different techniques for design entry including , HDL, Schematic,
and combination of both. The design is described in formal hardware
description language.
Synthesis:
In this step, the HDL code is converted in to gate level netlist i.e. a
complete circuit with logical elements( gates, flip flops etc)
Implementation:
This process has three steps:
Translate: This process combines all the input netlists and constraints to a
logic design file. Defining constraints is assigning the ports in the design to
the physical elements (pins, switches) of the targeted device. (NGD file)
Map: This process divides the whole circuit with logical elements into sub
blocks such that they can be fit into the FPGA logic blocks. That means
map process fits the logic defined by the NGD file into the targeted FPGA
elements. (NCD file)
Place and Route: The place and route process places the sub blocks from
the map process into logic blocks according to the constraints and
connects the logic blocks. The PAR tool takes the mapped NCD file as input The routed NCD file is then given to the BITGEN
and produces a completely routed NCD file as output having routing program to generate a bit stream (a .BIT file) which
can be used to configure the target FPGA device.
information.
Illustration
Example

• Suppose the above circuit is required to be designed on FPGA.

• The circuit will be realized after the synthesis of HDL.

• Now the design implementation software will calculate all the outputs for Sum and
Carry according to the truth table.
Example
• These outputs will be programmed to the
Lookup Tables (LUT) (SRAM) of logic cells and
that cell will be behave like logic function/gate.

• Now input to the FPGA will act as the address to

the LUT and corresponding output will come
out.
LUT (Sum)
Address Value
00 0
01 1
In Out
10 1
11 0