Symmetrical Hybrid Multilevel Inverters for Ship
Electric Propulsion Drives
Wenfeng Long Nianzhou Liu
Science and Technology on Ship Integrated Science and Technology on Ship Integrated
Power System Technology Laboratory Power System Technology Laboratory System
Wuhan, China Wuhan, China
longwenf@126.com 13407155431@139.com
Zedong Zheng
China State Key Lab. of Power
System, Dept. of Electrical
Engineering
Tsinghua University
Beijing China
zzd@tsinghua.edu.cn
Abstract—Medium voltage direct current (MVDC) based ship
integrated power system (IPS) is regarded as the future developing
trend of ship power system. Medium-voltage high power inverter
for ship electric propulsions is one of the key problem. In order to
improve the output voltage, power and harmonic performance, a
family of symmetrical hybrid multilevel inverter for open-winding
multi-phase motor based propulsion drive is presented in this
paper. Each phase of this inverter is composed of a high-frequency
multilevel DC/DC converter cell and a high-voltage H-bridge cell.
The DC/DC converter is operated at high frequency with low
voltage devices and the H-bridge is operated at fundamental
frequency with high voltage devices. All the phases are connected
to a common DC-link and each drives an isolated winding of an
open-winding motor. A symmetrical hybrid five-level topology is
taken as an example and the control method is discussed in this
paper. Simulation results demonstrate the feasibility of this
topology and control method.
Keywords—integrated power system (IPS), multilevel converter,
ship electric propulsion, voltage balance.
I. INTRODUCTION
All electric ship (AES) is the future trend for modern navy
ships due to the ever increasing power demand. Medium-voltage
direct current (MVDC) system has many advantages over
medium-voltage alternating current (MVAC) system and is
regarded as the next generation ship integrated power system
(IPS) [1]–[3]. In the MVDC system, medium-voltage high-
power inverters for electric propulsions are the most powerful
components. Conventional two-level dc–ac converter is not
suitable for high-power medium-voltage applications any more
[4]. Instead, multilevel converters receive increasing attentions
in recent years due to the ever growing demands for high power
and high voltage converters. Plenty of multilevel topologies
have been developed, and among them neutral-point-clamped
(NPC), flying-capacitor (FC) and cascaded H-bridge (CHB)
978-1-7281-3153-5/19/$31.00 ©2019 IEEE
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Kui Wang
China State Key Lab. of Power System, Dept.
of Electrical Engineering
Tsinghua University
Beijing China
wangkui@tsinghua.edu.cn
Yongdong Li
China State Key Lab. of Power
System, Dept. of Electrical
Engineering
Tsinghua University
Beijing China
liyd@tsinghua.edu.cn
multilevel converters are the most widely used topologies in the
industry [5]–[8].
Three-level NPC converter is widely used in medium-
voltage applications [6]. However, it is hard to be applied in high
voltage drives over 6 kV due to the present semiconductor
voltage ratings. Four or more -level NPC inverters are also
seldom used in industry due to the voltage imbalance problem
[9]. Compared with multilevel NPC inverters, flying-capacitor
multilevel converters do not have the voltage balance problem
[7]. The main drawback of this topology is the mass number of
clamping capacitors, which increases the system volume, weight
and control complexity tremendously. Cascaded H-bridge
(CHB) converter is widely used in high voltage applications [8].
The shortcoming of this topology is that lots of isolated DC
sources are required, which is not suitable for MVDC-based ship
IPS.
In order to increase the voltage levels and reduce the number
of clamping devices and isolated DC sources, plenty of new
multilevel topologies have been proposed based on the
combination of different types of multilevel topologies, which is
classified as hybrid multilevel topologies.
Stacked multi-cell (SMC) converter is one of the earliest
hybrid multilevel topologies [10], [11]. It can be seen as the
combination of two flying capacitor multilevel converters
stacked together. Five-level active neutral-point clamped (5L-
ANPC) converter is another hybrid multilevel topology which
can be seen as the combination of a three-level ANPC and a two-
level cell [12]–[14]. The main defect of this topology is that it
requires two switches connected in series in medium-voltage
applications, which may reduce the reliability of the inverter.
Many other topologies are also studied in the literature [15]–
[23]. However, they are not as commercialized as 5L-ANPC.
 In order to further increase the voltage levels, two multilevel
bridges can form an H-bridge to power a single phase. A five-
+ level voltage can be obtained by using a 3L-NPC H-bridge,
while a nine-level voltage can be obtained by using 5L-ANPC
X1 X2 H-bridge, as shown in Fig. 1.
+
Based on the concept of multilevel H-bridge, a family of
symmetrical hybrid multilevel inverter is presented in this paper.
A five-level symmetrical hybrid inverter is shown in Fig. 2(a)
and a nine-level symmetrical hybrid inverter is shown in Fig.
(a) 2(b) [24]. Each phase of the two inverters is composed of a
multilevel DC/DC converter cell and an H-bridge cell. The
multilevel DC/DC converter cell is operated at high frequency
S1xL S2xL
S3xL
+
S3xR
S2xR S1xR with low voltage devices such as MOSFETs or low voltage
Cd1 2E IGBTs, and the H-bridge cell is operated at fundamental
+
S3xL' S3xR' frequency with high voltage devices such as IGCTs or high
ifxL ifxR
ioxL + iNxL iNxR + ioxR voltage IGBTs.
E CfxL CfxR E
Compared the symmetrical hybrid five-level inverter in Fig.
S1xL' S2xL'
S4xL
+
S4xR
S2xR' S1xR' 2(a) with the 3L-NPC based 5L H-Bridge in Fig. 1(a), the
Cd2 2E number of switches is the same while the clamping diodes are
+ S4xR'
S4xL' eliminated. Compared the symmetrical hybrid nine-level
inverter in Fig. 2(b) with the 5L-ANPC based 9L H-bridge in
Fig. 1(b), the number of switches is also reduced. The main
(b) drawback of this topology is that the switches in the H-bridge
withstand the full DC-link voltage. However, the high voltage
Fig. 1. Multilevel H-bridge circuits: (a) 3L-NPC based 5L H-Bridge; (b) 5L-
ANPC based 9L H-Bridge.
switches in the H-bridge cell are operated at zero-voltage
switching condition, hence both the switching losses and turn-
Sx1 off surge voltage can be largely reduced. Therefore, for the
MVDC system lower than 6 kVDC, the symmetrical hybrid
five-level inverter can be used. For the MVDC system as high
idx
Cd1 + E
as 10 kVDC, the symmetrical hybrid nine-level inverter can be
Sx1'
+ Sx3 Sx4 used.
iNx iox X1 The symmetrical hybrid five-level topology is taken as an
N Sx2' Vdx Vox example and the control method is discussed in this paper. The
X2
key problem of this topology is the neutral-point (NP) voltage
Sx3' Sx4' balancing. A NP voltage balancing method based on phase-
–
Cd2 + E shifted PWM (PSPWM) is also proposed. Simulation results are
High-voltage H-bridge cell presented to demonstrate the feasibility of this topology and
control method.
Sx2 High-frequency DC/DC cell
II. OPERATING PRINCIPLES AND MODULATION METHOD
(a) In order to simplify the analysis, the five-level topology in
Sx1 Sx2 Fig. 2(a) is taken as an example in this paper. As shown in Fig.
High-voltage 2(a), the high frequency cell is composed of two half-bridges
H-bridge cell and the output voltage Vdx has three levels. For this three-level
i idx
Cfx1 + Efx1 DC/DC converter, all the switches are operated at high
Cd1+ 2E Sx1' Sx5 Sx6
Sx2' frequency and the voltage ratings are only Vdc/2. The high-
iox
voltage cell is an H-bridge and the voltage rating of four
X1
Sx3' Sx4' Vdx switches is Vdc. However, all the four switches are operated at
Vox
fundamental frequency.
X2
ifx2
Assuming the DC-link voltage is constant and equal to 2E,
Sx5' Sx6'
+ Cfx2 + E in order to output five voltage levels, the following operating
Cd2 2E
rules should be obeyed:
High frequency 1) Switches Sx1–Sx4 and Sx1'–Sx4' should be operated in a
Sx3 Sx4 DC/DC cell complementary way, respectively.
(b) 2) The H-bridge is operated with bipolar modulation. That
Fig. 2. A single phase of (a) symmetrical hybrid five-level inverter; (b) is to say, Sx3 and Sx4' are operated synchronously while
symmetrical hybrid nine-level inverter. Sx4 and Sx3' are operated synchronously.

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 Based on the above operating rules, each phase can output Equation (1) indicates that the output voltage of the high-
five voltage levels with eight distinct switching states. All the frequency cell is determined by the sum of the switching
switching states are summarized in Table I. Different switching functions Sfx1 and Sfx2. Moreover, switches Sx1 and Sx2 are
states have different effects on the neutral-point (NP) potential, independent of each other, so that classic phase-shifted PWM
which provides a high degree of freedom to balance the NP (PSPWM) can be used to control the high frequency cell. The
voltages. diagram of the modulation method is shown in Fig. 3. It can be
TABLE I SWITCHING STATES OF THE SYMMETRICAL HYBRID FIVE-LEVEL
seen that the H-bridge cell only acts when the reference voltage
INVERTER
is zero, which means the high voltage switches in the H-bridge
cell are operated at zero-voltage switching condition, hence both
Sx1 Sx2 Sx3 Sx4 Vox the switching losses and turn-off surge voltage can be largely
1 1 1 0 2E reduced.
1 0 1 0 E
0 1 1 0 E III. NP VOLTAGE BALANCING METHOD
0 0 1 0 0 A. Mathematical Model
0 0 0 1 0
One of the most important issues of this converter is the NP
0 1 0 1 –E
voltage balancing problem. A mathematical model of the NP
1 0 0 1 –E current should be established first. The instantaneous NP
1 1 0 1 –2E currents iNx can be written as:
Defining the switching functions of switches Sx1–Sx4 are
Sfx1–Sfx4, respectively, based on Table I, the instantaneous output iNx = ( Sfx2 − Sfx1 ) ⋅ idx (5)
voltage of the high frequency DC/DC cell can be written as:
Vdx = ( S fx1 + Sfx2 ) ⋅ E (1) Defining the duty ratios of Sfx1 and Sfx2 are dx1 and dx2,
respectively, based on (1), the average output voltage of the low
Then the total output voltage can be written as: voltage cell in a carrier period can be written as:
Vox = Vdx ⋅ ( S fx3 − S fx4 ) (2) udx = (d x1 + d x2 ) ⋅ E (6)
If E is selected as the base voltage value, then the range of
Vox is [–2, 2]. In order to operate Sx3 and Sx4 at fundamental If the carrier frequency is high enough, the reference signal
frequency, Sfx3 can be decided as follows: can be regarded as a constant in a carrier period. Then the duty
ratio of Sfx1 and Sfx2 in a carrier period can be written as:
0, uox ≤ 0
Sfx3 =  , (3) d x1 = d x2 = urefx / 2 (7)
1, uox > 0

where uox is the reference output phase voltage. Then the Based on (5), when PSPWM is used, the average NP current
reference modulation voltage urefx for the high frequency cell can in a carrier period can be written as:
be written as follows:
i Nx = ( d x2 − d x1 ) ⋅ idx (8)
u refx =| uox | (4)
From (7) and (8) it can be seen that the average NP current
urefx in a carrier period is zero, which indicates that the NP voltage
can be naturally balanced in a carrier period under ideal and
steady-state conditions.
uox Sfx3 B. NP voltage balancing method
Although the NP voltage can be naturally balanced under
Sfx1 ideal and steady conditions, it also may diverge under non-ideal
and dynamic conditions if not controlled.
Sfx2
The voltage ripple affected by a single phase can be written
Vdx
as follows:

ud1 − ud2 i Nx ⋅ Ts T
Vox
Δu Nx = = = s (d x2 − d x1 ) ⋅ idx (9)
2 2Cd 2Cd

where Cd is the capacitance of upper and lower DC-link

capacitors. From (9) it can be seen, a way to regulate the NP
voltage is to adjust the duty cycles of Sfx1 and Sfx2, which varies
Fig. 3. Diagram of the modulation method. the operation time of redundant switching states essentially. So

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the PSPWM method should be modified slightly to achieve this
goal.
If sign(ΔuNx * idx) > 0, according to (9), the duty ratio of Sfx2
should be decreased and the duty ratio of Sfx1 should be
increased. In order to not affect the output voltage and other
capacitor currents, the modified duty ratios of Sfx1 and Sfx2 can
be written as:

 ' 1
d x1 = d x1 − 2 Δd x
 (10)
d ' = d + 1 Δd
 x2 x2
2
x

Thus, the average NP current is as follows:

i Nx = (dx2' − dx1' ) ⋅ idx = Δdx ⋅ idx (11)

Fig. 5. Five-level phase voltage.

Δdx is very small and can be controlled by a PI regulator, so

the harmonic spectrum of the output phase voltage will not be
affected.
IV. SIMULATION RESULTS
In order to demonstrate the performance of the proposed
control method, a 5 kVDC/12 MVA five-phase symmetrical
hybrid five-level inverter is simulated in MATLAB/Simulink
environment. The circuit structure is shown in Fig. 4. All the
parameters used for simulation are summarized in Table II
Phase E

Phase D

Phase C

Phase B

Sx1 Phase A

+
Cd1
Sx3 Sx4
Sx1'

iox
Fig. 6. Five-phase currents
X1 Vox
Vdc Sx2'
N
X2

Sx3' Sx4' Open-Winding five-

Cd2 +
phase load

Sx2

Fig. 4. Circuit diagram of the symmetrical hybrid five-level inverter with a

five-phase load.

TABLE II CIRCUIT PARAMETERS USED FOR SIMULATION

Parameters Value
Rated volume 12 MVA
DC-link voltage Udc = 5000 V
Phases 5
DC-link capacitor Cd1 = Cd2 =2000 μF
Carrier frequency fc = 1 kHz
Load R = 2 Ω, L = 4 mH
Fig. 7. Voltages across the two dc-link capacitors

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Fig. 8. Detailed waveforms of the dc-link capacitor voltages.
Fig. 9. DC-link capacitor voltages and phase currents under different
modulation indexes.
Fig. 5 shows the phase voltage and Fig. 6 shows the five-
phase currents. Fig. 7 shows the DC-link capacitor voltages. The
two capacitor voltages are balanced at their nominal values,
which demonstrates the effectiveness of the proposed NP
voltage balancing method. Fig. 8 shows the detailed waveforms
of DC-link capacitor voltages. It can be observed that there is
only a carrier-frequency ripple in the capacitor voltages,
therefore the DC-link capacitor value can be very small.
Fig. 9 shows the NP voltage balancing performance under
different modulation indexes. The modulation index is stepped
up from 0.2 to 0.4, 0.6, 0.8 and 1.0 gradually. During the whole
process, the dc-link capacitor voltages are balanced very well,
which demonstrates the effectiveness of the proposed NP
voltage balancing method.
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V. CONCLUSIONS
This paper introduced a symmetrical hybrid multilevel
topology for multi-phase open-winding motor based ship
electric propulsions, including a five-level inverter and a nine-
level inverter. Each phase of this topology is composed of a
multilevel DC/DC converter cell and an H-bridge cell. The
multilevel DC/DC converter cell is operated at high frequency
with low voltage devices and the H-bridge cell is operated at
fundamental frequency with high voltage devices.
The symmetrical hybrid five-level topology is taken as an
example, and the operating principles and modulation method of
this inverter is introduced and a NP voltage balancing method
based on modified PSPWM is proposed. Simulation results
demonstrate the effectiveness of this voltage balancing method.
REFERENCES
[1] J. S. Thongam, M. Tarbouchi, A. F. Okou, D. Bouchard, and R.
Beguenane, "All-electric ships-A review of the present state of the art," in
2013 Eighth International Conference and Exhibition on Ecological
Vehicles and Renewable Energies (EVER), 2013, pp. 1-8.
[2] J. F. Hansen and F. Wendt, "History and State of the Art in Commercial
Electric Ship Propulsion, Integrated Power Systems, and Future Trends,"
Proceedings of the IEEE, vol. 103, no. 12, pp. 2229-2242, 2015.
[3] C. Su, K. Lin and C. Chen, "Power Flow and Generator-Converter
Schemes Studies in Ship MVDC Distribution Systems," IEEE
Transactions on Industry Applications, vol. 52, no. 1, pp. 50-59, 2016.
[4] G. Oriti and R. M. Cuzner, "Ship Propulsion AC/DC Conversion System
Modeling and Design," in Conference Record of the 2006 IEEE Industry
Applications Conference Forty-First IAS Annual Meeting, 2006, pp. 569-
575.
[5] S. Fazel, S. Bernet, D. Krug, and K. Jalili, “Design and comparison of 4-
kV neutral-point-clamped, flying-capacitor, and series-connected H-
bridge multilevel converters,” IEEE Trans. Ind. Appl., vol. 43, no. 4, pp.
1032–1040, July/August 2007.
[6] J. Rodriguez, S. Bernet, P. Steimer, and I. Lizama, “A survey on neutral-
point-clamped inverters,” IEEE Trans. Ind. Electron., Vol. 57, no. 7, pp.
2219–2230, July 2010.
[7] T. A. Meynard, M. Fadel and N. Aouda, “Modeling of multilevel
converters,” IEEE Trans. Ind. Electron., vol. 44, no. 3, pp. 356-364, June
1997.
[8] M. Malinowski, K. Gopakumar, J. Rodriguez, X. Pe and M. A. Rez, “A
Survey on Cascaded Multilevel Inverters, ” IEEE Trans. Ind. Electron.,
Vol. 57, no. 7, pp. 2197-2206, July 2010.
[9] N. Hatti, Y. Kondo and H. Akagi, “Five-Level Diode-Clamped PWM
Converters Connected Back-to-Back for Motor Drives,” IEEE Trans. Ind.
Appl., vol. 44, no. 4, pp. 1268-1276, July/Aug. 2008.
[10] A. M. Y. M. Ghias, J. Pou and V. G. Agelidis, "An Active Voltage-
Balancing Method Based on Phase-Shifted PWM for Stacked Multicell
Converters," IEEE Trans. Power Electron., vol. 31, no. 3, pp. 1921-1930,
March 2016.
[11] A. M. Y. M. Ghias, J. Pou, P. Acuna, S. Ceballos, A. Heidari, V. G.
Agelidis, and A. Merabet, “Elimination of Low-Frequency Ripples and
Regulation of Neutral-Point Voltage in Stacked Multicell Converters,”
IEEE Trans. Power Electron., vol. 32, no. 1, pp. 164-175, Jan. 2017.
[12] P. Barbosa, P. Steimer, J. Steinke, L. Meysenc, M. Winkelnkemper, and
N. Celanovic, “Active neutral-point-clamped (ANPC) multilevel
converter technology,” in Proc. Conf. Rec. EPE, 2005, CDROM.
[13] K. Wang, Z. Zedong, Y. Li, K. Liu, and J. Shang, “Neutral-Point Potential
Balancing of a Five-Level Active Neutral-Point-Clamped Inverter,” IEEE
Trans. Ind. Electron., vol. 60, no. 5, pp. 1907-1918, May 2013.
[14] Z. Liu, Y. Wang, G. Tan, H. Li, Y. Zhang, “A Novel SVPWM Algorithm
for Five-Level Active Neutral-Point-Clamped Converter,” IEEE Trans.
Power Electron., vol.31, no. 5, pp. 3859-3866, May 2016.
[15] K. Tian, B. Wu, M. Narimani, D. D. Xu, Z. Cheng, and N. Reza Zargari,
“A Capacitor Voltage-Balancing Method for Nested Neutral Point
Clamped (NNPC) Inverter,” IEEE Trans. Power Electron., vol. 31, no. 3,
pp. 2575-2583, March 2016.
[16] K. Wang, Z. Zheng, L. Xu, and Y. Li, “A Four-level Hybrid-Clamped
Converter With Natural Capacitor Voltage Balancing Ability,” IEEE
Trans. Power Electron., vol. 29, no. 3, pp. 1152-1162, March 2014.
[17] K. Wang, Z. Zheng, L. Xu, and Y. Li, “Voltage Balancing Control of a
Four-Level Hybrid-Clamped Converter Based on Zero-Sequence Voltage
Injection Using Phase-Shifted PWM”, IEEE Trans. Power Electron., vol.
31, no. 8, pp. 5389-5399, Aug. 2016.
[18] M. D. Manjrekar, P. K. Steimer and T. A. Lipo, “Hybrid multilevel power
conversion system: a competitive solution for high-power applications,”
IEEE Trans. Ind. Appl., vol. 36, no. 3, pp. 834-841, May/June 2000.
[19] C. Rech and J. R. Pinheiro, “Hybrid Multilevel Converters: Unified
Analysis and Design Considerations,” IEEE Trans. Ind. Electron., vol. 54,
no. 2, pp. 1092-1104, April 2007.
Authorized licensed use limited to: UNIVERSITY OF WESTERN ONTARIO. Downloaded on July 27,2020 at 10:42:43 UTC from IEEE Xplore. Restrictions apply.
[20] M. Veenstra and A. Rufer, “Control of a hybrid asymmetric multilevel
inverter for competitive medium-voltage industrial drives,” IEEE Trans.
Ind. Appl., vol. 41, no. 2, pp. 655-664, March/April 2005.
[21] Y. Zhang, G. P. Adam, T. C. Lim, S. J. Finney, and B. W. Williams,
“Hybrid Multilevel Converter: Capacitor Voltage Balancing Limits and
its Extension,” IEEE Transactions on Industrial Informatics, vol. 9, no. 4,
pp. 2063-2073, Nov. 2013.
[22] G. Su, “Multilevel DC-link inverter,” IEEE Trans. Ind. Appl., vol. 41, no.
3, pp. 848- 854, May/June 2005.
[23] Z. Zheng, K. Wang, L. Xu, and Y. Li, “A Hybrid Cascaded Multilevel
Converter for Battery Energy Management Applied in Electric Vehicles,”
IEEE Trans. Power Electron., vol. 29, no. 7, pp. 3537-3546, July 2014
[24] K. Wang, Y. Li, Z. Zheng, D. Wei, and B. Fan, “A symmetrical hybrid
nine-level inverter for high speed open-winding motor drive system,” in
proc. 2016 IEEE Energy Conversion Congress and Exposition (ECCE),
2016, pp. 1-6.