Finite State Machines

BECE102L
DIGITAL SYSTEM DESIGN

Module-6
Design of FSM
Part-1
Module-6 (Design of FSM)
Finite state Machine(FSM): Mealy FSM and Moore FSM, Design
Example : Sequence detection, Modeling of FSM using Verilog HDL.
(4 hours)
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Content
• Finite state Machine(FSM):
• Mealy FSM and
• Moore FSM
• Design Example
• Sequence detection.
3
Finite State Machines (FSM)
• A state machine is a sequential circuit having a limited (finite) number of states
occurring in a prescribed order.
• A counter is an example of a state machine; the number of states is called the
modulus.
• Two basic types of state machines are the Moore and the Mealy.
• The Moore state machine is one where the outputs depend only on the internal
present state.
• The Mealy state machine is one where the outputs depend on both the internal
present state and on the inputs.
• Both types have a timing input (clock) that is not considered a controlling input.
4
General Model of FSM
A typical sequential system is composed of
• Inputs
• Internal state of the system stored in the
memory elements
• Outputs
• Next state decoder
• Output decoder
• In a FSM, Both the next state and output
are functions of the input and current state
Next state = G (Input, current state)
Output = F (Input, current state)
General Model of FSM
5
Classification of FSM
The FSM are classified into 5 different types, they are
• Class A machine
• Class B machine
• Class C machine
• Class D machine
• Class E machine
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Class A Machine (Mealy Machine)
• The Mealy machine output is a
function of the present input and
the current state of machine.
• Serial Adders and fundamental
mode Asynchronous circuits fall
under this category.
Block Diagram of Mealy Machine

7
Moore Machines (Class B and Class C)
• In Moore machines, the output is depending
only on the current state (present state).
• Types are
• Class B and
• Class C
Class B Moore Machine

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Moore Machines (Class B and Class C)
• In Moore machines, the output is
depending only on the current state
(present state).
• Types are
• Class B and
• Class C
• Example
• Counters
Class C Moore Machine

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Class D and Class E machines
• Neither Moore nor Mealy type.
Class D and Class E Machines

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Moore-Mealy FSM Comparison
S. No. Mealy Machine Moore Machine
1 Output depends both upon the present Output depends only upon the present
state and the present input state.
2 Generally, it has fewer states than Generally, it has more states than Mealy
Moore Machine. Machine.
3 The value of the output function is a The value of the output function is a
function of the transitions and the function of the current state and the
changes, when the input logic on the changes at the clock edges, whenever
present state is done. state changes occur.
4 Mealy machines react faster to inputs. In Moore machines, more logic is
They generally react in the same clock required to decode the outputs resulting
cycle. in more circuit delays. They generally
react one clock cycle later.
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Design steps of FSM
The steps involved in the design of FSM are given below.
1. Understand the problem and determine the number of states needed.
2. Draw the state diagram.
3. Make the state table based on the state diagram.
4. Design the next state decoder and the output decoder using the state
table as the truth table.
5. Simplify the functions by K-map, and implement the next state and
output decoders at logic gate level.
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Moore Machine-Example
• The output is a function
of the present state only.
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• The next-state values can also be obtained by evaluating the state
equations from the characteristic equation.
• This is done by using the following procedure:
1. Determine the flip-flop input equations in terms of the present state
and input variables.
2. Substitute the input equations into the flip-flop characteristic
equation to obtain the state equations.
3. Use the corresponding state equations to determine the next-state
values in the state table.
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• The output is a function of the present state only.
• From Circuit Diagram, the State Equations are
𝐴 𝑡 + 1 = 𝐵𝐴′ + 𝐵𝑥 ′ ′ 𝐴 = 𝐴′ 𝐵 + 𝐴𝐵′ + 𝐴𝑥 (1)
𝐵 𝑡 + 1 = 𝑥 ′ 𝐵′ + 𝐴⨁𝑥 ′ 𝐵 = 𝐵′ 𝑥 ′ + 𝐴𝐵𝑥 + 𝐴′ 𝐵𝑥′ (2)
SR FF : 𝑸 𝒏 + 𝟏 = 𝑺 + 𝑹′ 𝑸
D FF : 𝑸 𝒏 + 𝟏 = 𝑫
JK FF : 𝑸 𝒏 + 𝟏 = 𝑱𝑸′ + 𝑲′ 𝑸
T FF : 𝑸 𝒏 + 𝟏 = 𝑻𝑸′ + 𝑻′ 𝑸
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𝑄𝑛 𝑄𝑛+1 𝐽 𝐾
0 0 0 X
Moore Machine-Example 0 1 1 X
• The output is a function of the present state only. 1 0 X 1
1 1 X 0
• State Table.
Present State Input Next State FF Inputs
S. No.
A B x A B 𝐽𝐴 𝐾𝐴 𝐽𝐵 𝐾𝐵
1 0 0 0 0 1 0 X 1 X
2 0 0 1 0 0 0 X 0 X
3 0 1 0 1 1 1 X X 0
4 0 1 1 1 0 1 X X 1
5 1 0 0 1 1 X 0 1 X
6 1 0 1 1 0 X 0 0 X
7 1 1 0 0 0 X 1 X 1
8 1 1 1 1 1 X 0 X 0
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• The State Diagram is
𝐴 𝑡 + 1 = 𝐵𝐴′ + 𝐵𝑥 ′ ′ 𝐴 = 𝐴′ 𝐵 + 𝐴𝐵′ + 𝐴𝑥 (1)
𝐵 𝑡 + 1 = 𝑥 ′ 𝐵′ + 𝐴⨁𝑥 ′ 𝐵 = 𝐵′ 𝑥 ′ + 𝐴𝐵𝑥 + 𝐴′ 𝐵𝑥′ (2)
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Mealy Machine Example
• Output y is a function of both input
x and the present state of A and B.
• State Equation.
• State Table.
• State Diagram.
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• Output y is a function of both input x and the present state of A and B.
• State Equations are derived from Logic Diagram as follows
A 𝑡 + 1 = 𝐴𝑥 + 𝐵𝑥 (1)
𝐵 𝑡 + 1 = 𝐴′ 𝑥 (2)
𝑦 = 𝐴 + 𝐵 𝑥′ (3)
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• From State Equations, the PS-NS table can be arrived.
Present State Input Next State Output

S. No.
A B X A B Y
1 0 0 0 0 0 0
2 0 0 1 0 1 0
3 0 1 0 0 0 1
4 0 1 1 1 1 0
5 1 0 0 0 0 1
6 1 0 1 1 0 0
7 1 1 0 0 0 1
8 1 1 1 1 0 0
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• The state table can be represented in more compact form.
Next State Output

Present State
S. No. X=0 X=1 X=0 X=1
A B A B A B y y
1 0 0 0 0 0 1 0 0
2 0 1 0 0 1 1 1 0
3 1 0 0 0 1 0 1 0
4 1 1 0 0 1 0 1 0
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• The State Diagram is
A 𝑡 + 1 = 𝐴𝑥 + 𝐵𝑥
𝐵 𝑡 + 1 = 𝐴′ 𝑥
𝑦 = 𝐴𝑥 ′ + 𝐵𝑥 ′ → 𝑦 = 𝐴 + 𝐵 𝑥′
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Sequence Detection
• The sequence detector is a single input circuit that will accept a stream of bits and
generate an output “1” whenever the particular sequence is detected.
• Two types
1. Non-overlapping
2. Overlapping
• To detect sequence 111 from incoming sequence 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1.
• Circuit produces an output “1” when it finds 3 or more consecutive 1’s in the input
sequence.
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Sequence Detection-Mealy type
Design a circuit that detects a sequence of three or more consecutive 1’s in a string
of bits coming through an input line.
• Consider the example sequence 11011101111.
• The state Diagram is
• Let the initial state is 𝑆0 .
• When it receives 1 as input goes to Another state 𝑆1 and output is 0.
• From 𝑆1 it goes to 𝑆2 if it receives 1 otherwise goes to 𝑆0 and output is 0.
• From 𝑆2 it goes to 𝑆3 if it receives 1 and output is 1,
otherwise goes to 𝑆0 and output is 0.
• The output remains at 0 till it gets 3 consecutive 1’s.
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Example: Sequence Detector
• The state diagram in its more compact form with unique name for each and every
states.
• From the diagram, it requires 4 states namely
𝑆0 , 𝑆1 , 𝑆2 𝑎𝑛𝑑 𝑆3
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• To design the circuit, binary codes to the states must be assigned.
• State Assignment can be done in 3 ways.
• We choose two flip-flops to represent the four states, and we label their outputs A
and B.
S. No. State Variable Binary Code Gray code One-Hot Code

1 𝑆0 00 00 0001
2 𝑆1 01 01 0010
3 𝑆2 10 11 0100
4 𝑆3 11 10 1000
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• Next step is finding State Table with inputs, Outputs, Present State and Next State
information. The state table is derived from the state diagram.
• Using Binary State Assignment, the PS-NS Table is constructed.
• There is one input x and one output y.
• Must choose type of FF to find excitation to the FF using PS-NS and input.
• Here, D FF is chosen for Simplicity.
• The characteristics equation of D FF is
𝑄 𝑡 + 1 = 𝐷(𝑡) (1)
• The next-state values in the state table specify the D input condition for the flip-
flop.
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• The State table is.
Present State Input Next State Output
S. No.
A B x A B y
0 0 0 0 0 0 0
1 0 0 1 0 1 0
2 0 1 0 0 0 0
3 0 1 1 1 0 0
4 1 0 0 0 0 0
5 1 0 1 1 1 0
6 1 1 0 0 0 1
7 1 1 1 1 1 1
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• Next step is choosing proper FF’s to implement the circuit.
• Here, D FF is chosen for Simplicity.
• The characteristics equation of D FF is
𝑄 𝑡 + 1 = 𝐷(𝑡) (1)
• The next-state values in the state table specify the D input condition for the flip-
flop.
• Using PS-NS values, the input to the FF’s can be predicted.
• The table which maps PS-NS with input is called as Synthesis table.
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• Synthesis using D FF. In D FF 𝐷 𝑡 =𝑄 𝑡+1
Present State Input Next State Output D FF inputs
S. No.
A B x A+ B+ y 𝐷𝐴 𝐷𝐵
1 0 0 0 0 0 0 0 0
2 0 0 1 0 1 0 0 1
3 0 1 0 0 0 0 0 0
4 0 1 1 1 0 0 1 0
5 1 0 0 0 0 0 0 0
6 1 0 1 1 1 0 1 1
7 1 1 0 0 0 1 0 0
8 1 1 1 1 1 1 1 1
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Synthesis using D FF.
• The FF input equation can be obtained directly from the next-state columns of A
and B and expressed in sum-of- minterms form using K-map like methods.
• The minterms are
𝐴 𝑡 + 1 = 𝐷𝐴 𝐴, 𝐵, 𝑥 = Σ(3, 5, 7)
𝐵 𝑡 + 1 = 𝐷𝐵 𝐴, 𝐵, 𝑥 = Σ(1, 5, 7)
𝑦 𝐴, 𝐵, 𝑥 = Σ(6, 7)
• Using K-map with A, B and x as Input and A(t+1), B(t+1) and y as output, the
simplified expression can be obtained.
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Bx 0 0 01 11 10
Sequence Detection-Mealy type A
0 1 3 2
0 1
Synthesis using D FF. 4 5 7 6
1 1 1
• Simplification using K-map.
• The simplified expressions are Bx 0 0 01 11 10
𝐷𝐴 = 𝐴𝑥 + 𝐵𝑥 A
0 1 3 2
𝐷𝐵 = 𝐴𝑥 + 𝐵′ 𝑥 0 1
4 5 7 6
𝑦 = 𝐴𝐵 1 1 1
Bx 0 0 01 11 10
A
0 1 3 2
0
4 5 7 6
1 1 1
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Schematic Diagram using D FF.
𝐷𝐴 = 𝐴𝑥 + 𝐵𝑥
𝐷𝐵 = 𝐴𝑥 + 𝐵′ 𝑥
𝑦 = 𝐴𝐵
33
• Design a Mealy type sequence detector to detect 101 from given serial input data
using D FF..
• For state diagram of the overlapping type sequence detector is
• The state assignments are
A00, B01, C10. 0/0
1/1
A B C
1/0 0/0
1/0
0/0
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(101) overlapping Mealy type
• The state table with PS –NS details is is
S. No.
𝑄𝐴 𝑄𝐵 x 𝑄𝐴 + 𝑄𝐵 + y 𝐷𝐴 𝐷𝐵
1 0 0 0 0 0 0 0 0
2 0 0 1 0 1 0 0 1
3 0 1 0 1 0 0 1 0
4 0 1 1 0 1 0 0 1
5 1 0 0 0 0 0 0 0
6 1 0 1 0 1 1 0 1
7 1 1 0 X X X X X
8 1 1 1 X X X X X
35
• The K-maps for 𝐷𝐴 and 𝐷𝐵 is (101) overlapping Mealy type
QBx 0 0 01 11 10
QA
0 0 0 0 1
𝐷𝐴 = 𝑄𝐵 𝑥′
1 0 0 X X
QBx 0 0 01 11 10
QA
0 0 1 1 0
𝐷𝐵 = 𝑥
1 0 1 X X
36
• The K-maps for output y is (101) overlapping Mealy type
QBx 0 0 01 11 10
QA
0 0 0 0 0
𝑦 = 𝑄𝐴 𝑥
1 0 1 X X
37
• The logic diagram is (101) overlapping Mealy type
𝐷𝐵 = 𝑥
38
• Design a Mealy type sequence detector to detect 101 from given serial input data
using D FF..
• For state diagram of the Non- overlapping type sequence detector is
• The state assignments are
1/1
A00, B01, C10.
0/0
A B C
1/0 0/0
1/0
0/0
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(101) Non-overlapping Mealy type
S. No.
1 0 0 0 0 0 0 0 0
2 0 0 1 0 1 0 0 1
3 0 1 0 1 0 0 1 0
4 0 1 1 0 1 0 0 1
5 1 0 0 0 0 0 0 0
6 1 0 1 0 0 1 0 0
7 1 1 0 X X X X X
8 1 1 1 X X X X X
40
• The K-maps for 𝐷𝐴 and 𝐷𝐵 is
QBx 0 0 01 11 10
QA
0 0 0 0 1
1 0 0 X X
QBx 0 0 01 11 10
QA
0 0 1 1 0
𝐷𝐵 = 𝑄𝐴 ′𝑥
1 0 0 X X
41
(101) Non-verlapping Mealy type
• The K-maps for output y is
QBx 0 0 01 11 10
QA
0 0 0 0 0
1 0 1 X X
42
• The logic diagram is
𝐷𝐵 = 𝑄𝐴 ′𝑥
43
Sequence Detection-Moore type
• Design a Moore type sequence detector to detect 101 from given serial input data
using D FF..
• For state diagram of the Non- overlapping type sequence detector is
• The state assignments are 1
A00, B01, C10, D11.
0
𝐴 𝐵 𝐶 𝐷
0 0 0 1
1 0 1
1
0 0
44
(101) Non-overlapping Moore type
S. No.
1 0 0 0 0 0 0 0 0
2 0 0 1 0 1 0 0 1
3 0 1 0 1 0 0 1 0
4 0 1 1 0 1 0 0 1
5 1 0 0 0 0 0 0 0
6 1 0 1 1 1 0 1 1
7 1 1 0 0 0 1 0 0
8 1 1 1 0 1 1 0 1
45
• x QBx 0 0 01 11 10
QA
0 0 0 0 1
𝐷𝐴 = 𝑄𝐴′ 𝑄𝐵 𝑥 ′ + 𝑄𝐴 𝑄𝐵′ 𝑥
1 0 1 0 0
QBx 0 0 01 11 10
QA
0 0 1 1 0
𝐷𝐵 = 𝑥
1 0 1 1 0
46
QBx 0 0 01 11 10
QA
0 0 0 0 0
𝑦 = QAQB
1 0 0 1 1
47
𝐷𝐴 = 𝑄𝐴′ 𝑄𝐵 𝑥 ′ + 𝑄𝐴 𝑄𝐵′ 𝑥
𝐷𝐵 = 𝑥
𝑦 = QAQB
48
• Design a Moore type sequence detector to detect 101 from given serial input data
using D FF..
• For state diagram of the overlapping type sequence detector is
• The state assignments are 1
A00, B01, C10, D11.
0
𝐴 𝐵 𝐶 𝐷
0 0 0 1
1 0 1
1
0
0
49
(101) overlapping Moore type
S. No.
1 0 0 0 0 0 0 0 0
2 0 0 1 0 1 0 0 1
3 0 1 0 1 0 0 1 0
4 0 1 1 0 1 0 0 1
5 1 0 0 0 0 0 0 0
6 1 0 1 1 1 0 1 1
7 1 1 0 1 0 1 0 0
8 1 1 1 0 1 1 0 1
50
• x QBx 0 0 01 11 10
QA
0 0 0 0 1
𝐷𝐴 = 𝑄𝐵 𝑥 ′ + 𝑄𝐴 𝑄𝐵′ 𝑥
1 0 1 0 1
QBx 0 0 01 11 10
QA
0 0 1 1 0
𝐷𝐵 = 𝑥
1 0 1 1 0
51
QBx 0 0 01 11 10
QA
0 0 0 0 0
𝑦 = QAQB
1 0 0 1 1
52
𝐷𝐴 = 𝑄𝐵 𝑥 ′ + 𝑄𝐴 𝑄𝐵′ 𝑥
𝐷𝐵 = 𝑥
𝑦 = QAQB
53
Sequence Detection-Practice problems
• Sequence detector to detect 1101.
54
Sequence Detection
• Sequence detector to detect 0101.
1/0
1/0
𝑆0 𝑆1 𝑆2 𝑆3
0/0 1/0 0/0
0/0 1/1
0/0
55
Sequence Detection-Verilog
• Sequence detector to detect 1101 Moore Non-overlapping.
0
𝐴 𝐵 𝐶 𝐷 𝐸
0
0 0 0 0 1 1
1 1 0
1
0 1
56
Sequence Detection-Verilog
Next State Output
Present State D FF inputs
S. X=0 X=1 X=0 X=1
No.
𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐴 𝑄𝐵 𝑄𝐶
𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑦 𝑦 𝐷𝐴 𝐷𝐵
+ + + + + +
1 0 0 0 0 0 0 0 0 1 0 0
2 0 0 1 0 0 0 0 1 0 0 0
3 0 1 0 0 1 1 0 1 0 0 0
4 0 1 1 0 0 0 1 0 0 0 0
5 1 0 0 0 0 0 0 0 1 1 1
57
Sequence Detection-Verilog HDL
module sd1101_moore(clk, reset, din, dout, begin

state); case(state)
input clk, reset, din; 3'b000: begin
output reg dout; dout <=1'b0;
output reg [2:0] state=3'b000; if(din==1)
state <= 3'b001;
always @(posedge clk) end
begin 3'b001: begin
if(reset) dout <= 1'b0;
begin if(din==1)
dout <= 1'b0; state <= 3'b010;
state <= 3'b000; else
end state <= 3'b000;
else end
58
3'b010: begin 3'b100: begin

dout <= 1'b0; dout <= 1'b1;
if(din==1) if(din==1)
state <= 3'b010; state <= 3'b001;
else else
state<=3'b011; state <= 3'b000;
end end
3'b011: begin endcase
dout <= 1'b0; end
if(din==1) end
state <= 3'b100;
else
state <= 3'b000; endmodule
end
59
Sequence Detection-Verilog HDL-TB
module sd1101_moore_tb; #2 din=0;

reg clk, reset, din; #6 din=1;
wire dout; #2 din=1;
sd1101_moore uut(clk, reset, din, dout); #2 din=0;
initial begin #2 din=1;
clk=0; end
forever #2 clk=~clk; endmodule
end
initial begin
reset=1;
din=0;
#2 reset=0;
#2 din=1;
#6 din=1;
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Summary
• FSM and its types.
• Moore machine design
• Mealy Machine design
• Sequence Detectors.
62
63

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BECE102L

DIGITAL SYSTEM DESIGN

Block Diagram of Mealy Machine

Class B Moore Machine

Class C Moore Machine

Class D and Class E Machines

𝐵 𝑡 + 1 = 𝑥 ′ 𝐵′ + 𝐴⨁𝑥 ′ 𝐵 = 𝐵′ 𝑥 ′ + 𝐴𝐵𝑥 + 𝐴′ 𝐵𝑥′ (2)

𝐵 𝑡 + 1 = 𝑥 ′ 𝐵′ + 𝐴⨁𝑥 ′ 𝐵 = 𝐵′ 𝑥 ′ + 𝐴𝐵𝑥 + 𝐴′ 𝐵𝑥′ (2)

Present State Input Next State Output

Next State Output

S. No. State Variable Binary Code Gray code One-Hot Code

module sd1101_moore(clk, reset, din, dout, begin

3'b010: begin 3'b100: begin

module sd1101_moore_tb; #2 din=0;

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