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Lecture09 Ee620 Digital PLLs
Lecture09 Ee620 Digital PLLs
Lecture09 Ee620 Digital PLLs
Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• HW3 due Oct 31
2
Agenda
• Digital PLL Overview
• Linear Model
• Design Procedure
• Noise Analysis
• Time-to-Digital Converters
• Conclusion
3
References
• Techniques for High-Performance Digital
Frequency Synthesis and Phase Control,
C.-M. Hsu, MIT Thesis, 2008.
4
Analog PLL Issues
PFD
D UP ICP
Q
in R
Vctrl
VCO out
fb R DN
Q R C2
D
ICP
C1
Divider
1/N
6
Digital PLL
Digital Loop Filter
DCO
in
TDC DAC VCO out
fb
Z-1
Divider
1/N
8
Digital PLL Model
TDC DCO
TDC Loop DAC
Gain Filter Gain DT-CT
in[k] T 1 VFS KVCO
H(z) T out(t)
2 t 2B j2f
z=ej2fT
fb[k]
CT-DT
1 1
N T
[Hsu Thesis 2018]
Divider
t
in(t)
e[k]
• TDC converts the time difference between the input and feedback
clocks to a digital code at a resolution t
1
TDC Gain = with units of 𝑠
∆
• Phase-domain model requires an initial scaling factor to convert the
input phase error to a timing error
𝑇
𝑡 𝜙
2𝜋
𝑇
Effective TDC Gain = with units of 𝑟𝑎𝑑
2𝜋∆ 10
Digital Loop Filter
Analog Filter Transfer Function
IN OUT 1
𝑅 𝑠
𝐹 𝑠
𝑅𝐶
𝑠
CLK
w/ Bilinear Transform
𝛽 𝛽
𝛼 𝑠
2 𝛽
𝑂𝑈𝑇 𝛽 𝛼 𝑇
2
𝐻 𝑧 𝛼 𝐻 𝑠
𝐼𝑁 1 𝑧 𝑠
𝑇 𝑇
𝛼 𝑅 𝛽
2𝐶 𝐶
11
DCO Model
VFS
R/2
DCO
R
DAC
VCO out Gain DT-CT
R
VFS KVCO
DCO[k] T out(t)
R/2
2B j2f
DCO[k] Decoder
B
1 1
N T
Divider
𝛼 𝛽 𝛼𝑧 𝛼 𝛽 𝛼𝑒
𝐻 𝑧 𝐻 𝑒
1 𝑧 1 𝑒
𝑇 1 𝑉 𝐾
𝜙 𝑁 · 𝑇 · 𝐿𝐺 𝑓 𝑇 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓
𝜙 1 𝐿𝐺 𝑓 𝑇 1 𝑉 𝐾 1
1 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁
13
DT & CT Spectral Density Calculations
Since 𝐻 𝑓 is computed with a DT input, a CT 𝑆 𝑓 must be first converted to a
1
DT 𝑆 𝑒 by scaling with
𝑇
CT-DT
1 Sx(ej2fT)
Sx(f) H(f) Sy(f)
T
1
𝑆 𝑒 𝑆 𝑓
𝑇
Computing a CT 𝑆 𝑓 output with a DT 𝑆 𝑒 input through 𝐻 𝑓 requires
1
scaling by 1
𝑇 𝑆 𝑓 𝐻 𝑓 𝑆 𝑒
𝑇
Total system output with 𝑆 𝑓
1
𝑆 𝑓 𝐻 𝑓 𝑆 𝑓
𝑇 14
14GHz Digital PLL
Closed-Loop Transfer Function (Initial Design)
Parameter
Fref 156.25MHz
N 90
Fvco 14GHz
fu 2MHz
m 60°
f3dB 2.7MHz
t 10ps
2π*1MHz/LSB
(VFS/2B)Kvco
(10b)
1.49
7.11e-2
𝑇 1 𝑉 𝐾
𝜙 𝑓 1 𝑇 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓
𝜙 𝑓 𝑇 𝑇 1 𝑉 𝐾 1
1 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁
15
Digital PLL Loop Gain
TDC DCO
TDC Loop DAC
Gain Filter Gain DT-CT
in[k] T 1 VFS KVCO
H(z) T out(t)
2 t 2B j2f
z=ej2fT
fb[k]
CT-DT
1 1
N T
Divider
𝑇 1 𝑉 𝐾 1
𝐿𝐺 𝑓 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁
16
Agenda
• Digital PLL Overview
• Linear Model
• Design Procedure
• Noise Analysis
• Time-to-Digital Converters
• Conclusion
17
Second-Order Digital PLL Design Procedure
• Design the digital PLL to emulate a second-order analog
charge-pump PLL [Kratyuk TCAS2 2007]
Digital PLL Analog PLL
𝑇 1 𝑉 𝐾 1 𝐼 𝑅 𝑠 𝜔 𝐾 1
𝐿𝐺 𝑓 𝐻 𝑒 ⟺ 𝐿𝐺 𝑠
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁 2𝜋 𝑠 𝑠 𝑁
𝑇 1 𝐼
Digital PLL PDC Gain ⟺ Analog PLL PFD Gain
2𝜋 Δ 2𝜋
18
Second-Order Digital PLL Design Procedure
1. Set z based on u and m specs PLL Specs
𝜔
𝜔 Parameter
tan Φ Fref 156.25MHz
𝑉 2𝜋 ∗ 1𝑀𝐻𝑧
𝑁 90 & 𝐾 →𝑅 1.53Ω
2 𝐿𝑆𝐵 19
Second-Order Digital PLL Design Procedure
4. Set an equivalent C value to achieve z PLL Specs
1 Parameter
𝐶
𝜔 𝑅 Fref 156.25MHz
N 90
𝐶 90.1𝑛𝐹 Fvco 14GHz
fu 2MHz
5. Compute and from equivalent m 60°
R and C values
t 10ps
𝑇 𝑇 2π*1MHz/LSB
𝛼 𝑅 𝛽 (VFS/2B)Kvco
(10b)
2𝐶 𝐶
??
??
𝛼 1.49 & 𝛽 7.11 ∗ 10
20
Simulated Responses
𝑇 1 𝑉 𝐾
𝑇 1 𝑉 𝐾 1 𝜙 𝑓 1 𝑇 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓
𝐿𝐺 𝑓 𝐻 𝑒 𝑇 1 𝑉 𝐾 1
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁 𝜙 𝑓 𝑇 1 𝐻 𝑒
2𝜋 Δ 2 𝑗2𝜋𝑓 𝑁
22
Common Digital PLL Noise Sources
TDC DCO
TDC Loop DAC
n,in(t) CT-DT tq[k] Gain Filter DACq[k] Gain DT-CT n,DCO(t)
1 1
N T
Divider
1
𝑆 𝑓 𝑆 𝑓 𝑁𝑇𝐹 𝑓
𝑇
1
𝑆 𝑓 𝑆 𝑒 𝑁𝑇𝐹 𝑓
𝑇
1
𝑆 𝑓 𝑆 𝑒 𝑁𝑇𝐹 𝑓
𝑇
𝑆 𝑓 𝑆 𝑓 𝑁𝑇𝐹 𝑓
𝑆 𝑓 𝑆 𝑓 𝑆 𝑓 𝑆 𝑓 𝑆 𝑓
23
Noise Transfer Functions
𝜙 𝑁 · 𝑇 · 𝐿𝐺 𝑓
𝑁𝑇𝐹 𝑓
𝜙 1 𝐿𝐺 𝑓
𝜙 𝑁 · 2𝜋 · 𝐿𝐺 𝑓
𝑁𝑇𝐹 𝑓
𝑡 1 𝐿𝐺 𝑓
𝐾
𝜙 𝑇
𝑗2𝜋𝑓
𝑁𝑇𝐹 𝑓
𝑞 1 𝐿𝐺 𝑓
𝜙 1
𝑁𝑇𝐹 𝑓
𝜙 1 𝐿𝐺 𝑓
t
in(t)
e[k]
26
TDC Quantization Noise
1 1 𝑁 · 2𝜋 · 𝐿𝐺 𝑓
𝑆 𝑓 𝑆 𝑒 𝑁𝑇𝐹 𝑓 𝑆 𝑒
𝑇 𝑇 1 𝐿𝐺 𝑓
VCO out
R
1
𝑆 𝑒 10.8𝑑 𝐵⁄𝐻 𝑧
R/2 12
DCO[k] Decoder
B
DCO
DAC
DACq[k] Gain DT-CT
Loop
VFS KVCO
Filter T out(t)
2B j2f
Output
TDC
68%
Jitter
Variance DCO
7%
Ref Clk
DAC 1%
25%
TDC
67%
After CDR
DAC TDC
14%
6%
Jitter
Variance Ref Clk
3%
TDC DAC
4%
8%
DCO
85%
After CDR
33
With Delta-Sigma Modulation
PLL Output
DCO Ref Clk
52.4% 47.2%
Jitter
Variance
Ref Clk
12%
TDC
8% DAC
6%
DCO
74%
After CDR
TDC
1%
DAC 0.5%
Jitter
Variance Ref Clk
3%
TDC DAC
14% 6%
DCO
77%
After CDR
36
Flash TDC
e[k]
CLKFB(t) t t t t
1
t
te
t
CLKIN(t)
e[k]
t
CLKIN(t) t2 t2 t2
e[k]
41
Oscillator-Based TDC
[Hsu JSSC 2008]
45