A Simple LDO with Adaptable Bias

For Internet of Things Applications

I.M. Filanovsky, L.B. Oliveira, N.T. Tchamov, and V.V. Ivanov

VDD VDD
Abstract—A new transistor model is used for design of two RS
M3 M4
LDO regulators using a differential stage loaded by a current
amplifier and the voltage feedback. The first LDO has a constant I3 I4 M3 M4
bias current, the second LDO has an additional adaptable bias I3
I1 I4
circuit controlled by the load current. The LDOs are analyzed and
compared. When the load is absent, the transistors in both circuits VRef I2 V Out
are operating in weak inversion; when the load is increasing the M1 M2
b)
pass transistors in both circuits are moving to strong inversion. It CL
is shown that in these LDOs the output voltage may be higher IB IL
than the input reference voltage at very small load currents, and
the circuits start “to follow” the input voltage only being loaded . a)
with a load current depending on the bias and LDO loop gain. The
circuits were designed for 130 nm CMOS technology and their Fig. 1 Simple LDO regulator (a); increasing loop gain (b)
operation was verified using CADENCE simulation tool.
­ A W I1 = I 2 + I L
Index Terms—LDO, Weak inversion, Moderate inversion, ® (2)
Strong Inversion, Adaptable bias, Translinear loop. ¯ I1 + I 2 = I B
From (2) one obtains that
I. INTRODUCTION I1 = ( I B + I L ) /( A W + 1) , (3)

A daptive and reconfigurable designs for components close

to both source and load can be a viable and energy
efficient solutions for designing power delivery networks for
and
I 2 = ( AW I B − I L ) /( A W + 1) . (4)

internet of things (IoT) [1]. Yet, the desire to increase their
efficiency may result, as shown below, in some unpredictable
characteristics.
An LDO regulator for the load currents in milliampere
range could be designed using a differential pair loaded with a
simple current amplifier providing the voltage feedback (Fig. 1
a)). The circuit operation assumes that the bias current, I B , is
split in two parts, I 1 and I 2 ; I 1 is equal to the input current
I 3 of the current amplifier M3, M4. The amplifier develops the
current
I 4 = (W 4 / W3 ) I 3 = A W I 3 (1)
which supplies both the load current I L and the current I 2 . If
I L increases, then I 2 decreases. Then I 1 increases, and, being
amplified, replenishes the required increasing the load current.
The circuit static operation is described by two equations
This work was supported by the NSERC, Canada (Grant EE638), by the
Portuguese Foundation for Science and Technology (FCT/MCTES) under
projects DISRUPTIVE (EXCL/EEI-ELC/0261/2012) and PEST (PEST-OE
EEI/UI0066/2014), and by Academy of Finland under Project Decision
No.295865, NOLIDIS.
I.M. Filanovsky is with the University of Alberta, Edmonton, Canada
(igor@ece.ualberta.ca); L.B. Oliveira is Universidade Nova de Lisboa,
Caparica, Portugal; N.T. Tchamov is with the Technical University of Tampere,
Finland; V.V. Ivanov is with Texas Instruments.
The output current, I L , becomes maximal when I 2 = 0 . From
(4) one can find that this maximal value, I L max , is equal to
I L max = AW I B (5)
To increase LDO efficiency, the bias current should be
chosen as small as possible, and the current gain AW as large
as possible. To increase the gain one uses W 4 >> W3 or even
adds a resistor R S (Fig. 1 b)) in the source circuit of M3 (of
course, in this case AW becomes a nonlinear function of I 1 ).
Assuming that for all values of I 1 and I 2 one has
approximately equal gate-source voltages of M1 and M2, the
output voltage VOut should be approximately equal to the input
voltage V Re f .
Unfortunately, this last assumption is not valid when the
bias current I B is very small. Then, with small I L (especially
when I L = 0 ), and for high AW , the current distribution
I 2 >> I1 occurs with M1 operating in weak inversion. It will
result in a large difference between the gate-source voltages of
M1 and M2, with VOut > V Re f . Only when I L is sufficiently
high (but then M4 is not operating in weak inversion and is
moving via moderate to strong inversion with load increasing)
then I 1 and I 2 become approximately equal. This means that

978-1-4673-6853-7/17/$31.00 ©2017 IEEE

in this case the circuit is starting to function as LDO for load VGS −VTH § VGS −VTH ·
currents defined by I B and AW (or, with R S , by the LDO loop n φt ¨ 2 nφt ¸
I DW = I Z e ¨1 − α 1 e ¸ (10)
gain), i.e. around I L ≈ 0.5 I L max = 0.5 AW I B . ¨ ¸
© ¹
One can see that the correct calculation of the circuit load where α 1 = 1− (ln 2) 2 . In the region of moderate inversion
characteristic requires the transistor model (at least, for M4)
( VGS > VTH ) (9) can be approximated as
which clearly describes the transition from weak via moderate
2
to strong inversion. § V −V
− GS TH − GS TH ·
V −V
¨ VGS − VTH 2 nφt ¸
This paper describes such a model, and shows how to I DM = I Z ¨ +e − α 2 e nφt ¸ (11)
calculate the LDO load characteristics using it. It is also shown ¨ 2nφ t ¸
© ¹
how to do calculations in case of using an adaptive bias circuit.
where α 2 = 1 − ln 2 . In fact the eq. (11) covers both the regions
The paper is organized the following way. Part II describes
the approximations for the transfer characteristics of transistors of moderate and strong inversions.
operating in weak and moderate inversion. Part III consider It is easy to verify that at VGS = VTH both (10) and (11)
load characteristics of the LDO shown in Fig. 1 when I B is result in the same value of I DW = I DM = (ln 2) 2 I Z . One can
small. Part IV describes the LDO with adaptable bias. Part V also verify that the derivatives of (10) and (11) at this point are
summarizes the results of calculations and simulations. very close, the difference is less than 0.015.
For graphical representation and calculations it is rational to
II. “RECONCILIATION” TRANSISTOR MODEL APPROXIMATION introduce the normalized variable U = (VGS − VTH ) /(nφ t ) and
In the transistor “reconciliation” model [2] valid in all normalized currents J W = I DW / I Z and J M = I DM / I Z . Then
operating regions the drain current I D of an n-channel one can use
transistor (without body effect) is described by the following J W = e U (1 − α 1 e U / 2 ) (12)
equation
for U < 0 and
ª § VGS −VTH · § VGS −VTH − nVDS · º
« 2¨ 2 nφ t ¸ 2¨ 2 nφt ¸» J M = [(U / 2) + e −U / 2 − α 2 e −U ] 2 (13)
I D = I Z ln ¨1 + e ¸ − ln ¨1 + e ¸» . (6)
« ¨ ¸ ¨ ¸ for U > 0 . These normalized values are represented in Fig. 2
¬« © ¹ © ¹¼»
where the left part of the graph (black) correspond to operation
Here in weak inversion (eq. (12)), and the right part (red)
I Z = 2 μC ox (W / L)nφt 2 (7) corresponds to operation in moderate inversion (eq. (13)).
where φt = (kt ) / q is the thermal voltage, VTH is the threshold 4
Normalized Transconductance Characteristic

voltage. All other symbols have their usual meanings. The 2

substrate factor n may be approximated [2] as
0

n ≈ 1 + [γ /(2 V SB + 2φ F )] (8)
-2

where φ F is the Fermi voltage. The model (6) usually -4

provides, with some ordinary precautions (long and wide

-6
transistor), a good correspondence between theoretical and J
W

experimental results [3] in typical CMOS technologies. -8 J

M

In the model (6), all voltages are taken with respect to the -10

source. The term involving only the gate-source voltage VGS is
separate from the term including the drain-source voltage V DS .
This allows one consider the degree of inversion separately
from the degree of saturation. If the voltage V DS is sufficiently
high the transistor operates in strong saturation. Then the
second term can be omitted, and the drain current may be
described as
§ VGS −VTH ·
¨ ¸
I D = I Z ln 2 ¨1 + e 2 nφt ¸ (9)
¨ ¸
© ¹
It was shown in [4] that this dependence may be approximated,
depending on the level of inversion, by two expressions. In
weak inversion ( VGS < VTH ) one can use the approximation
-12
-10 -8 -6 -4 -2 0 2 4 6 8 10
Normalized Effective Voltage, U
Fig. 2 Normalized transconductance characteristic
At the point U = 0 both (12) and (13) have the value of
(ln 2) 2 = 0.481 , and this number can be used as an indicator of
transistor inversion: if I D / I Z < 0.481 the transistor operates
in weak inversion, if I D / I Z > 0.481 the transistor operates in
moderate inversion (Fig. 2 shows ln[(ln 2) 2 ] = −0.733 ).
In the calculations of CMOS circuits operating in weak
inversion one has to find negative solutions for the variable
U from eq. (12) when J W is given, or positive solutions for
U from eq. (13) when J M is given. The convenient way to
find them is interactive calculations using MATLAB command
for solution of nonlinear equations. If this program is not at Further calculations will follow the same pattern. It is
hand one can do the calculations using the Table I with linear convenient to use ΔI 1 = 0.091 μA as a step for increasing I1
interpolation for the values between rows. and calculate the load current as
I L = AW I1 − I 2 (14)
Table I Solutions for nonlinear equations (12) and (13)
It is not important here whether M3 and M4 are in weak or
JW U JM U
moderate inversion; the gain is equal to AW .
0.48 - 0.0023 0.50 0.0502 Case II. RS = 100 kȍ
0.42 - 0.2572 0.70 0.4798 Using (7) and corresponding values of parameters for
0.37 - 0.4630 1.00 1.0206 p-channel transistors one finds I Z 3 = 0.181 μA. If the
0.25 - 1.0101 1.50 1.7099
previous values of I1 are used as the input currents for M3, one
0.14 - 1.7175 2.00 2.2416
0.09 - 2.2202 3.00 3.0598 finds that even the first value ( I1 =0.091 μA) results in the
0.05 - 2.8632 4.00 3.7008 moderate inversion of M3 (0.091/0.181= 0.502 >0.4805),
0.03 - 3.4072 5.00 4.2410 hence, for all other values of I1 M3 will be in moderate
0.02 - 3.8325 7.00 5.1422 inversion as well. Then, the effective voltages U 3 will be
0.01 - 4.5503 10.0 6.2373 found using eq. (13) (of course, it is more convenient, for
p-channel transistors to use source-gate voltage). Adding to the
If J W < 0.01 or J M > 10 the calculation for the required values of U 3 the normalized values of the voltage drop
values of U may be obtained using the approximation U R = ( I1 RS ) /(n pφt ) one finds the normalized values of U 4 .
U 2 2
J W ≈ e (very weak inversion) or J M ≈ [(U / 2)] = U / 4 All these values are positive, which means that M4 operates in
(strong inversion). moderate inversion. The normalized values of J 4 are obtained
using (13); the de-normalization using I Z 4 = 1.811 μA will
III. SIMPLE LDO REGULATOR
give the values of I 4 . Then, using I L = I 4 − I 2 one finds the
In this part we consider calculations and simulations for the
load current.
LDO shown in Fig. 1. The calculations are done for UMC
The load characteristics for both cases are shown in Fig. 3.
0.13 μm 1P8M logic CMOS digital technology. The basic
LDO Regulator Load Characteristics
parameters are the following: VTN =0.38 V, VTP =0.33 V,
1 Rs =0; Calc.
μ n C ox =490 μA/V-2, μ p C ox =100 μA/V-2. The substrate 0.88
2 Rs =100k; Calc.

factors nn ≈ 1.30 and n p ≈ 1.35 were considered constant. The

0.86 3 Rs =0; Sim.
4 Rs =100k; Sim,
0.84
Output voltage, VOut,volts

bias I B = 1 μA, the reference voltage VRe f = 0.8 V, the 0.82

required output voltage range is 0.78 V < VOut < 0.82 V . The 0.8

calculations and simulations were done for V DD = 1.2 V. All 0.78

devices have the length of L =0.4 μm, the widths of M1 and M2 0.76
1 3 2 4
are W1 = W 2 = 1 μm. 0.74

Case I. R S = 0 . 0.72

The amplifier transistors have W3 = 0.4 μm and 0.7

W4 = 4 μm. Hence, AW = 10 . Using (2) one finds that
for I L = 0 the currents I 1 = 0.091 μA, and I 2 = 0.909 μA.
Now, using (7) one calculates I Z 1 = I Z 2 = 2.136 μA, and find
the normalized values J 1 = 0.042 and J 2 = 0.425 . Both
values are less than 0.4805, which means that M1 and M2 are
operating in weak inversion. Solving eq. (12) for these values
of J1 and J 2 (i.e. using Table I) one finds the normalized
effective voltages of U 1 = −3.038 an U 2 = −0.235 . The
difference (U 2 − U 1 )n n φ t = 0.094 V gives the
difference between gate voltages of M2 and M1. Hence, the
output voltage for I L = 0 is VOut = 0.894 V (i.e. larger
than VRe f ).
0 5 10 15 20 25
Load Current, IL, microamperes
Fig. 3 Load characteristics of simple LDO regulator
IV. LDO REGULATOR WITH ADAPTIVE BIAS
A reduction of the bias current can be achieved (Fig. 4)
adding to the regular bias source I B , a special circuit
(transistors M5, M6, M7, and the source I 0 ) which modifies the
current of M1 when the load changes. The circuit operates the
following way. The current I 0 create a constant voltage
voltage between the gates of M5 and M6; the same constant voltage will
be between the gates of M2 and M7. When I L is very small ( AW
is high) the current I B is taken by M2 and an additional current
is developed in M2 and M7 to provide this equality (so VOut is
larger than VRe f ). When I L is increasing, and the current I 2 described in Part III, Case II.
The load characteristics for both cases are shown in Fig. 5.
is diminishing ( I L takes it out of M2), the gate-source voltage
LDO Regulator Load Characteristics
of M2 is diminishing (so that VOut becomes close to VRe f ). 1 Rs =0; Calc.
0.88
Then the source-gate voltage of M7 is increasing, and the 2 Rs =100k; Calc.
0.86 3 Rs =0; Sim.
current of this transistor not only compensate the loss of current 4 Rs =100k; Sim,
in M2 but creates an additional current flowing into M1. As a 0.84

Output voltage, VOut,volts

result one achieves the same (or a wider) range of I L for the 0.82

same prescribed difference between VOut and VRe f using a 0.8

0.78
smaller total bias current I B + I 0 , and I L is not limited by this 4
0.76
bias as in (5). 0.74
1 3 2

RS VDD 0.72

0.7
0 5 10 15 20 25
M3 M4 Load Current, IL, microamperes

I3 I4 Fig. 5 Load characteristics of LDO regulator with adaptable bias

V Out
I1
VRef I2
M1 M2 M5
CL
IS M6
M7 IL
I7
IB I0
Fig. 4 LDO with gain loop and bias current controlled by the load
We will do the calculation of load characteristics for two
cases as well. The adaptive bias circuit is the same for both
cases, with W5 = 1 μm and W6 = W7 = 5 μm. The current
sources are I B = I 0 = 0.15 μA. The width W3 = 0.4 μm, but
the output device is enlarged to W4 = 16 μm.
Case I. RS = 0 .
Calculating the normalized currents J 5 = 0.069 and
J 6 = 0.063 one finds that both M5 and M6 are operating in
weak inversion; using Table I one finds the normalized
effective voltages U E 5 = −0.075 and U E 6 = −0.091 (again,
these are the source-gate voltages). The sum
U B = U E 5 + U E 6 = −0.166 is the normalized constant voltage
between the gates of M2 and M7. Further calculations are
similar to that which were used in the previous circuit. One
chooses a value of I 2 (it is easy to see that these values should
be around of I 2 = I 0 ). For each value of I 2 one finds U E 2 ,
and U E 7 = U B − U E 2 will define the corresponding value of I 7 .
This will define I S = I 7 − I 2 , the additional current supplied to
M1 by the adaptive bias circuit. After that one can
find I 4 = 40 I1 and I L = I 4 − I 2 − I 0 . Finally, using I1 and
I 2 one finds VOut .
Case II. RS = 100 kȍ.
The calculations of I1 follows the order described in the
previous case. The calculations of I 4 follows the order
V. DISCUSSION
A simple transistor model for IoT circuits where transistors
are operating in wide range (from weak via moderate to strong)
of inversion is proposed. The results of calculations and
simulations, for such simple model, are in a good agreement,
and confirm the usefulness of the proposed transistor model.
The secondary effects (velocity saturation, etc.) can be also
included in a usual way [5, eq. (7)].
An LDO with an additional adaptive bias circuit controlled
by the current load is proposed. The adaptive bias allows to
reduce the total LDO bias current: the calculations show that
when the output voltage becomes just below 0.78 V, I 7 is
about 0.2 μA (in simulations it is 0.19 μA), i.e. the total bias
current is below 0.5 μA, and the LDO efficiency is increased
twice.
Adaptable bias is improving the LDO load characteristics:
the range of load currents for a given variation of output
voltage is increased. Yet, it does not solve the problem for very
low load currents. Here, the circuit restructuring, which is a
matter of future work, may help.
The LDO regulator of Fig. 4 found application as memory
retention regulator [6].
REFERENCES
[1] S. Gangopadhyay, S.B. Nasir, and A. Raychoudhury, “Integrated Power
Management in IoT Devices under Wide Dynamic Ranges of Operation”,
Proc. 52nd Design Automation Conf. (DAC’15), pp.1-6, 2015.
[2] Y. Tsividis, K. Suyama, and K. Vavelidis, “Simple ‘reconciliation’
MOSFET model valid in all regions”, EL vol. 3, no. 6, pp. 506-508, 1995.
[3] D.M. Binkley, Tradeoffs and Optimization in Analog CMOS Design, J.
Wiley, West Sussex, England, 2008.
[4] I.M. Filanovsky, J.K. Jarvenhaara, and N.T. Tchamov, “On Moderate
Inversion/Saturation Regions as Approximations to “Reconciliation”
Model, Proc. IEEE Canadian Conf. Elec. Comp. Eng. (CCECE’2016), in
print.
[5] B. Toole, C. Plett, and M. Cloutier, “RF Circuit Implications of Moderate
Inversion Enhanced Linear Region in MOSFETS,” IEEE Trans. Circ.
Syst., Pt. I, vol. 51, no. 2, pp. 319-327, 2004.
[6] V. Ivanov, “Design methodology and circuit techniques for any load
stable LDO with instant load regulation and low noise”, in Advanced
Analog Circuit Design, New York: Springer, 2008.