01 MOS Lecture

MOS Transistors
MOS Transistors
Dinesh Sharma
EE Department
IIT Bombay, Mumbai
August 4, 2023
MOS Transistors
The Parallel Plate Capacitor
Parallel Plate Capacitor
The parallel plate capacitor

consists of two parallel metallic
+ + + + + + + + Q
plates of area A, separated by an ti
insulator of thickness ti and − − − − − − − − −Q
dielectric constant ǫ.
If we place a charge Q on the upper plate, it attracts charges of

opposite sign in the bottom plate, while repelling charges of the
same sign.
If the bottom plate is connected to ground, the repelled charge
flows to ground.
MOS Transistors
The two capacitor plates hold equal and + + + + + + + + Q

opposite charge. ti
This charge resides just next to the − − − − − − − − −Q
insulator on either side of it.
This is so, whatever be the quantity or sign of charge placed on
the upper plate.
The inducing and induced charge are always separated by the
thickness of the insulator, ti .
Therefore this structure has a constant capacitance given by:
Ctotal = ǫA/ti
MOS Transistors
+ + + + + + + + Q
ti
− − − − − − − − −Q
Since there are no charges inside the dielectric,
∇·D =0
So the electric field in the insulator is constant. The electrostatic

potential changes linearly from one plate to the other.
MOS Transistors
The MOS capacitor
The MOS Capacitor
What happens if we replace the lower metal

plate of the parallel plate capacitor by a Metal
Insulator (Oxide)
semiconductor? Depletion region
Semiconductor
This structure is known as the Metal Oxide
Metal
Semiconductor (MOS) capacitor.
Unlike a metal, a semiconductor can have charges distributed
in its bulk.
It is interesting to see what happens to the capacitance of this
structure, depending on the polarity and quantity of charge
placed on the upper plate.
MOS Transistors
The MOS capacitor
The MOS Capacitor
As an example, let the semiconductor be P type silicon,

doped to 1016 atoms /cm3 with Boron.
Holes will outnumber electrons by an extremely large factor
in this semiconductor. (1016 holes as opposed to
2.25 × 104 electrons per cm3 ).
If we place a negative charge on the upper plate, holes will
be attracted by this charge and will accumulate near the
silicon-insulator interface.
This situation is analogous to the parallel plate capacitor,
so the capacitance is the same as that of the
corresponding parallel plate capacitor.
MOS Transistors
The MOS capacitor
The MOS Capacitor
Let us see what happens if we place a positive charge on the

upper plate.
The positive charge on the upper plate needs to be
balanced by a negative charge in the semiconductor.
What can provide this negative charge?
Negative charge is carried by electrons (which are mobile)
and by ionised acceptors (which are fixed in their position).
As we have seen, there are very few electrons in this P
type silicon.
So the negative charge will have to be provided by
acceptor ions.
MOS Transistors
The MOS capacitor
The MOS Capacitor
The positive charge on the upper plate

repels holes away from the surface, which Metal
Insulator (Oxide)
move to the bulk. Depletion region
Semiconductor
This leaves negatively charged acceptors
Metal
in a depletion layer which forms at the
surface.
The -ve charges are fixed in position and have a charge
density of −1016 q/cm3 .
Thus the induced charge is now distributed and not
concentrated at the surface.
The average distance between inducing and induced
charge is now more as compared to the parallel plate
capacitor.
MOS Transistors
The MOS capacitor
The MOS Capacitor

For positive charge placed on the top metal plate, the induced
negative charge in the semiconductor is distributed.
The average distance between inducing
and induced charge is now more as Metal
Insulator (Oxide)
compared to the parallel plate capacitor. Depletion region
Semiconductor
So the capacitance of the structure is less
than that of the corresponding parallel Metal
plate capacitor.
As we add more and more +ve charge to the top plate, a
thicker and thicker depletion layer is required to balance
this charge.
So the capacitance keeps reducing as we make the top
plate more and more positive.
MOS Transistors
The MOS capacitor
The MOS Capacitor

As we make the top plate more and more positive, the
capacitance of the MOS structure reduces. How long will this
continue?
Recall that our reasoning was based on the fact that there
are very few electrons in the semiconductor and -ve charge
can only be provided by fixed acceptor ions.
However, as we keep reducing the hole concentration, the
electron concentration will keep going up, to keep the np
product constant.
As some point, the concentration of electrons will equal
and then exceed that of holes.
This is called inversion because the surface has electrons
as majority carriers in this P type silicon.
MOS Transistors
The MOS capacitor
The MOS Capacitor
What will happen to the capacitance when inversion occurs?

In inversion, there are many more electrons compared to
holes near the surface.
All incremental positive charge on the top plate will be met
by negative charge of electrons at the silicon-oxide
interface.
So the capacitance will recover to parallel plate
capacitance once again.
MOS Transistors
The MOS capacitor
Low frequency Capacitance of The MOS Capacitor:

Accumulation
Accumulation Inversion
Negative Bias: Depletion
Capacitance
For a negative DC bias on the top
plate, induced charge is provided
by holes which are mobile.
V
For all incremental negative charge on the top plate, the

incremental positive charge is provided as increased
concentration of holes, right at the surface of silicon.
The differential capacitance is the same as that of the
corresponding parallel plate capacitor.
MOS Transistors
The MOS capacitor

Depletion
Small Positive Bias: Accumulation Inversion
For a small positive DC bias on the Depletion
Capacitance
top plate, induced charge is
provided by acceptor ions in the
depletion layer, which are fixed in
their location. V
For all incremental positive charge on the top plate, the

incremental negative charge is provided at the edge of the
depletion layer through widening of the depletion layer.
The differential capacitance reduces as the top plate is made
more and more positive.
MOS Transistors
The MOS capacitor

Inversion
Accumulation Inversion
Positive Bias Beyond Inversion:
Depletion
Once inversion sets in, practically
Capacitance
all of the additional induced
negative charge is provided by
electrons which are mobile.
V
For all incremental positive charge on the top plate, the

incremental negative charge is provided through increased
electron concentration at the silicon/oxide interface.
The differential capacitance recovers to parallel plate
capacitance.
MOS Transistors
The MOS capacitor
Frequency dependence of MOS Capacitance

The capacitance in accumulation and depletion is due to
movement of holes.
In accumulation, holes move towards the surface, resulting
in parallel plate capacitor like behaviour.
In depletion, holes move away from the surface, exposing
the ionised acceptors which provide the depletion charge.
Since holes are already there in large numbers, changes in
induced charge can respond to changes in top plate
charge even at high frequency.
However, the recovery of capacitance to its parallel plate
value during inversion is caused by electron charge.
Thermal generation of electrons and their transport to the
surface is a slow process. So the capacitance recovery in
inversion is seen only at low frequency.
MOS Transistors
The MOS capacitor
MOS inversion capacitance at High frequency
We apply bias at DC (so that equilibrium conditions may be

assumed), and then superimpose a small AC signal to measure
capacitance.
Electrons can respond to DC bias, not to
High Frequency Signal.
Metal
Oxide
As we increase the DC bias beyond the
NOT TO SCALE
Inversion layer
Depletion Region
(Depletion width is constant after
inversion point, practically all the
Onset of inversion)
additional charge required in silicon is
(Only holes can respond to HF)
p type Si provided in the form of electrons. No more
Back Contact depletion charge is required.
Depletion width becomes nearly constant
beyond the inversion voltage.
MOS Transistors
The MOS capacitor
If the superimposed AC signal is changing

very fast, the incremental charge caused
Metal
Oxide by this signal cannot be provided in the
NOT TO SCALE
Inversion layer
Depletion Region form of electrons.
Onset of inversion)
So the incremental charge in response to
p type Si a high frequency AC signal has to be
Back Contact provided by holes.
This leads to a fluctuation in the width of
the depletion layer.
MOS Transistors
The MOS capacitor
To summarise:
In response to positive DC bias, the depletion width
increases till the inversion point and becomes constant at
this value for higher DC bias values.
This is because practically all the additional silicon charge
needed (corresponding to the bias voltage being higher
than the inversion voltage) is in the form of electrons.
If the superimposed AC signal is changing very fast, the
incremental charge in response to this signal cannot be
provided in the form of electrons.
This is because electrons cannot be generated and
transported fast enough to respond to the signal.
MOS Transistors
The MOS capacitor

In inversion region, the incremental
charge in response to a high frequency
Metal
Oxide AC signal is provided as a fluctuation in
NOT TO SCALE
Inversion layer
Depletion Region the width of the depletion layer.
Onset of inversion)
This response thus occurs at the edge of
p type Si the depletion region.
Back Contact
The depletion width has become constant
at its maximum value for bias voltages
greater than the inversion voltage.
Thus the induced incremental charge is at a constant depth into
the silicon at the edge of the depletion layer.
So the high frequency capacitance remains constant at its
minimum value as we increase the positive bias beyond the
inversion voltage.
MOS Transistors
The MOS capacitor
MOS capacitance at Low and High frequency
Low Frequency High Frequency

Accumulation Inversion Accumulation Inversion
Capacitance
Depletion
Capacitance
Depletion
V V
At high frequency, capacitance remains constant at its
minimum value as the bias voltage is increased beyond the
inversion point.
MOS Transistors
The MOS capacitor
Quantitative Analysis
Consider a one dimensional representation of the MOS

structures as shown in the figure below.
M O S M
The origin is at the silicon-oxide

interface and the positive x
direction is into the bulk of silicon.
o
X
Using a one dimensional analysis, we want to relate the
semiconductor charge to the applied gate voltage.
MOS Transistors
The MOS capacitor
We consider the ideal case first. Assume that

there is no built in contact potential between the
semiconductor and the metal,
there is no interface charge.
Let the back surface of Si be at zero potential
and the voltage applied to the gate terminal be M O S M
Vg .
Let the electrostatic potential at any point x be
denoted by φ(x)
and let the potential at the silicon-oxide o
X
interface be φs .
MOS Transistors
The MOS capacitor
We construct a Gaussian box passing through

M O S M
the interface and extending to +∞.
The surface integral of the outward pointing D
vector around the box should be equal to the
Gaussean Box
charge contained inside.
Normal component of D is non zero only for the surface passing
φ −V
through the interface. Here, D = ǫox stox g
φs − Vg
So Area × ǫox = Total Charge in silicon
tox
MOS Transistors
The MOS capacitor
φs − Vg
= Total Charge in silicon
Area × ǫox
tox
If we define Qsi to be the semiconductor charge per unit area,
and Cox to be the parallel plate capacitance per unit area,
Qsi
Cox (φs − Vg ) = Qsi So Vg = φs −
Cox
Thus, the surface potential and the applied gate voltage can be
related to each other.
MOS Transistors
The MOS capacitor
Quantitative Analysis: Solution of Poisson’s Equation
We can write the Poisson’s equation in the semiconductor as
∇·D=ρ
∂2φ
or = q(Nd+ − Na− + p − n)
− ǫsi
∂x 2
Since the electrostatic potential is dependent only on x, we can
change partial derivatives to total derivatives.
d2 φ

d dφ d
− 2 = − = (E)
dx dx dx dx
where E is the electrostatic field.

MOS Transistors
The MOS capacitor
Changing the variable from x to φ.
d2 φ

dE dφ d d 1 d 2
− 2 = = (E) = −E (E) = − E
dx dx dx dφ dφ 2 dφ
defining
q
u ≡ βφ where β ≡
KB T
We get
d2 φ 1 d 2 β d 2
− = − E = − E
dx 2 2 dφ 2 du
MOS Transistors
The MOS capacitor
The right hand side of the Poisson’s equation
∂2φ
−ǫsi = q(Nd+ − Na− + p − n)
∂x 2
represents the charge density. In the absence of an applied
voltage, this must be zero everywhere.
q(Nd+ − Na− + p0 − n0 ) = 0
where p0 and n0 represent the hole and electron density in the

absence of an applied field. therefore,
Nd+ − Na− = −(p0 − n0 )

MOS Transistors
The MOS capacitor
The Poisson’s equation in the semiconductor is
∂2φ
−ǫsi = q(Nd+ − Na− + p − n)
∂x 2
We have established that
d2 φ β d 2
− = − E and Nd+ − Na− = −(p0 − n0 )
dx 2 2 du
q qφ
where β≡ and u≡ = βφ
KB T KB T
βǫsi d 2
Therefore − E = q [p − p0 − (n − n0 )]
2 du
MOS Transistors
The MOS capacitor
βǫsi d 2
− E = q [p − p0 − (n − n0 )]
2 du
so
d 2 2qp0 p n0 n
E =− −1− −1
du βǫsi p0 p0 n0
n = n0 e u and p = p0 e−u
This gives,

d 2 2qp0 −u n0 u
E =− e − 1 − (e − 1)
du βǫsi p0
MOS Transistors
The MOS capacitor

d 2 2qp0 −u n0 u
E =− e − 1 − (e − 1)
du βǫsi p0
This can be integrated from x = ∞ (where E = 0 and u = 0) to x
to give
2qp0 u
Z
n0
E2 = −e−u + 1 + (eu − 1) du
βǫsi 0 p0
Integrating and putting limits at 0 and u, we get

2 2qp0 −u n0 u
E = e − 1 + u + (e − 1 − u)
βǫsi p0
MOS Transistors
The MOS capacitor
Quantitative Analysis: Evaluation of D

2qp0 −u
2 n0 u
E = e − 1 + u + (e − 1 − u)
βǫsi p0
Therefore
s 1
2qp0 −u n0 u 2
E =± e − 1 + u + (e − 1 − u)
βǫsi p0
So the displacement vector D can be evaluated as:

s 1
2qp0 ǫsi −u n0 u 2
D = ǫsi E = ± e − 1 + u + (e − 1 − u)
β p0
This equation permits us to calculate D, given the value of u. In

particular, the value of D at the surface (which is required for
integration over the Gaussean box), can be evaluated from us .
MOS Transistors
The MOS capacitor
Quantitative Analysis: Debye Length

As an aside, this equation leads to the definition of Debye
Length in a semiconductor.
s 1
2qp0 ǫsi −u n0 u 2
D = ǫsi E = ± e − 1 + u + (e − 1 − u)
β p0
If u is very small, the exponentials in u can be expanded to
second order. The first two terms cancel with 1 and u, leaving
s 1
2qp0ǫsi 2 n0 2 2
D = ǫsi E = ± u /2 + (u /2)
β p0
s
∂u qβp0 n0
≃∓ 1+ u
∂x ǫsi p0
∂u
Since ∂x ∝ u, this leads to exponential solutions for u.
MOS Transistors
The MOS capacitor
Quantitative Analysis: Debye Length
For an unperturbed semiconductor, u = 0 everywhere.

If we perturb the surface potential by a small value us , this
potential will decay exponentially in the bulk of the
semiconductor, with a characteristic length known as
Debye Length.
For the p doped semiconductor under consideration,
n0 n0
p0 << 1, so (1 + p0 ) ≃ 1. In this case, the characteristic
lengthq(known as the extrinsic Debye Length) is
ǫsi
LD = qβp 0
.
In the intrinsic case, n0 = p0 , so 1 + pn00 = 2.
Thus, in the intrinsic case, we get an additional factor
q of 2
ǫsi
in the denominator under the square root. LD = 2qβn i
.
MOS Transistors
The MOS capacitor
Quantitative Analysis: Semiconductor Charge

We construct a Gaussian box passing through
M O S M
the interface and extending to +∞.
The surface integral of the outward pointing D
vector around the box should be equal to the
Gaussean Box
charge contained inside.
The charge contained in the box is then the integral of the
outward pointing D vector over the surface of the box.
The normal component of D is non zero only at the surface
forming the interface. Also, the outward pointing D is along the
negative x axis. Therefore,
Total Semiconductor Charge = Area × (−D)

MOS Transistors
The MOS capacitor
Defining Qsi to be the charge in the semiconductor per unit

area,
√ 1
2ǫsi −us n 0 us 2
Qsi = ∓ e − 1 + us + (e − 1 − us )
βLD p0
q ǫsi
r
where β ≡ , us ≡ βφs , and LD ≡
KB T qβp0
Here LD is the Extrinsic Debye Length.
MOS Transistors
The MOS capacitor
Qsi consists of mobile as well as fixed charge.

The mobile charge is contributed by holes when us < 0
and by electrons when us > 0.
The mobile electron charge is substantial only when the
positive surface potential exceeds a threshold value.
The fixed charge is contributed by the depletion charge
when the surface potential is positive. It can be calculated
using the depletion formula.
MOS Transistors
The MOS capacitor
Quantitative Analysis: Depletion Charge
Depletion charge can be calculated by the depletion formula.

p
Qdepl = −qNa Xd = 2qNa ǫsi φs (φs > 0)
A more accurate expression for depletion charge accounts for

slightly lower charge density at the edge of the depletion region
by subtracting KB T/q from φs .
p
Qdepl = −qNa Xd = 2qNa ǫsi (φs − KB T /q) (φs > KB T /q)
MOS Transistors
The MOS capacitor

The figure below shows the calculated values for the total
semiconductor charge per unit area (i.e.. inclusive of depletion
and mobile charge) and just the depletion charge per unit area
for a P type semiconductor doped to 1016 /cm3 .
1e−05
Abs. Sem. Charge (C/cm2 )
Maj. Carrier
1e−06 Charge
Q
total
1e−07
Q
Depl.
1e−08
1e−09
−0.4 −0.2 0 0.2 0.4 0.6 0.8 1
Gate Voltage (V)
MOS Transistors
The MOS capacitor
For small positive surface 1e−05

potential, the total
Abs. Sem. Charge (C/cm2 )

Maj. Carrier
semiconductor charge 1e−06 Charge
contains only depletion Q
total
charge. However, beyond a 1e−07
surface potential near 2ΦF , Q
the total charge exceeds the 1e−08
Depl.
depletion charge very rapidly.
This additional charge is due 1e−09
to mobile minority carriers (in −0.4 −0.2 0 0.2 0.4 0.6 0.8 1
Gate Voltage (V)
this case, electrons).
MOS Transistors
The MOS capacitor
Quantitative Analysis: Practical Case
A practical MOS structure will differ from the ideal case

assumed above in a few respects.
There is a built-in potential difference between the metal
used and Si, due to the difference between their work
functions. This shifts the relationship between Vg and φs ..
Also, there is a fixed oxide charge which resides
essentially at the silicon-oxide interface.
The total charge in the Gaussian box includes this fixed charge
as well as the semiconductor charge.
MOS Transistors
The MOS capacitor
Quantitative Analysis: Practical Case
These two non-idealities can be accounted for by modifying the

relationship between Vg and φs to be
Qsi + Qox
Vg = Φms + φs −
Cox
Where Φms is the metal to semiconductor work function
difference.
Now given φs , we can compute the semiconductor charge, and
hence the gate voltage.
MOS Transistors
The MOS capacitor
Quantitative Analysis: Surface Potential

The figure below shows the surface potential as a function of
applied voltage for a MOS capacitor with oxide thickness of
22.5 nm, substrate doping of 1016 /cm3 , oxide charge of
4 × 1010 q and aluminium as the gate metal.
1.0
0.8
Surface Potential (V)
0.6
0.4
0.2
0.0
−0.2
−4.0 −2.0 0.0 2.0 4.0
GATE VOLTAGE (V)
MOS Transistors
The MOS capacitor
Quantitative Analysis: Charge vs Voltage

The figure below shows the absolute value of semiconductor
charge as a function of the applied gate voltage. (The charge is
actually negative for positive gate voltages).
1e−06
Q
Abs. Sem. Charge (C/cm )
total
2
Q
1e−07 inv
Q
depletion
1e−08
1e−09
−2 −1 0 1 2 3 4 5
Gate Voltage (V)
MOS Transistors
The MOS capacitor

1e−06
Q
As one can see, for small

total
2
positive gate voltages, the Q
1e−07 inv
entire semiconductor charge
is depletion charge. Q
depletion
As the voltage exceeds a 1e−08
threshold voltage, the total

charge becomes much larger
1e−09
than the depletion charge. −2 −1 0 1 2 3 4 5
Gate Voltage (V)
The excess charge is provided by mobile electron charges. This

is the inversion region of operation, where electrons become
the majority carriers near the surface in a p type semiconductor.
MOS Transistors
The MOS capacitor
1e−06
Qtotal

2
Notice that the depletion Q
1e−07 inv
charge is practically constant
in the inversion region. Q depletion
This region begins when the 1e−08
surface potential exceeds

≈ 2ΦF . 1e−09
−2 −1 0 1 2 3 4 5
Gate Voltage (V)
The fact that depletion charge becomes constant beyond some

voltage is used for making approximations while solving for
drain current in a MOS transistor.
MOS Transistors
The MOS Transistor
The MOS Transistor
Inversion converts a p type

Metal Gate
semiconductor to n type at the
surface. n+ n+
We can use this fact to construct a P type Si
transistor.
We place semiconductor regions strongly doped to n type on
either side of a MOS capacitor made using p type silicon, to
sense if inversion has been caused by the voltage on the Gate.
MOS Transistors
The MOS Transistor
The MOS Transistor
Metal Gate
n+ n+
P type Si
if we try to pass a current between the two n+ regions (S

and D) when inversion has not occurred, we shall
encounter series connected np and pn diodes on the
current path.
Whatever be the polarity of the voltage applied between S
and D to pass current, one of these diodes will be reverse
biased and practically no current will flow.
MOS Transistors
The MOS Transistor
The MOS Transistor
Metal Gate
n+ n+
P type Si
After inversion, the intervening p region is converted to n

type.
Now there are no junctions as the whole surface region is
n type.
Current can be easily passed between the two n regions.
This structure is an n channel MOS transistor.
MOS Transistors
The MOS Transistor
MOS Transistor terminals
PMOS transistors can be similarly made using P regions

on either side of a MOS capacitor made on n type silicon.
When current flows in an n channel transistor, electrons
are supplied by the more negative of the two n+ contacts.
This is called the source electrode.
The more positive n+ contact collects the electrons and is
called the drain.
The current in the transistor is controlled by the metal
electrode on top of the oxide. This is called the gate
electrode.
MOS Transistors
I-V characteristics of a MOS transistor
A quantitative derivation of the current-voltage

characteristics of the MOS device is complicated by the
fact that it is inherently a two dimensional device.
The vertical field due to the gate voltage sets up a mobile
charge density in the channel region.
The horizontal field due to source-drain voltage causes
these charges to move, and this constitutes the drain
current.
Therefore, a two dimensional analysis is required to
calculate the transistor current, which can be quite
complex.
However, reasonably simple models can be derived by
making several simplifying assumptions.
MOS Transistors
A simple MOS model

We make the following simplifying assumptions:
The vertical field is much larger than the horizontal field.
Then, the resultant field is nearly vertical, and the results
derived for the 1 dimensional analysis for the MOS
capacitor can be used to calculate the point-wise charge
density.
This is known as the gradual channel approximation.
Accurate numerical simulations have shown that this
approximation is valid in most cases.
The source is shorted to the bulk.
The gate and drain voltages are such that a continuous
inversion region exists all the way from the source to the
drain.
Estimation of the current when this is not the case will be
taken up later.
MOS Transistors
A simple MOS model
We make the following additional assumptions:

The depletion charge is constant along the channel. This is
because the depletion charge becomes constant once
inversion sets in as was seen earlier.
The total current is dominated by drift current.
The mobility of carriers is constant along the channel.
MOS Transistors
A simple MOS model

The figure below shows the co-ordinate system used for
evaluating the drain current.
L
W
Y
S D
X dy
The x axis points into the semiconductor, the y axis is from

source to the drain and the z axis is along the width of the
transistor.
The origin is at the source end of the channel.
MOS Transistors
A simple MOS model

L
W
Y
S D
X dy
We represent the channel voltage as V(y), which is 0 at the

source end and Vd at the drain end.
We assume the current to be made up of just the drift
current.
Since we are carrying out a quasi 2 dimensional analysis,
all variables are assumed to be constant along the z axis.
MOS Transistors
A simple MOS model
W
Y
S D
X dy
Let n(x,y) be the concentration of mobile carriers (electrons for

an n channel device) at the position x,y (for any z). The drift
current density at a point is
J = no. of carriers × charge per carrier × velocity

MOS Transistors
A simple MOS model
J = no. of carriers × charge per carrier × velocity

∂V (y)
= n(x, y) × (−q) × µ × −
∂y
∂V (y)
J = µn(x, y)q
∂y
Integrating the current density over a semi-infinite plane at the

channel position y will then give the drain current.
MOS Transistors
A simple MOS model
L Drain current is given by

∞ W
∂V (y)
Z Z
W
µn(x, y)q dzdx
Y x=0 z=0 ∂y
S D
Z
Since there is no dependence on
z, the z integral just gives a
X dy multiplication by W.
Therefore,
∞
∂V (y)
Z
Id = µWq n(x, y) dx
x=0 ∂y
MOS Transistors
A simple MOS model
L
the value of n(x,y) is non zero in a
very narrow channel near the
W
Y
surface. We can assume that ∂V∂y(y )
S D is constant over this depth.
Z ∂V (y) ∞
Z
Id = µWq n(x, y)dx
X dy
∂y x=0
R∞
q x=0 n(x, y)dx = −Qn (y) where Qn (y) is the electron charge
per unit area in the semiconductor at point y in the channel.
(Qn (y) is negative, of course).
MOS Transistors
A simple MOS model
∂V (y) ∞
Z
Id = µWq n(x, y)dx
∂y x=0
∂V (y)
= −µW Qn (y)
∂y
Integrating the drain current along the channel gives
Z L Z L
∂V (y)
Id dy = −µW Qn (y) dy
0 0 ∂y
Z Vd
Id × L = −µW Qn (y)dV (y)
0
Vd
W
Z
So, Id = −µ Qn (y)dV (y)
L 0
MOS Transistors
A simple MOS model

The surface potential due to the vertical field saturates around
2ΦF if we are in the inversion region.
Therefore, the total surface potential at point y is V(y) + 2 ΦF .
Now, by Gauss law and continuity of normal component of D at
the interface,

Cox Vg − ΦMS − φs = − (Qsi + Qox )

Therefore, − Qsi = Cox Vg − ΦMS − V (y) − 2ΦF + Qox /Cox
However, Qsi = Qn + Qdepl . So,
−Qn (y) = −Qsi (y) + Qdepl

Qox + Qdepl
= Cox Vg − ΦMS − V (y) − 2ΦF +
Cox
MOS Transistors
A simple MOS model
This simple model assumes that the depletion charge is

constant along the channel. Let us define
(Qox + Qdepl )
VT ≡ ΦMS + 2ΦF −
Cox
then − Qn (y) = Cox (Vg − VT − V (y))
W Vd
Z
Therefore Id = µCox (Vg − VT − V (y))dV (y)
L 0
W 1
= µCox [(Vg − VT )Vd − Vd2 ]
L 2
MOS Transistors
A simple MOS model
Mobile charge density at source end = Cox (VG − VT )

Mobile charge density at drain end = Cox (VG − VD − VT )
Average charge density in the channel = Cox (VG − VT − VD /2)
Average carrier velocity = µVD /L
Current is scaled by the width of the transistor. So
W 1
ID = WCox (VG −VT −VD /2)µVD /L = µCox [(Vg −VT )Vd − Vd2 ]
L 2
MOS Transistors
A simple MOS model
A More Accurate Model

Our model gives a very simple expression for the drain current.
W 1
[(Vg − VT )Vd − Vd2 ]
Id = µCox
L 2
However, it requires a lot of simplifying assumptions, which limit
the accuracy of this model.
If we do not assume a constant depletion charge along the
channel, we can apply the depletion formula to get its
dependence on V(y).
p
Qdepl = − 2ǫsi qNa (V (y) + 2ΦF )
then, The absolute value of mobile electron charge -Qn is given
by
p
Cox Vg − ΦMS − V (y) − 2ΦF + Qox − 2ǫsi qNa (V (y) + 2ΦF)
MOS Transistors
A simple MOS model
A More Accurate Model
p
−Qn = Cox Vg − ΦMS − V (y) − 2ΦF +Qox − 2ǫsi qNa (V (y) + 2ΦF )
This leads to

W Qox 1
Id = µCox Vg − ΦMS − 2ΦF + Vd − Vd2
L Cox 2
p #
2 2ǫsi qNa
− (Vd + 2ΦF )3/2 − (2ΦF )3/2
3 Cox
This is a more complex expression, but gives better accuracy.

MOS Transistors
Modeling the saturation region
The treatment in the previous section is valid only if there is

an inversion layer all the way from the source to the drain.
For high drain voltage, the local vertical field near the drain
is not adequate to take the semiconductor into inversion.
Several models have been used to describe the transistor
behaviour in this regime.
The simplest of these defines a saturation voltage at which
the channel just pinches off at the drain end.
The current calculated for this voltage by the above models
is then supposed to remain constant at this value for all
higher drain voltages.
MOS Transistors
The pinch-off voltage is the drain voltage at which the

channel just vanishes near the drain end.
Therefore, at this point the gate voltage Vg is just less than
a threshold voltage above the drain voltage Vd .
Thus Vdsat = Vg − VT .
The current calculated at Vdsat is denoted as Idss .
W 1
Idss = µCox [(Vg − VT )2 − (Vg − VT )2 ]
L 2
1 W
Thus, Idss = µCox (Vg − VT )2
2 L
The drain current is assumed to remain constant at this value
for all drain voltages > Vg − VT .
MOS Transistors
Assuming a constant current in the saturation region leads

to an infinite output resistance.
This can lead to exaggerated estimates of gain from an
amplifier.
Therefore, we need a more realistic model for the transistor
current in the saturation region.
One of these is a generalization of the model proposed by
James Early for bipolar transistors.
This model is not strictly applicable to MOS transistors.
However, due to its numerical simplicity, it is often used in
compact models for circuit simulation.
MOS Transistors
Drain Current ->

Early model states that the drain current
increases linearly in the saturation region with
drain voltage.
Drain Voltage ->
VE
The slopes of the linear I-V characteristics in the saturation

region is such that if the saturation current characteristics
for different gate voltages are produced backwards, they
will all cut the drain voltage axis at the same (negative)
drain voltage point.
The absolute value of this voltage is called the Early
Voltage VE .
MOS Transistors
The current equations in saturation mode now become:
IDSS ≡ ID (VG , VDSS )

V + VE
ID = IDSS d For VDS > VDSS
VDSS + VE
The value of VDSS will be determined by considerations of

continuity of the drain current and its derivative at the
changeover point from linear to saturation regime.
For large values of VE , the value of Vdss is quite close to

VGS − VT .
MOS Transistors

If we use the simple model discussed earlier,
∂Id W
= µCox Vg − VT − Vd For Vd ≤ Vdss
∂Vd L
∂Id Idss
And = For Vd ≥ Vdss
∂Vd Vdss + VE

W 1 2
Where Idss ≡ µCox Vg − VT Vdss − Vdss
L 2
∂Id
On matching the value of ∂Vd on both sides of Vdss , we get
s 
2 Vg − VT
Vdss = VE  1+ − 1
VE
MOS Transistors
s 
2 Vg − VT
Vdss = VE  1+ − 1
VE
In practice, VE is much larger than Vg − VT .

If we expand the above expression, we find that to first
order the value of Vdss remains the same as the one used
in the simple model - that is, Vg − VT .
Expansion to second order gives

Vg − VT
Vdss ≃ Vg − VT 1−
2VE
MOS Transistors
Since the value of Vdss does not change substantially from the
ideal saturation case, a simpler approach can be tried.
The drain current is calculated using the ideal saturation
model and its value is multiplied by a correction factor =
(1 + λVd ) in saturation as well as in linear regime.
This automatically assures continuity of Id and its
derivative.
λ is a fit parameter, whose value is ≈ 1/VE .
This approach is used in SPICE, a popular circuit simulation
program.
MOS Transistors
MOS Device Scaling
Scaling transistor geometry

Since the transistor current depends on W /L, it is
interesting to see what happens if we reduce both W and
L, keeping their ratio constant.
We have to adjust other parameters in order to ensure that
the transistor works without problems.
Due to technological constraints, we cannot reduce lateral
geometries without reducing layer thicknesses. To define
finer lateral dimensions through etching etc., we need the
layers to be thinner.
Thus all dimensions, vertical or lateral, need to be scaled
by the same factor.
To ensure that higher fields in the device do not cause
breakdown, we have to scale down all the voltages by the
same factor as L. (This is known as constant field scaling).
MOS Transistors
MOS Device Scaling
Scaling in general
Scaling is not a new concept. Examples of scaling abound in

nature.
It is well known that water stored in a smaller earthen pitcher is
much cooler than when it is stored in a large pitcher. – Why?
Cooling is caused by evaporation.
Cooling ∝ surface area ∝ r 2 .
R r
Mass of water to be called is ∝ r 3
So cooling efficiency is ∝ r 2 /r 3 = 1/r .
Smaller the r , better is the cooling efficiency!
So scale down r.
MOS Transistors
MOS Device Scaling
Other examples in general
Small animals like earthworms etc. have simple, straight

digestive and respiratory paths. Larger animals have coiled
intestines, lungs with sac structure etc. – Why?
Absorption of food or oxygen is ∝ surface area ∝ size2 .
Requirement for food or oxygen is ∝ body mass ∝ size3 .
Absorption of nutrients and oxygen per unit tissue mass
decreases as size becomes larger.
So larger animals have evolved to increase the surface area of

digestive and respiratory membranes beyond what would be
provided by simple scaling, by developing structures like coiled
intestines and lungs with texture
MOS Transistors
MOS Device Scaling
Grandma’s story
Remember the story that grandma used to tell about the giant
who was ten times taller, ten times broader and ten times fatter
than a human being?
And how terrified were we of this creature!
Well, we need not have worried about the giant.

The area of cross section of the giant’s bones is 100 times
compared to us, but its weight is 1000 times our weight. So the
stress on the bone material is 10 times higher than us.
The giant will break its bones every time it tries to get up and
chase us!!
By the way, this is the reason that elephants have

disproportionately thick legs. An elephant which is just a scaled
up version of a dog will not survive!
MOS Transistors
MOS Device Scaling
Back to MOS Devices!
We need to scale depletion widths in the same ratio as W

and L. This is essential in order to scale down the
separation between transistors and to control channel
length modulation due to drain voltage.
This requires doping densities to be scaled up by the same
factor as the one used to scale down W and L.
So we define a scaling factor S, and reduce W, L, junction
depths and oxide thicknesses etc. by this factor.
Doping densities need to be increased by factor S.
All working voltages and the Threshold voltage VT need to
be scaled down by S.
Once this scaling is done, we are interested in evaluating the
impact on the circuit performance.
MOS Transistors
Consequences of Scaling
We assume classical or Constant Field scaling.
Device Area: Since W reduces by ↓ S and L reduces by ↓ S,
the area reduces by ↓ S 2 .
Packing Density: For a given chip area, the number of devices
which can be packed in this chip will go up by ↑ S 2 .
Cox : The gate capacitance per unit area is given by
ǫ/tox . Since tox scales down by ↓ S, Cox increases
by ↑ S. Cox determines the transconductance, so
this increase is good.
Load capacitance: All dimensions, including depletion widths
have been scaled down by ↓ S. Total capacitance
= ǫA/t. Now A reduces by ↓ S 2 , while the
dielectric thickness (be it oxide or depletion width)
reduces by ↓ S. The net effect is that total
capacitance = ǫArea ↓ S 2 /t ↓ S reduces by ↓ S.
MOS Transistors
Voltages: All voltages such as VDS , VGS , VT etc. are scaled

down by ↓ S to keep the field constant.
Drain current: IDS is given by µCox (W /L)f (VDS , VGS , VT ).
Since all voltages are scaled down by ↓ S and f is
a square function of voltages both in linear mode
and saturation, f will scale down as ↓ S 2 . Thus,
IDS = µCox (↑ S)(W ↓ S/L ↓ S)f (VDS , VGS , VT )(↓ S 2 )
So combining all dependencies, IDS ↓ S.

MOS Transistors
Slew Rate: Slew rate is the rate of change of voltage at any
node. Since I = C dV dt , the slew rate goes as
I(↓ S)/C(↓ S). Thus slew rate remains unchanged
with scaling.
Delay: Delay is given by the total voltage change divided
by dV
dt . Since all voltages are scaled down by ↓ S,
while dVdt remains unchanged, the delay reduces
as ↓ S.
Static Power: It is given by V × I . So it scales as (↓ S)(↓ S),
that is ↓ S 2 .
Dynamic Power: Dynamic power is given by Ctotal V 2 f . This
scales as (↓ S)(↓ S 2 )(↑ S) Thus dynamic power
reduces as ↓ S 2 even when the frequency of
operation is increased by ↑ S to take advantage of
shorter delays, which scale down by (↓ S).
MOS Transistors
Classical Constant Field Scaling: All dimensions and voltages
divided by the factor S(> 1).
Device area ∝ W × L : (↓ S)(↓ S) ↓ S2
Cox ǫox /tox : const/(↓ S) ↑S
Ctotal 2
ǫA/t : (↓ S )/(↓ S) ↓S
VDS , VGS , VT Voltages : (↓ S) ↓S
Id µCox (W /L)(∝ V ) :2
(↑ S)(const)(↓ S 2 ) ↓S
dV
Slew Rate dt I/Ctotal : (↓ S)/(↓ S) const.
Delay V / dV
dt : (↓ S)/(const) ↓S
Static Power V × I : (↓ S)(↓ S) ↓ S2
dynamic power Ctotal V f : (↓ S)(↓ S )(↑ S) ↓ S 2
2 2
Power delay product delay × power(↓ S)(↓ S 2 ) ↓ S3

Power density 2 2
power/area : (↓ S )/(↓ S ) const.
MOS Transistors
Impact of scaling
Improved packing density: ↑ S 2

Improved speed: delay ↓ S
Improved power consumption: ↓ S 2
So, circuit performance improves dramatically with transistor
scaling. This provides the motivation for making transistors as
small as possible.
What are the limits on scaling?
These come from processing technology limitations, device
limitations and circuit considerations such as reduced signal to
noise ratio due to reduced supply voltages.
MOS Transistors
Moore’s “Law”
In 1965, Gordon Moore, the co-founder of Fairchild
Semiconductor as well as Intel, described a doubling every
year in the number of components per integrated circuit.
It is an observation of a trend and an empirical relationship
– not a physical or natural law! However, given the
prominence of Gordon Moore, it is widely referred to as
Moore’s Law.
In 1975, Moore modified his observation for the rate of
device scaling and predicted a doubling of device density
every two years.
It is remarkable that this trend has continued over several
decades. It is only in the last decade that the rate of
doubling has slowed down remarkably, as we hit several
physical limits.
MOS Transistors
Theoretic Analysis of MOS scaling
Device scaling started initially as an empirical observation.

The theoretical basis of constant field device scaling was
laid down in a landmark paper in 1974 from a group of
scientists from IBM.
R.H. Dennard, F. H. Gaensslen, Hw A-Nien Yu, V. L.

Rideout, E. Bassous, and A. R, LeBlanc, “Design of
Ion-Implanted MOSFETs with Very Small Physical
Dimensions”, IEEE Journal of Solid-State Circuits, Vol.
SC-9, No. 5, pp. 256-268, 1974.
This is one of the most quoted papers in this field. I
strongly recommend that you read it – for its contents, but
also to learn from its style of technical writing.
MOS Transistors
The technology road map
The incredible rate of increase in circuit performance has

been possible through careful planning.
The semiconductor industry used Moore’s prediction for
setting specific targets for development in process
technology, processing equipment and for research and
development in critical areas of device Physics.
The result of this planning was the creation of an
International Technology Road map for Semiconductor
Scaling – or ITRS.
ITRS has been revised every year till recently. A new ITRS
has not been issued after 2016.
MOS Transistors
The λ rules
It is hard to track and scale the optimum size of numerous
structures on an Integrated circuit.
It is common to describe feature sizes in units of a
parameter called λ.
Now sizes of various structures can be described in units
of λ.
As we scale technologies, we just scale the value of λ.
Feature sizes remain the same in units of λ. This is
convenient.
The smallest feature on a chip is the contact window. The
value of λ is so defined that the smallest feature size is 2λ.
The smallest registration rule – for example the extent to
which a contact window must be inside a diffused region –
is λ.
MOS Transistors
The technology road map
As a result of careful planning and the considerable financial

rewards of improved MOS technology, feature sizes have been
continually scaled.
The table below gives the commonly used channel lengths by
the year in various decades.
1971 10 µm 1974 6 µm 1977 3 µm
1981 1.5 µm 1984 1 µm 1987 800 nm
1990 600 nm 1993 350 nm 1996 250 nm 1999 180 nm
2001 130 nm 2003 90 nm 2005 65 nm 2007 45 nm 2009 32 nm
2012 22 nm 2014 14 nm 2017 11 nm
The scaling rate has slowed down after 2010. This is because
feature sizes had already reached about 20 nm – about 3% of
the wavelength of sodium light!
MOS Transistors
Demand from Processing Technology

Circuit performance improves dramatically with transistor
scaling. This provides the motivation for making transistors as
small as possible.
What demands does it place on processing technology?
Scaling requires much higher resolution in defining
geometries. Size of the finest patterns in the state of the
art technologies is about 10nm. This is about a fiftieth of
the wavelength of sodium light!
Advanced photo-lithographic techniques need to be used
to define such fine geometries. We need deep UV
lithography and even XRay lithography to define such fine
structures.
Etching techniques have to be improved to define such fine
structures. Dry etching using plasma or reactive ion
etching is used rather than wet chemical etching to define
MOS Transistors
Evolution of Photolithography: DSW

As a result of the need for defining incredibly fine structures on
the chip, the art of photolithography has evolved over time.
Contact mask photolithography was replaced by Direct
Stepping on Wafer (DSW).
Here the feature size on the mask is much bigger – say 5X
or 10X. So mask making is easier. A reduced image is
formed optically on the wafer.
The image size is much smaller due to optical reduction. At
the same time wafer sizes have been increasing.
Therefore the image has to be printed many times by
moving the wafer in steps.
Thus the step-and-repeat process used for making masks
has been carried over to each photolithography step on
wafer.
MOS Transistors
Evolution of Photolithography: Deep UV and XRay
As feature sizes became smaller and smaller, DSW was unable

to provide the kind of resolution which was required using the
commonly used Mercury G line.
To get higher resolution, we need shorter wave lengths. Mask

illumination moved from G line to Indigo line or I line. When
even that was not adequate, Ultraviolet light was used.
UV lithography is challenging. Ordinary optical components are

not transparent to UV. Special materials have to be used –
some of these materials are hygroscopic and need careful
protection from the atmosphere!
To get even higher resolution, XRay lithography was used.

MOS Transistors
From Optical lithography to e-Beam
conventional optics and imaging is not possible with

XRays. The masks had to be 1X again. So the masks had
to be made with some new process. Electron beams were
used to make these masks.
Specialized photoresists such as poly methyl methacrylate
(PMMA) and their developing chemicals were required for
eBeam lithography.
Eventually, lithography moved to direct writing on wafer
using electron Beams.
This required development of advanced e-Beam optics
using electro-magnetic deflection!
MOS Transistors
Evolution of Etching techniques: Plasma and RIE

It is not enough to define a fine pattern on photoresist. This
pattern has to be transferred to the silicon wafer by etching
some material, Which could be SiO2 , silicon nitride,
polysilicon or metal.
Conventional chemical etching is not directional. So a fine
pattern on photoresist may be washed out due to
undercutting by a non-directional etch.
Etchant Etchant
Resist Resist
Metal Metal
Etchant Pattern washout
Resist Resist
undercut
Metal
MOS Transistors

To define fine patterns with high aspect ratios, we need
directional etching.
Directional etching may be provided by several physical
processes, such as plasma etching or reactive ion etching.
In plasma etching, we form a plasma in a low pressure gas
using RF. Ions in the plasma are accelerated using a DC
field. The accelerated ions can dislodge atoms of the
material being etched. Now the etching will proceed along
the direction of the DC field – so high aspect ratios may be
achieved without undercutting.
Purely physical etching techniques have the problem that
these are not material selective. Therefore determining
when to stop etching may become critical.
Some material selectivity may be provided by Reactive Ion
Etching, which is directional as well as selective.
MOS Transistors

To have a robust process, etching should stop as soon as
we strike a material different from the one which was being
etched.
While Plasma etching provides highly directional etching, it
is not very material selective.
To get material selectivity, we need to etch using a
chemical reaction, which takes place only with a given
material. This is why wet chemical etching is so selective.
We can combine the two properties by using Reactive Ion
Etching (RIE). Here, the acceleration of gas ions just
provides the energy of reaction. Etching is due to this
reaction, not due to physical dislodging of atoms.
So material selectivity may be obtained by Reactive Ion
Etching, which is also directional – because accelerated
ions will not move sideways to attack the just exposed side
MOS Transistors
Demand from Processing Technology
Oxide thickness needs to be scaled down, as well. It is

very difficult to make such thin oxides without pin holes
and leakage problems. In modern processes, high
dielectric constant insulators replace SiO2 as the gate
oxide to provide higher Cox , rather than using impractically
thin SiO2 .
Junction depths need to be much shallower. This requires
precise low energy ion implantation and much lower
thermal budgets for the process.
To define fine geometries on top of the lower layers which
may have steps, planarization using Chemical Mechanical
Polishing (CMP) has to be used for metal layers.
MOS Transistors
Limits of scaling
Limits of scaling
Scaling is being limited now due to several reasons.
We are reaching limits of resolution possible with
photo-selective processes and etching etc.
Traditional Device Physics is not valid any more for such
small structures. Remember, the lattice constant of Silicon
is ≈ 0.5 nm. So there are as few as 20 atoms between
source and drain of a 10 nm channel MOSFET. Clearly,
conduction models based on statistics will not hold here.
Indefinite voltage scaling is not possible. If the voltage is
scaled down drastically, signal to noise ratio will become
poor and leakage currents will become dominant as KT /q
has not been scaled and current equations of junctions
involve qV /KT .
System considerations such as interconnect delay will limit
performance gain.
MOS Transistors
Limits of scaling
Unscaled Interconnect Delay
Interconnect Design
The chip designer has no control over material properties

such as the resistivity of metal or the dielectric constant of
insulator between metal layers.
Structural parameters – such as the thickness of metal
layer or the thickness of inter-metal dielectric are also
chosen by the process designer.
The length of the interconnect is also not a design
parameter.
The only parameters that a chip designer may choose are
the layer in which to run the interconnect and the width of
the wire.
Typically, the upper layers offer thicker metal, but lower
packing density.
MOS Transistors
Limits of scaling
Concerns in Interconnect Design
Concern: Interconnect Delay
L LW
R=ρ , C=ǫ
L Wtm ti
tm W
ti L2
Charge Time ≈ RC = ρǫ
tm ti
To first order, delay is independent of W.
This is because increasing W reduces resistance but
increases capacitance in the same ratio.
Unfortunately W is about the only parameter that the circuit
designer can decide! (L is fixed by the distance between
the points to be connected, ρ, ǫ, tm and ti are decided by the
technology).
MOS Transistors
Limits of scaling
Concerns in Interconnect Design
Concern: Interconnect Delay

Relative Frequency
Local interconnects scale with device size.

Global interconnects scale with die size.
Normalized Wire length
ρǫ 2
Interconnect Delay = tm ti L ≡ AL2
For local interconnects, L scales the same way as tm , ti ,
so delay is invariant.
For Global Interconnects, L goes up with die size, while tm and
ti scale down. This leads to a sharp increase in delay.
MOS Transistors
Limits of scaling
Solutions for Interconnect Delay problem
Buffer Insertion
Global Interconnect delay can be the determining factor for the

speed of an integrated system.
The L2 dependence of interconnect delay is a source of

particular concern.
This problem can be somewhat mitigated by buffer insertion in

long wires.
We define some critical wire length and when a wire segment

exceeds this length, we insert a buffer.
MOS Transistors
Limits of scaling
Repeater Insertion in Voltage Mode
Length = L’ Length = L’ Length = L’

Let the total wire length be L, with
n − 1 repeaters. Hence each
segment has a length L′ = Ln
Segment wire delay = AL′2 .
Let buffer delay = τ
For n segments, there will be n-1 buffers. n = L/L′ .

L L
∆ = (n − 1)τ + nAL′2 = − 1 τ + ′ AL′2
L′ L

L
= − 1 τ + ALL′
L′
What is the optimum wire length after which we should place a

buffer?
MOS Transistors
Limits of scaling
Optimal Buffer Insertion
We can differentiate the delay expression with respect to L′ and

equate it to zero to get the optimum value of L′

L d∆ L
∆ = − 1 τ + ALL′ So = − ′2 τ + AL = 0
L ′ dL ′ L
L
Thus AL = τ And so, AL′2 = τ
L′2
Thus the optimum choice for L′ is such that the segment delay
AL′2 should be equal to buffer delay τ .
∆ = (n − 1)τ + nAL′2 = (2n − 1)τ
Total delay is now proportional to n and so, is linear in L.

MOS Transistors
Breakdown Phenomena
Avalanche Breakdown
GATE
SOURCE p DRAIN The drain channel junction is reverse

n+ e- n+
h+ e+
-
biased.
h
S D Parasitic NPN
In saturation region, there is a high field
Bipolar Transistor region next to the drain.
Channel
If the field exceeds some critical value, carrier

multiplication will occur, leading to avalanche breakdown.
Carrier multiplication near drain results in a sharp increase
in drain current. This is the avalanche breakdown of the
transistor.
MOS Transistors
Breakdown Phenomena
Avalanche Breakdown
Multiplication produces excess

GATE
electron-hole pairs.
SOURCE p DRAIN
n+ e-
-
n+ Electrons are collected by the positively
h+ e+
h biased drain.
S
Holes drift towards the source and
D Parasitic NPN
Bipolar Transistor
Channel constitute a “base current” for the parasitic
lateral npn transistor, turning it ON.
If the parasitic bipolar turns ON due to the base current
provided by the drifting holes from the drain junction, its
current will be added to the MOS drain current.
The additional current due to the bipolar action, combined
with carrier multiplication near the drain can result in early
breakdown of the transistor.
MOS Transistors
Breakdown Phenomena
Punch Through
If the channel is very short, at high drain

GATE voltages, the depletion region due to the
SOURCE p DRAIN drain-substrate junction can reach the
n+ e- n+
h+ e+
-
source.
h
S
Due to the drain field, the source/substrate
D Parasitic NPN
junction will get forward biased and will
Bipolar Transistor
Channel
inject current into the channel, even if the
gate voltage is below VT .
This is an extreme case of drain induced barrier lowering.
It results in heavy current flow even though the transistor is
supposed to be ‘OFF’.
This is known as “Punch Through”
MOS Transistors
Parasitic Devices
Parasitic Devices: Field transistors
Field A MOS like structure exists between

Diffusion Line
Diffusion Line
Oxide
TOP VIEW unrelated diffusion areas due to metal

Metal Line
lines crossing over unrelated diffusion
areas.
Cross Section Metal Line
This is known as a “Field Transistor”.
Field
Oxide
It can turn on, shorting the unrelated
Diffusion Diffusion
diffusion lines if the metal line is at a high
Parasitic Field Transistor
enough potential.
Voltages much higher than VDD can occur in a MOS circuit
due to charge pumping effects.
Doping levels and field oxide thickness have to be chosen
so that this parasitic device never turns ON.
MOS Transistors
Parasitic Devices
Parasitic Devices: Latch up structure

nMOS pMOS n Well
Output
(Metal)
The figure on the
VDD Input
left shows a badly
Poly Poly
Input Output
VDD (Metal)
laid out inverter.
(Metal) cross section
through this line While the lay out
VDD
Gnd
Substrate does form an
Contact nMOS source pMOS source Well Contact
R well
inverter as
Vertical PNP
p+ n+ p+ n+
p n
desired, it also
Vertical PNP
p substrate n Well
Horizontal
NPN
Horizontal
forms a parasitic
p substrate
NPN latch-up structure.
This pnpn structure is like a thyristor which can turn on,

shorting VDD to ground and destroying the IC due to the
resulting heavy current.
MOS Transistors
Parasitic Devices
A vertical pnp transistor is formed by . . .

nMOS pMOS n Well
Output
1 the p+ source of a pMOS
VDD Input (Metal)
transistor connected to VDD
Poly Poly
Input Output
VDD (Metal)
(which becomes the emitter),
Gnd
through this line
2 the n well (which becomes the
VDD
Substrate
R well Contact nMOS source pMOS source Well Contact base), and
Vertical PNP
p+ n+ p+ n+
p n
3 the p substrate (which
Vertical PNP
p substrate n Well
Horizontal
NPN
Horizontal
NPN
p substrate becomes the collector of this
transistor).
The n well is connected to VDD through a resistive path, which
represents the resistance of the n well to the well contact.
MOS Transistors
Parasitic Devices

A horizontal npn transistor is formed by . . .
nMOS pMOS n Well
VDD Input
Output
(Metal)
1 the n+ source of an nMOS
Input Output
Poly Poly transistor connected to ground
(Metal)
VDD (Metal)
cross section (which becomes the emitter),
through this line
VDD Gnd
Substrate
2 the p substrate, (which
R well
Vertical PNP
p+ n+ p n p+ n+ becomes the base), and

Vertical PNP
p substrate n Well
Horizontal
NPN Horizontal
3 the n well, (which becomes
p substrate
NPN
the collector).
Since the collector of the npn and the base of the pnp are
both formed by the n well, these two are connected.
Similarly, the collector of the pnp and the base of the npn
are formed by the p substrate, so these are also
connected.
MOS Transistors
Parasitic Devices

The latchup structure forms a positive feedback loop.
Substrate contact n source
Gnd Gnd
p source
VDD
Well contact
VDD
An increase in the base current of the pnp
p+ n+ n+ p+ p+ n+ will be amplified by its βp and a large part
p substrate
n well
of it will flow through the base emitter
junction of the npn transistor.
Rwell
Vertical pnp This part will be amplified by the βn of the
npn and a substantial part of it will go
Rsub
horizontal npn
through the base emitter junction of the
pnp transistor.
If the product of the two amplification factors βp and βn and the
current division ratios between the resistors and the base
emitter junctions exceeds 1, the currents will keep increasing
due to this feedback, till there is a dead short between VDD and
ground.
MOS Transistors
Parasitic Devices
Preventing Latch up
Substrate contact n source p source Well contact

Gnd Gnd VDD VDD
p+ n+ n+ p+ p+ n+ The positive feedback phenomenon which

p substrate
n well
shorts VDD to ground is known as latchup.
Rwell
To prevent it, we must ensure that the
Vertical pnp product of s βp , βn and the current division
ratios between the resistors and the base
Rsub
horizontal npn
emitter junctions never exceeds 1
We must reduce the β of both the parasitic bipolar transistors
and make sure that most of the collector current of either
transistor is directed to the resistor and not to the base-emitter
junction of the other transistor.
MOS Transistors
Parasitic Devices
Preventing Latch up
Latchup prevention requires care in process design, as well as
in layout rules.
nMOS pMOS n Well
VDD Input
Output
(Metal)
The doping gradient of the n well should
Input Output
Poly Poly
VDD (Metal)
be made retrograde. (Doping should
VDD Gnd
Substrate
through this line
increase as we go deeper). This kills the
current gain βp of the pnp transistor.

R well
Vertical PNP
p+ n+ p n p+ n+
Vertical PNP
p substrate n Well
Horizontal
NPN Horizontal
NPN
p substrate
The n well should be deep to kill the gain
Substrate contact n source
Gnd Gnd
p source
VDD
Well contact
VDD of the pnp transistor.
p+ n+ n+ p+ p+ n+
n well
n channel transistors should be placed far
p substrate
from the edge of the n well to increases
Rwell the base width of npn transistors and
Vertical pnp
reduce their current gain.
horizontal npn Rsub p channel transistors should also be
placed far from the well edge.
MOS Transistors
Parasitic Devices
Preventing Latch up
Substrate contact n source p source Well contact
Gnd Gnd VDD VDD
The n well should have a guard ring
p+ n+ n+ p+ p+ n+
n well connected to VDD , which will collect any
p substrate
current which could form the base current
Rwell of the pnp.
Vertical pnp
In layout, substrate and well contacts
horizontal npn Rsub should be placed frequently to reduce the
value of Rwell and Rsubstrate .
Normally, the n well is connected to VDD and the p well is
connected to ground. Thus there is no forward bias for emitter
base junctions and bipolar action is prevented.
However, if layout rules are not observed, latch up may be
triggered by stray currents from junctions near avalanche, or
due to exposure to light etc.

01 MOS Lecture

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

01 MOS Lecture

Uploaded by

Copyright:

Available Formats

MOS Transistors

Parallel Plate Capacitor

The parallel plate capacitor

If we place a charge Q on the upper plate, it attracts charges of

Parallel Plate Capacitor

The two capacitor plates hold equal and + + + + + + + + Q

Parallel Plate Capacitor

Since there are no charges inside the dielectric,

So the electric field in the insulator is constant. The electrostatic

The MOS Capacitor

What happens if we replace the lower metal

The MOS Capacitor

As an example, let the semiconductor be P type silicon,

The MOS Capacitor

Let us see what happens if we place a positive charge on the

The MOS Capacitor

The positive charge on the upper plate

The MOS Capacitor

The MOS Capacitor

The MOS Capacitor

What will happen to the capacitance when inversion occurs?

Low frequency Capacitance of The MOS Capacitor:

For all incremental negative charge on the top plate, the

Low frequency Capacitance of The MOS Capacitor:

Small Positive Bias: Accumulation Inversion

For a small positive DC bias on the Depletion

For all incremental positive charge on the top plate, the

Low frequency Capacitance of The MOS Capacitor:

For all incremental positive charge on the top plate, the

Frequency dependence of MOS Capacitance

MOS inversion capacitance at High frequency

We apply bias at DC (so that equilibrium conditions may be

MOS inversion capacitance at High frequency

If the superimposed AC signal is changing

MOS inversion capacitance at High frequency

MOS inversion capacitance at High frequency

MOS capacitance at Low and High frequency

Low Frequency High Frequency

Consider a one dimensional representation of the MOS

The origin is at the silicon-oxide

We consider the ideal case first. Assume that

We construct a Gaussian box passing through

Quantitative Analysis: Solution of Poisson’s Equation

We can write the Poisson’s equation in the semiconductor as

where E is the electrostatic field.

Quantitative Analysis: Solution of Poisson’s Equation

Changing the variable from x to φ.

Quantitative Analysis: Solution of Poisson’s Equation

The right hand side of the Poisson’s equation

where p0 and n0 represent the hole and electron density in the

Nd+ − Na− = −(p0 − n0 )

Quantitative Analysis: Solution of Poisson’s Equation

The Poisson’s equation in the semiconductor is

Integrating and putting limits at 0 and u, we get

Quantitative Analysis: Evaluation of D

So the displacement vector D can be evaluated as:

This equation permits us to calculate D, given the value of u. In

Quantitative Analysis: Debye Length

Quantitative Analysis: Debye Length

For an unperturbed semiconductor, u = 0 everywhere.

Quantitative Analysis: Semiconductor Charge

Total Semiconductor Charge = Area × (−D)

Quantitative Analysis: Semiconductor Charge

Defining Qsi to be the charge in the semiconductor per unit