AN126

Product Description
Description Continued
The Future of Analog IC Technology

How to Loading & Writing a

Configuration File into MTP for MP2940A

Application Note

Prepared by Reagan Luo/Marvin Ma

September 04, 2017

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ABSTRACT
This document tells user how to load the MP2940A configuration file and save it into the MTP in
DOS/WINDOWS environment.
CONDITION
Connect VDD33 pin to 3.3V power supply;
Pull PE pin high;
Pull EN pin low.
It’s not suggested to load configuration file when EN pin is high.

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INDEX
Configuration File Format ......................................................................................................................... 4
PMBus Protocol ........................................................................................................................................ 7
Start and Stop Frame ............................................................................................................................... 7
Acknowledge Bit ....................................................................................................................................... 8
Transmission Structure ............................................................................................................................. 8
PMBus Register List ............................................................................................................................... 11

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CONFIGURATION FILE FORMAT

While using MPS’s digital GUI to optimize the design, an EXCEL format configuration file is generated.
This file contains address and value information of the configurable registers.

An example of configuration file is shown as Table 1. It contains 6 columns:

1) Device Address: PMBus address of this MP2940A chip; 00h is the “All call’’ address. MP2940A
always responds to this address.
2) Command code: register address in the memory of MP2940A.
3) Command name: name of the register.
4) Byte: byte number of the register. 2 represents that it needs the word type command to read or
write. 1 represents that it needs the byte type command to read or write.
5) WR: whether this register supports to be written or read. Read only registers can’t be stored into
MTP. All the registers exported by the GUI can be written and read.
6) Register Value: accessed by sending command 0x00 with 8’h00 firstly; these registers are for
operation and system operation;

Table 1 example of configuration file

Device Command
Command name Byte W/R Register value
Address code

0x20 0x00 PAGE 1 WR -

0x20 0x01 OPERATION 1 WR 8’h80

0x20 0x21 VOUT_COMMAND 2 WR 16’h007e

0x20 0x22 VOUT_TRIM 2 WR 16’h0000

0x20 0x23 VOUT_CAL_OFFSET 2 WR 16’h0000

0x20 0x24 VOUT_MAX 2 WR 16’h00ff

0x20 0x25 VOUT_MARGIN_HIGH 2 WR 16’h0000

0x20 0x26 VOUT_MARGIN_LOW 2 WR 16’h0000

0x20 0x2E MFR_PLATFORM_TIME 2 WR 16’h0004

0x20 0x35 VIN_ON 2 WR 16’he838

Figure 1 shows the configuration process for MP2940A.

It should turn to the right page before configuring the registers.
Send Command 0x00 with Data of 8’h00 before writing or reading registers;

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MP2940A has a password check mechanism to prohibit terminal user invade the configuration data. So
before loading configure file, please make sure password is right. You should read MFR_INPUT_
PASSWORD (0x51), and judge whether present system password(0x50) is correct before the below
operation.
Storing all the registers to MTP or restoring from MTP can be done both in page0 and page1, i.e.
sending 0x15 and 0x16 will make effect in any page.
Before the regular configure process, it should be checked that if the PMBus address and the Configure
ID in the configure file match with the MP2940A chip.
After the regular configuration process, it is required to read STATUS_CML (0x7E) to check if the writing
process is totally correct. Bit 4 and Bit 0 of 0x7E should be both zero after restoring from MTP, or it
means storing or restoring MTP is not successful. If PMBUS transmission without PEC, it’s also needed
to read back from MTP and compare register values with the configure file. Table 2 shows the bit
definition.

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START

MP2940A VDD33 pin= 3.3V

PE pin=3.3V, EN pin=0V

Wait 1ms, for the MTP data to be

loaded to registers

Fault 1: PMBUS address wrong.

PMBus address check Double check the address setting
No of EC

Yes

Register 7Eh bit[4] = 0 ?

No

Yes

Fault 2: NVM CRC fault Register C1h bit[8:0] Yes

Register C0h bit[15:0] Yes
Send command 0x03 with no match configure file?
match configure file?
data on page 1

No No
4‐digit code does not match, code rev does not match,
need MTP re‐program need MTP re‐program

Input Password: 51h=xxh

Restore data from MTP

Regular load excel configuration file Send command 0x16 with no data
to all registers on page1

Store data to MTP Wait 1ms

Send command 0x15 with no data
on page1

Read back all register values and ready to

Wait 250ms compare with the excel configure file

Fault 2: NVM CRC fault

Send command 0x03 with no Register 7Eh bit[4] = 0 ?
data on page 1
No
If retry 1 time fail, it need Yes
replace MP2940A

All Match ?
If retry 1 time fail, check the process,
maybe the programming wrong or read No
wrong data Yes

Successful
programming, proceed
to system start‐up

(End step)
Figure 1: PMBUS register writing sequence

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The object of “Regular Load Configure to Registers” step is to set registers of page0 in the memory
(volatile) of the chip to the desired value in the EXCEL file. This process can be done by writing each
register one by one manually, but it would be easy to make mistakes. Therefore it suggests writing
registers automatically through software with just loading the EXCEL file like the MPS GUI.
The 250ms waiting time is derived from estimation. Because writing one byte of the MTP will cost 0.5ms
(typ.) if the writing value is different from its current value, or will cost 1us (min.) if the value is the same.
The MTP in MP2940A has 256 bytes. We keep a margin for safety.

PMBUS PROTOCOL
MP2940A’s PMBUS SCL, SDA and ALT# pin need external pull-up to 3.3V. Figure 2 shows an example
implementation of PMBUS devices connecting on the bus. When the bus is idle, the voltage of the bus is
3.3V. When each device on the bus wants to talk, it will pull the bus low. Only the Master has the ability
to drive the SCL bus.

Figure 2: PMBUS topology

START AND STOP FRAME

Figure 3: start and stop condition

1) A high to low transition of sda line while scl is high indicates a message start condition;
2) A low to high transition of sda line while scl is high defines a stop condition.

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3) Start and stop conditions are generated by master. After a start condition, the bus is considered to
be busy. The bus becomes idle again certain time later after stop condition.

ACKNOWLEDGE BIT
Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an acknowledge bit.
The acknowledge-related clock pulse is generated by the master. The slave device must always
acknowledge (ACK) when the address is targeted or receiving the valid command or address. In order to
acknowledge a byte, the slave must pull the SDA line low during the clock pulse. If the slave should not
acknowledge, it should not do anything during the clock pulse. The default state of SDA line is high
during this period.

data output
by master
MSB
NACK
data output
by slave ACK

scl S 1 2 7 8 9

Clock pulse
start For acknowledgement

Figure 4: ACK and NACK signal

TRANSMISSION STRUCTURE
MP2940A accommodate any mixture of devices that support Packet Error Checking and devices that do
not. The PEC uses an 8-bit cyclic redundancy check (CRC-8,g=8'h07) of each read or write bus
transaction to calculate a Packet Error Code (PEC). A NACK received after a PEC by a
master-transmitter indicates that the slave-receiver became aware of an error with the transmission in
time to supply a NACK at the end of the PEC byte. This may be due to an incorrect PEC or any other
error. So MP2940A supports 10 kinds of the transmission structure.
1) Send command only;
2) Write byte;
3) Write word;
4) Read byte;
5) Read word;
6) Send command only with PEC;
7) Write byte with PEC;
8) Write word with PEC;
9) Read byte with PEC;
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10) Read word with PEC;
Details see Figure 5:

Figure 5: supported PMBUS transmission structure without PEC

Figure 6: supported PMBUS transmission structure with PEC

MP2940A detects the following transmission errors (see Table 2):

1. Sending too few bits; set bit1 (other fault) of STATUS_CML.
2. Reading too few bits; set bit1 (other fault) of STATUS_CML.
3. Master sends or reads too few bytes; set bit1 (other fault) of STATUS_CML.
4. Master reads too many bytes; set bit1 (other fault) of STATUS_CML.
5. Improperly Set Read bit in the address byte; set bit1 (other fault) of STATUS_CML.
6. One or more bit error when Sending bits, set bit5 (PEC error) of STATUS_CML.

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7. Master sends too many bytes; set the bit6 (invalid/unsupported data received) of the
STATUS_CML register.
8. Unsupported Command Code; set bit7 (invalid/unsupported command received) of the
STATUS_CML

Table 2 Transmission Errors

STATUS_CML
Bit 7 Invalid/unsupported command
Bit 6 Invalid/unsupported data
Bit 5 PEC error
Bit 4 MTP CRC error/MTP write fail
Bit 3 Reserved
Bit 2 Reserved
Bit 1 Other communication fault
Bit 0 MTP signature fault

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PMBUS REGISTER LIST
Table 3 an example of PMBUS register list
Device Command
Command name Byte W/R Register value
Address code
0x20 0x00 PAGE 1 WR 0x00
0x20 0x01 OPERATION 1 WR 0x80
0x20 0x1B IDROOP_CTRL 2 WR 0x0000
0x20 0x1D MFR_MTP_CTRL 2 WR 0x0000
0x20 0x1E PSYS_WARN_FILT_CNT 1 WR 0x00
0x20 0x21 VOUT_COMMAND 2 WR 0x0000
0x20 0x22 MFR_VOUT_TRIM 2 WR 0x0000
0x20 0x23 VOUT_CAL_OFFSET 2 WR 0x0000
0x20 0x24 MFR_VOUT_MAX 2 WR 0x0000
0x20 0x25 VOUT_MARGIN_HIGH 2 WR 0x0000
0x20 0x26 VOUT_MARGIN_LOW 2 WR 0x0000
0x20 0x2B MFR_IMMEDIATE_SET 2 WR 0x002F
0x20 0x2E MFR_PLATFORM_TIME 2 WR 0x0000
0x20 0x30 MFR_APSI_CTRL 2 WR 0x03F6
0x20 0x35 VIN_ON 2 WR 0xE800
0x20 0x36 VIN_OFF 2 WR 0xE800
0x20 0x38 IOUT_CAL_GAIN 2 WR 0x0000
0x20 0x39 IOUT_CAL_OFFSET 2 WR 0xF800
0x20 0x3A MFR_IMON_SVID1 2 WR 0x0080
0x20 0x3B MFR_IMON_SVID2 2 WR 0x0080
0x20 0x3C MFR_IMON_SVID3 2 WR 0x7E80
0x20 0x50 MFR_SYS_PASSWORD 1 WR 0x00
0x20 0x51 MFR_INPUT_PASSWORD 1 WR 0x00
0x20 0x55 VIN_OV_FAULT_LIMIT 2 WR 0xE800
0x20 0x58 VIN_UV_WARNING_LIMIT 2 WR 0xE800
0x20 0xB8 MFR_VIN_HYS 1 WR 0x20
0x20 0xBB MFR_1PHL_HYS 2 WR 0x0000
0x20 0xBD PROTOCOL_ID_SVID_RDY_VR 2 WR 0x0000
0x20 0xBE PS3_PS4_EXIT_DELAY 2 WR 0x0000
0x20 0xBF VENDOR_ID_PRODUCT_ID 2 WR 0x0000
0x20 0xC0 PRODUCT_DATA_CODE_VR 2 WR 0x0000
0x20 0xC1 LOT_CODE_VR 1 WR 0x00
0x20 0xC2 DECAY_CFG_34H_36H 2 WR 0x0000
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Device Command
Command name Byte W/R Register value
Address code
0x20 0xC3 TOLERANCE_SR_FAST 2 WR 0x0000
0x20 0xC4 MFR_VOUT_MAX_9BIT 2 WR 0x0000
0x20 0xC5 IVID2_1_I_DEF 2 WR 0x0000
0x20 0xC6 PIN_MAX_IVID3_I_DEF 2 WR 0x0000
0x20 0xCA MFR_PHASE_NUM 1 WR 0x02
0x20 0xCC DC_CTRL_DYNAMIC_FLT 2 WR 0x0000
0x20 0xCD MFR_SW_HF_SET 2 WR 0x0000
0x20 0xCE MIN_ON_OFF_BLANK_TIME 2 WR 0x0000
0x20 0xCF MFR_SW_LF_SET 2 WR 0x0000
0x20 0xD6 MFR_SLOPE_SR_3P 2 WR 0x0000
0x20 0xD7 MFR_SLOPE_CNT_3P 2 WR 0x0000
0x20 0xD8 MFR_SLOPE_SR_2P 2 WR 0x0000
0x20 0xD9 MFR_SLOPE_CNT_2P 2 WR 0x0000
0x20 0xDA MFR_SLOPE_SR_1P 2 WR 0x0000
0x20 0xDB MFR_SLOPE_CNT_1P 2 WR 0x0000
0x20 0xDC MFR_SLOPE_SR_DCM 2 WR 0x0000
0x20 0xDD MFR_SLOPE_CNT_DCM 2 WR 0x0000
0x20 0xDE MFR_TRIM_2_1_DCM 2 WR 0x0000
0x20 0xDF MFR_TRIM_3 2 WR 0x0000
0x20 0xE1 SHUTLEVEL_ADDRPMBUS 2 WR 0x0000
0x20 0xE2 MFR_CB_SATU_PI 2 WR 0xB50A
0x20 0xE3 MFR_VCAL_PI 1 WR 0x1A
0x20 0xE4 MFR_VR_CONFIG 2 WR 0x2C50
0x20 0xE5 MFR_FS_VBOOT 2 WR 0x10A1
0x20 0xE6 MFR_ADDR_SVID 2 WR 0x0030
0x20 0xE8 TEMPERATURE_GAIN_OFFSET 2 WR 0x500A
0x20 0xE9 MFR_CUR_GAIN 2 WR 0x00FD
0x20 0xEA MFR_CUR_OFFSET 1 WR 0x50
0x20 0xEB MFR_CS_OFFSET1_2 2 WR 0xFE01
0x20 0xEC MFR_CS_OFFSET3 2 WR 0xFD00
0x20 0xEE MFR_OCP_SET 2 WR 0x0735
0x20 0xEF MFR_ICC_MAX 1 WR 0xFF
0x20 0xF0 MFR_VOUT_CMPS_MAX 2 WR 0xFF15
0x20 0xF1 UVP_OVP12_OCP_MODE 2 WR 0x7F53
0x20 0xF2 MFR_OTP_SET 2 WR 0x4B1E

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Device Command
Command name Byte W/R Register value
Address code
0x20 0xF3 MFR_TEMP_MAX 1 WR 0x7D
0x20 0xF5 MFR_AUDIBLE_REDUCE 2 WR 0x0020
0x20 0xF6 OCP_OVP_DA_LIMIT 2 WR 0xFFFF
0x20 0xF7 MFR_OVP_UVP_SET 2 WR 0x0294
0x20 0xF8 MFR_VID_DOWN_DELAY 2 WR 0x0055
0x20 0xF9 MFR_FILTER_SET 2 WR 0xC8D1
0x20 0xFA MFR_TRANS_FAST 2 WR 0x1A43
0x20 0xFB MFR_EN_DLY 2 WR 0x0385
0x20 0xFC MFR_PSYS_SVID 2 WR 0x0080
0x20 0xFD MFR_ALT_SET 2 WR 0x0803

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