Higher Technological Institute 10° of Ramadan City 6‘ of October Branch Electrical and Computer Engineering Department Lecture Notes in EEC 151 Electronics 3 Under Supervision Dr. Mahmoud Mohamed Lecture 6Course Contents & <3) 2 | e MOS inverter & & Electronics 3 32 Higher Technological InstituteNoise Margins UO What is noise? Anything that degrades the signal *E.g., re: stance, power supply noise, coupling to neighboring wires, etc. Driving device Receiving device Output Input Characteristics vy; Characteristics Logical high —, ——————_—_ Togeal high output range: NM, === | input range Vow min ¥ 7 Indeterminate region $ Memon Logical low Logical low —— NM, 4 —-E input range output range— ————— es GND Electronics 3 34 Higher Technological InstituteNoise Margins con OQ V,,,= minimum HIGH output voltage Vg, = maximum LOW output voltage NM, = —Vor Q V,,= minimum HIGH input voltage AM = Vou ~P QV, = maximum LOW input voltage Output Characteristics, Input Characteristics oo Logical High * BEE *- a Output eet Vor ae fam m= Viv | Indeterminate Va} Region nn Logical Low Logical Low Vor Input Range Output Range See GND Electronics 3 32 Higher Technological InstituteNoise Margins con 40V nv 5 < Output voltage OV 10¥ 20V 3.0V 40V 5.0V vy QO) Noise margins are defined by the regions shown in the given figure Electronics 3 33 Higher Technological InstitutePropagation delay The propagation delay . . i Up, Input Voltage waveform Vpn. is the time the inverter takes to U respond to a change at its input Yop Rising time Interval between the 10% and 90% amplitude points on the leading edge. } Output Voltage! i waveform | Falling time Interval between the 90% and 10% amplitude points on the trailing edge. The propagation delay tp = Hera leess Electronics 3 34 Higher Technological InstitutePower in Circuit Elements EO) _ aye F(t) E = falar nar= for (yar oe 1 dt Ye = cf (nar =1cr? a Electronics 3 * Vere fc =C dVidt 36 Higher Technological InstituteCharging a Capacitor 1 When the gate output rises = Energy stored in capacitor is an gpl Vp Eo =3CV ap Hl ™ But energy drawn from the supply is. Vy fj i Vout . fH ‘ Bee Fino = [1 tVoostt = Jr tls To -CFoe | dV =CVin = Half the energy from Veo is dissipated in the PMOS transistor as heat, other half stored in capacitor 1) When the gate output falls = Energy in capacitor is dumped to GND = Dissipated as heat in the NMOS transistor Electronics 3 37 Higher Technological InstituteSMI Nae on TI Q) Energy consumed in one switching cycle (Ts = 1/fa,): Esw = CrV5p Q Average switching power (a.k.a. dynamic power): sw E, = = 2 Pay = 5 = CV Bh = Quadratic dependence on Vpp = Linear dependence on fiw Electronics 3 38 Higher Technological Institute