Dept.

of Electronics and Electrical Communication Engineering Indian

Institute of Technology Kharagpur

VLSI LABORATORY (EC39002)

Experiment - 6
Date of submission: 04-03-2024

Instructor: Group Members:

Prof. Gourab Dutta Name: Akash Ganeriwal
Roll Number: 21EC30063
Name: Aditya Varshney
Roll Number: 21EC10089
Objective-1:
Design a CMOS inverter and plot its VTC using LTSpice. Investigate the effect of PMOS and NMOS widths on
the VTC and the switching threshold. What is the impact of VDD on the VTC (check even when VDD < |VTh|)?
Plot the current characteristics of a CMOS inverter.

Circuit Diagrams:

a) For plotting the VTC:

b) For investigating the effects of PMOS and NMOS widths on the VTC and the switching threshold:

c) For checking the impact of Vdd on VTC:

Plots and Observations:
a) Plotting the VTC of the Inverter:

è PMOS Width = 2um, NMOS Width = 1um.

b) Effects of device widths on the VTC and the switching threshold:

è The above plot is for varying PMOS width against a constant NMOS width = 1um.
è We observed that the switching threshold shifts to a larger value as we increase the width of PMOS.
è The above plot is for varying NMOS width against a constant PMOS width = 2um.
è We observed that the switching threshold shifts to a smaller value as we increase the width of NMOS.

c) Impact of Vdd on VTC:

è We observed that the range of voltage (w.r.t. Vdd) for which both PMOS and NMOS remains in saturation
region decreases, attains a minimum and further increases as we decrease the Vdd.
è We observed that the inverter preserved its VTC even when the Vdd < |VTh|.

Objective-2:
For the CMOS inverter, estimate its propagation delay when no load is connected. Examine the effect of the
PMOS/NMOS ratio on the propagation delay. Find the PMOS/NMOS ratio for which the delay is minimum.
Now, could you connect a variable load capacitor at the output node and investigate the delay?

Circuit Diagrams:
a) Circuit for estimating propagation delay:
b) Circuit for examining the effect of PMOS/NMOS ratio on the propagation delay:

c) Circuit for investigating the delay for variable load capacitor:

d) Circuit for calculating ‘gamma’:

e) Circuit for calculating Cin

f) Circuit for calculating Rep,p / Req,n :

Plots and Observations:

a) Plots for estimating the propagation delay:

è For estimation we considered the PMOS/NMOS ratio = 2.
è Propagation Delay = (tPLH + tPHL) / 2 = ((30.172 – 30.15) + (10.064 – 10.05)) / 2 = 0.018ns = 18ps

b) Plot for examining the effect of PMOS/NMOS ratio on the propagation delay:

è We observed that the propagation delay increases as we increase the PMOS/NMOS ratio.

c) Plot of delay for variable capacitor:

è We observed that the propagation delay increases as we increase the value of load capacitor.

d) Plot for calculating ‘gamma’:

è For estimation we considered the PMOS/NMOS ratio = 2.

è Propagation Delay = (tPLH + tPHL) / 2 = ((30.194 – 30.15) + (10.083 – 10.05)) / 2 = 0.0385ns = 38.5ps
!"#$
è We know that, tp = tpo (1 + ) = tpo (1 + 1/g)
g!%&
è Implies that, g = 0.878

e) Plot for calculating Cin:

è For estimation we considered the PMOS/NMOS ratio = 2.
è Propagation Delay = (tPLH + tPHL) / 2 = ((30.364 – 30.15) + (10.233 – 10.05)) / 2 = 0.1985ns = 198.5ps
!"#$
è We know that, tp = tpo (1 + g!%& )
è Implies that, Cin = 0.0114 pF

f) Plot for calculating Rep,p / Req,n :

è For estimation we considered the PMOS and NMOS to be unit width.
è Propagation Delay = tPLH = 0.69 * Req,p *(Cself + Cext.) = 30.178 – 30.15 = 0.028ns = 28ps
è Propagation Delay = tPHL = 0.69 * Req,n *(Cself + Cext.) = 10.058 – 10.05 = 0.008ns = 8ps
è We know r = Req,p / Req,n = tPLH / tPHL = 28/8 = 3.5
è We know, for minimum propagation delay PMOS/NMOS ratio = √𝑟 = 1.871

Discussion:

Objective – 1:

1. Effect of PMOS and NMOS Widths on VTC and Switching Threshold:

• As expected, wider transistors (PMOS and NMOS) tend to decrease the resistance
and hence improve the switching speed of the CMOS inverter.
• Increasing the width of the PMOS transistor shifts the switching threshold towards
the positive voltage range, while increasing the width of the NMOS transistor
shifts it towards the negative voltage range.
• This behavior can be explained by considering the relative strength of the pull-up
and pull-down networks in the CMOS inverter. A wider PMOS transistor enhances
the pull-up strength, leading to a higher switching threshold, and vice versa for the
NMOS transistor.

2. Impact of VDD on VTC:

• Varying the supply voltage (VDD) affects the VTC in several ways. Increasing
VDD leads to a wider input voltage range for which the CMOS inverter operates in
the saturation region.
• At lower VDD values, the VTC curve may exhibit asymmetry due to unequal
operating regions of the PMOS and NMOS transistors. This can result in non-ideal
switching behavior and reduced noise margins.
• When VDD approaches or falls below the threshold voltage of the transistors, the
CMOS inverter may fail to operate properly, leading to unpredictable behavior.

3. Current Characteristics:
• Plotting the current characteristics of the CMOS inverter reveals the dynamic
behavior of the transistors during switching.
• During the transition from logic low to logic high (or vice versa), the PMOS and
NMOS transistors conduct current simultaneously, resulting in a short-circuit
current path between VDD and ground. This phenomenon, known as shoot-
through current, causes power dissipation and limits the maximum achievable
switching speed.

Objective – 2:

1. Estimation of Propagation Delay Without Load:

• Propagation delay without load primarily depends on the intrinsic capacitances

and resistances of the transistors.
• By considering the rise and fall times using the RC time constant formula, we
estimated the propagation delay.
• The propagation delay is the sum of the rise and fall times, which represent the
time taken for the output to transition from one logic level to another.

2. Effect of PMOS/NMOS Ratio on Propagation Delay:

• Varying the PMOS/NMOS ratio allows us to adjust the pull-up and pull-down
strengths of the CMOS inverter, influencing the propagation delay.
• By simulating the CMOS inverter with different PMOS and NMOS transistor
widths, we observed how the propagation delay changes.
• We aimed to find the PMOS/NMOS ratio for which the propagation delay is
minimized, indicating optimal performance.

3. Investigation with Variable Load Capacitance:

• Connecting a variable load capacitor at the output node enables us to analyse

the impact of load capacitance on the propagation delay.
• Increased load capacitance slows down the charging and discharging processes,
leading to longer propagation delay.
• By simulating the CMOS inverter with varying load capacitance values, we
observed how the propagation delay varies under different load conditions.
• This investigation is crucial for understanding the tolerance of CMOS circuits
to load variations and optimizing circuit performance accordingly.